CN109585452B - Memory and manufacturing method thereof - Google Patents
Memory and manufacturing method thereof Download PDFInfo
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- CN109585452B CN109585452B CN201811492899.8A CN201811492899A CN109585452B CN 109585452 B CN109585452 B CN 109585452B CN 201811492899 A CN201811492899 A CN 201811492899A CN 109585452 B CN109585452 B CN 109585452B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The application provides a memory and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: and providing a first wafer, wherein a groove is formed in a position, corresponding to a position where a metal bonding pad is formed subsequently, on the first wafer, and the depth of the groove is greater than or equal to the thickness of the thinned first wafer, so that after the first wafer is thinned, the groove on the first wafer is punched through to form a wafer through hole penetrating through the first wafer. Therefore, after the metal bonding pad is formed subsequently, the wafer through hole penetrating through the first wafer is arranged at the position corresponding to the metal bonding pad, the area of the wafer opposite to the metal bonding pad is reduced, the parasitic capacitance between the first wafer and the metal bonding pad is reduced, the groove can be formed through one-time etching, the depth does not need to be strictly controlled, the process window is enlarged, the mode of reducing the parasitic capacitance is easier to control, and the requirement on process control precision is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a memory and a manufacturing method thereof.
Background
In a novel 3D NAND product architecture, a memory Cell area (Cell) and a peripheral area (CMOS) are manufactured on different wafers, circuits are connected together through a three-dimensional special process, a wafer where the Cell is located is thinned from the back, and then the circuits are connected.
Usually, a plurality of pads are arranged in the edge area of the 3D NAND chip to connect out the internal circuit of the chip, but when the pads and the internal wafer of the 3D NAND chip have current flowing at the same time, a strong parasitic Capacitance (CIO) is generated, which slows down the speed of operation and storage.
Therefore, reducing the parasitic capacitance between the wafer and the bonding pad inside the 3D NAND chip becomes a technical problem to be solved in the 3D NAND manufacturing process, and the 3D NAND manufacturing process for reducing the parasitic capacitance adopted in the prior art is difficult to control and has a high requirement on process precision.
Disclosure of Invention
In view of this, the present invention provides a memory and a manufacturing method thereof, so as to solve the problems in the prior art that the manufacturing process for reducing the parasitic capacitance is difficult to control and the requirement on the process precision is high.
In order to achieve the purpose, the invention provides the following technical scheme:
a memory fabrication method, comprising:
providing a first wafer, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged; a groove is formed in the position, on the first surface of the first wafer, of the metal bonding pad of the memory to be formed, and the depth of the groove is larger than or equal to the thickness of the thinned first wafer;
forming a first insulating layer on the first surface, the first insulating layer filling the groove;
forming a plurality of through array contact parts on the surface of the first insulating layer, wherein orthographic projections of the through array contact parts on the first wafer are positioned in the grooves;
thinning the first wafer from the second surface of the first wafer, so that the groove forms a wafer through hole penetrating through the thinned first wafer;
forming a second insulating layer on the surface of the thinned first wafer, which is far away from the first surface;
forming a plurality of through array through holes in the groove, wherein the through array through holes are arranged in one-to-one correspondence to the through array contact parts and penetrate through the second insulating layer and the first insulating layer to reach the through array contact parts;
forming a through contact in the through array via;
and forming a metal pad on the surface of the second insulating layer, wherein the metal pad covers all the through array through holes in the groove.
Preferably, the providing the first wafer specifically includes:
providing a complete first wafer;
and forming the groove at the position of the first surface of the first wafer where the metal pad is to be formed.
Preferably, the forming a plurality of penetrating array contacts on the surface of the first insulating layer specifically includes:
forming a plurality of first grooves on the surface of the first insulating layer in regions corresponding to the grooves;
and filling a plurality of first grooves with conductive materials to form a plurality of penetrating array contact parts.
Preferably, the method further comprises the following steps:
providing a second wafer;
forming a memory array on the second wafer;
and bonding the first wafer and the second wafer, and electrically connecting the through array contact part on the first wafer with the memory array on the second wafer.
The present invention also provides a memory comprising:
the wafer structure comprises a first wafer and a second wafer, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged, and a wafer through hole which penetrates through the first wafer;
the insulating layer is filled in the wafer through hole and covers the first surface and the second surface of the first wafer, and the insulating layer comprises a third surface and a fourth surface which are oppositely arranged;
a plurality of through array contacts disposed within the third surface;
a metal pad disposed within the fourth surface;
the wafer through hole is internally provided with a plurality of through array through holes filled with through contact parts, the through contact parts are in one-to-one correspondence electrical connection with the through array contact parts, and the through contact parts are in electrical connection with the metal pad.
Preferably, an orthographic projection of the metal pad on the first wafer overlaps the through wafer via.
Preferably, an orthographic projection of the metal pad on the first wafer covers the wafer through hole or is superposed with the wafer through hole or is positioned in the wafer through hole.
Preferably, a through silicon contact is further included through the first wafer.
Preferably, the through contact portion and the through array contact portion are made of the same material.
Preferably, a second wafer is also included;
a storage array is formed on one surface of the second wafer;
the second wafer is bonded on the first surface of the first wafer, and the memory array is electrically connected with the through contact part on the first wafer.
As can be seen from the above technical solutions, the method for manufacturing a memory according to the present invention includes: and providing a first wafer, wherein a groove is formed in a position, corresponding to a position where a metal bonding pad is formed subsequently, on the first wafer, and the depth of the groove is greater than or equal to the thickness of the thinned first wafer, so that after the first wafer is thinned, the groove on the first wafer is punched through to form a wafer through hole penetrating through the first wafer. Therefore, after the metal bonding pad is formed subsequently, because the position corresponding to the metal bonding pad is the wafer through hole penetrating through the first wafer and the area of the wafer opposite to the metal bonding pad is reduced, the parasitic capacitance between the first wafer and the metal bonding pad is reduced, the groove can be formed through one-time etching, and the depth is not required to be strictly controlled.
The invention also provides a memory, and the wafer through hole penetrating through the first wafer is formed at the position of the first wafer where the metal bonding pad is arranged, so that the dead area of the first wafer and the metal bonding pad is reduced, and further parasitic capacitance can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a cross-sectional view of a memory provided in the prior art;
FIG. 2 is a process flow diagram of a method for fabricating a memory according to an embodiment of the present invention;
fig. 3-9 are schematic process steps of a memory manufacturing method according to an embodiment of the invention.
Detailed Description
As described in the background section, the 3D NAND fabrication process for reducing parasitic capacitance in the prior art is difficult to control and has high requirements for process precision.
The reason why the above phenomenon occurs is found in the present invention, please refer to fig. 1, in which fig. 1 is a schematic cross-sectional structure diagram of a memory; the memory comprises a silicon substrate 01, insulating layers 03 formed on two sides of the silicon substrate 01, metal routing lines 06 formed inside the silicon substrate 01, Through Silicon Contact (TSC) 05 penetrating through the substrate, and Through Array Contact (TAC) 04 electrically connected with the TSC05, wherein a protective layer 07 is further arranged on the surface of the memory structure. In a partial region of the protective layer 07, a metal pad 02 is formed, and the metal pad 02 is used for connecting a circuit inside the memory to a chip.
When current flows through the metal pad 02 and the silicon substrate 01 simultaneously, a plate capacitor, that is, a parasitic capacitor described in the background section, is formed between the silicon substrate 01 and the metal pad 02. Due to the parasitic capacitance, the speed of operation storage is reduced.
The inventor finds that: the fundamental reason for the parasitic capacitance is that a plate capacitor is formed between the metal pad and the silicon substrate when current passes through the plate capacitor, and the size of the plate capacitor is according to the formula:
and determining that d is the thickness of the insulating layer between the lower surface of the metal pad and the upper surface of the silicon substrate, please refer to fig. 1, and S is the overlapping area of the metal pad and the silicon substrate. The inventors' current method of reducing parasitic capacitance is: by strictly controlling the thickness of the insulating layer between the metal bonding pad and the silicon substrate, the parasitic capacitance is reduced, and the storage speed is prevented from being reduced. The method for controlling the thickness of the insulating layer specifically comprises the following steps: the thicker insulating layer is formed on the silicon substrate in a growing mode, the thickness of the insulating layer is reduced through multiple times of etching, in the etching process, the uniformity and the thickness need to be controlled, and the thickness of the insulating layer also needs to be controlled through controlling the etching precision of the insulating layer. The etching end point is difficult to control in process, so that the thickness of the insulating layer is difficult to control, and if deviation occurs in the process, the internal circuit of the 3D NAND memory may be broken or leaked. And the uniformity of the insulating layer is difficult to control each time, and the etching of the insulating layer needs to be carried out for multiple times, so that the thickness of the insulating layer is difficult to control.
Moreover, while the internal circuit of the memory is connected, the insulating layer 03 and the silicon substrate 01 after the back surface of the silicon substrate is thickened must be opened, while the parasitic capacitance is reduced by increasing the thickness (to more than 1.4 μm) of the insulating layer 3 between the silicon substrate 01 and the metal pad 02, the subsequent punching is caused, and the aspect ratio of the hole is increased in the process of filling metal to form the TSC, particularly, the aspect ratio of the TSC is increased because the diameter of the punching is not changed and the depth is increased, thereby greatly increasing the difficulty of the process. And after the thickness of the insulating layer 03 is increased, the cost for depositing the insulating layer is increased, and meanwhile, as the depth-to-width ratio of the TSC is increased, a more advanced machine is required to be used for realizing, and the process cost is also increased.
Accordingly, an embodiment of the present invention provides a method for manufacturing a memory, including:
providing a first wafer, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged; a groove is formed in the position, on the first surface of the first wafer, of the metal bonding pad of the memory to be formed, and the depth of the groove is larger than or equal to the thickness of the thinned first wafer;
forming a first insulating layer on the first surface, the first insulating layer filling the groove;
forming a plurality of through array contact parts on the surface of the first insulating layer, wherein orthographic projections of the through array contact parts on the first wafer are positioned in the grooves;
thinning the first wafer from the second surface of the first wafer, so that the groove forms a wafer through hole penetrating through the thinned first wafer;
forming a second insulating layer on the surface of the thinned first wafer, which is far away from the first surface;
forming a plurality of through array through holes in the groove, wherein the through array through holes are arranged in one-to-one correspondence to the through array contact parts and penetrate through the second insulating layer and the first insulating layer to reach the through array contact parts;
forming a through contact in the through array via;
and forming a metal pad on the surface of the second insulating layer, wherein the metal pad covers all the through array through holes in the groove.
The memory manufacturing method provided by the invention comprises the following steps: and providing a first wafer, wherein a groove is formed in a position, corresponding to a position where a metal bonding pad is formed subsequently, on the first wafer, and the depth of the groove is greater than or equal to the thickness of the thinned first wafer, so that after the first wafer is thinned, the groove on the first wafer is punched through to form a wafer through hole penetrating through the first wafer. Therefore, after the metal bonding pad is formed subsequently, because the position corresponding to the metal bonding pad is the wafer through hole penetrating through the first wafer and the area of the wafer opposite to the metal bonding pad is reduced, the parasitic capacitance between the first wafer and the metal bonding pad is reduced, the groove can be formed through one-time etching, and the depth is not required to be strictly controlled.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a method for manufacturing a memory structure, please refer to fig. 2, which includes:
s101: providing a first wafer, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged; a groove is formed in the position, on the first surface of the first wafer, of the metal bonding pad of the memory to be formed, and the depth of the groove is larger than or equal to the thickness of the thinned first wafer;
the specific structure of the memory structure is not limited in the embodiments of the present invention, and in one embodiment of the present invention, the memory structure may be a 3D NAND memory structure. The 3D NAND memory structure is formed by manufacturing a memory Cell area (Cell) and a peripheral area (CMOS) on different wafers, and then connecting circuits together through a three-dimensional special process. Therefore, the first wafer provided in this embodiment is a wafer for forming a peripheral structure, which includes but is not limited to a CMOS structure, and during the process of manufacturing the 3D NAND, a second wafer for forming a memory array may be further provided.
Referring to fig. 3, the first wafer 1 provided in the present embodiment has a groove 11 formed on one surface thereof, and the second wafer 2 does not need to have a groove. After forming the peripheral structure on the first wafer 1 and forming the memory array on the second wafer, the first wafer and the second wafer are bonded by a hybrid bonding process, and specifically, the through array contact portion of the peripheral structure on the first wafer is electrically connected with the memory array on the second wafer.
In the embodiment of the present invention, the material of the first wafer and the second wafer is not limited, and optionally, in the embodiment of the present invention, the material of the first wafer and the material of the second wafer are the same and are both silicon wafers. It should be noted that, in other embodiments of the present invention, the first wafer and the second wafer may also be a silicon-on-insulator substrate or other wafer structure materials, which is not limited in this embodiment.
Because a metal pad is required to be formed on the surface of the first wafer, which is away from the second wafer, to connect the circuit inside the 3d nand memory to the outside of the memory, in order to reduce the parasitic capacitance between the metal pad and the first wafer, in this embodiment, a groove is formed on the first wafer at a position corresponding to the metal pad, and the depth of the groove is greater than or equal to the thickness of the thinned first wafer, so as to form a through hole penetrating through the thinned first wafer, so that the area of the first wafer corresponding to the metal pad is reduced compared with the prior art, and the parasitic capacitance between the metal pad and the first wafer can be reduced.
It should be noted that, in this embodiment, the size of the groove is not limited, but in order to reduce the parasitic capacitance and reduce the area of the first wafer opposite to the metal pad, in this embodiment, the projection of the metal pad on the first wafer, on which the 3D NAND memory is to be formed, coincides with the outline of the groove or is located in the groove. That is, by removing the wafer material in the region corresponding to the metal pad on the first wafer in the prior art, the facing area of the metal pad and the first wafer is reduced, and the parasitic capacitance between the metal pad and the first wafer is further reduced.
In other embodiments of the present invention, the contour of the groove may also be set inside the projection contour of the metal pad on the first wafer, so as to reduce the parasitic capacitance between the metal pad and the first wafer as long as the facing area between the metal pad and the first wafer can be relatively reduced compared to the prior art. However, in this case, the area between the projection profile of the metal pad on the first wafer and the groove profile needs to be strictly controlled, so that the parasitic capacitance can be greatly reduced, and a better effect is achieved. Therefore, in the embodiment of the present invention, it is more preferable that a projection of the metal pad on the first wafer coincides with an outline of the groove or is located in the groove.
In addition, in other embodiments of the present invention, there may also be overlap between the groove and the metal pad, that is, the edge profile of the groove and the edge profile of the metal pad are all crossed, and as long as the overlapping area of the groove and the metal pad is smaller than the facing area of the first wafer and the metal pad in the prior art, the size of the parasitic capacitance can also be reduced to a certain extent.
In this embodiment, the specific process of providing the first wafer is not limited, and may specifically include: providing a complete first wafer, and forming the groove at a position where a metal pad is to be formed on the first surface of the first wafer after the complete first wafer is provided, wherein the groove is etched on the surface of the first wafer where a peripheral structure is to be formed by an etching process in the process of forming the groove. In other embodiments of the present invention, the mask may also be formed by a wet etching process, which is not limited in this embodiment. In this embodiment, a layer etched by first masking a wafer is referred to as a ZERO layer, that is, a groove is formed in the ZERO layer in this embodiment.
S102: forming a first insulating layer on the first surface, the first insulating layer filling the groove;
fig. 4 is a partial schematic view of the first wafer, and only the positions of the metal pads to be formed on the first wafer 1 are selected for illustration in this embodiment, and other portions of the first wafer are not shown in the figure.
As shown in fig. 4, the first wafer 1 comprises a silicon substrate on which grooves 11 are provided. Due to the fabrication of the peripheral structure, a first insulating layer 13 is further formed on the surface of the silicon substrate on which the peripheral structure is formed, and the first insulating layer 13 fills the groove 11 and covers the first surface. In this embodiment, the specific material of the insulating layer is not limited, and in the embodiment of the present invention, the material of the first insulating layer may be an oxide, particularly silicon oxide.
S103: forming a plurality of through array contact parts on the surface of the first insulating layer, wherein orthographic projections of the through array contact parts on the first wafer are positioned in the grooves;
with reference to fig. 4, the specific process of fabricating the through array contact includes:
forming a plurality of first grooves on the surface of the first insulating layer 13 in regions corresponding to the grooves;
the plurality of first recesses are filled with a conductive material to form a plurality of through array contacts 12. In the present embodiment, a partial structure of the peripheral device is represented by a Through Array Contact (TAC) 12.
S104: thinning the first wafer from the second surface of the first wafer, so that the groove forms a wafer through hole penetrating through the thinned first wafer;
please refer to fig. 5, which is a schematic structural diagram of the thinned first wafer deviating from the surface of the second wafer; wherein, the surface of the first wafer is thinned at least to the bottom of the groove 11, so that the groove forms a through wafer hole 111 penetrating through the first wafer for the subsequent process to be completed.
In this embodiment, the process used for thinning the first wafer is not limited, and optionally, in this embodiment, a CMP (chemical mechanical polishing) process is used to remove the excess silicon substrate and thin the first wafer.
It should be noted that, in this embodiment, the first insulating layer 13 is filled in the groove, the first insulating layer 13 and the silicon substrate 1 are made of different materials, and a clear boundary is formed between the first insulating layer 13 and the silicon substrate 1, so that whether the first wafer is ground to the bottom of the groove can be determined by detecting a signal change of grinding in CMP, thereby simplifying detection of the first wafer thinning endpoint.
S105: forming a second insulating layer on the surface of the thinned first wafer, which is far away from the first surface;
referring to fig. 6, after thinning the first wafer and before forming the metal pads, growing a thicker second insulating layer 14 is further included. The second insulating layer 14 grown in this embodiment is used to protect the first wafer.
S106: forming a plurality of through array through holes in the groove, wherein the through array through holes are arranged in one-to-one correspondence to the through array contact parts and penetrate through the second insulating layer and the first insulating layer to reach the through array contact parts;
the first insulating layer 13 and the second insulating layer are etched at the wafer through hole 111 to form a through array through hole 15, and TAC12 forming a peripheral structure on the first wafer is exposed, so that metal is filled subsequently, and the 3D NAND internal circuit is connected to an external TSC structure.
Referring to fig. 7, the region outside the metal pad to be formed further includes other grooves 16 for etching the second insulating layer 14 and exposing TAC in other regions of the first wafer after thinning.
S107: forming a through contact in the through array via;
referring to fig. 8, metal is filled into all the grooves in fig. 7 to form TSCs 17 connected to the TAC on the other surface of the first wafer.
S108: and forming a metal pad on the surface of the second insulating layer, wherein the metal pad covers all the through array through holes in the groove.
Referring to fig. 9, metal pads 18 and metal traces 19 are formed on the TSCs 17 to connect circuits inside the 3D NAND to the outside of the 3D NAND.
Finally, a protective layer 110 is formed in a region outside the metal pad 18, in this embodiment, the material of the protective layer 110 is not limited, and optionally, the protective layer 110 is silicon nitride.
The memory manufacturing method provided by the invention comprises the following steps: and providing a first wafer, wherein a groove is formed in a position, corresponding to a position where a metal bonding pad is formed subsequently, on the first wafer, and the depth of the groove is greater than or equal to the thickness of the thinned first wafer, so that after the first wafer is thinned, the groove on the first wafer is punched through to form a wafer through hole penetrating through the first wafer. Therefore, after the metal bonding pad is formed subsequently, because the position corresponding to the metal bonding pad is the wafer through hole penetrating through the first wafer and the area of the wafer opposite to the metal bonding pad is reduced, the parasitic capacitance between the first wafer and the metal bonding pad is reduced, the groove can be formed through one-time etching, and the depth is not required to be strictly controlled.
Fig. 9 shows a cross-sectional view of a portion of a memory according to an embodiment of the invention; the memory includes: a first wafer 1, wherein the first wafer 1 includes a first surface 101 and a second surface 102 which are oppositely arranged, and a through wafer via 111 which penetrates through the first wafer 1; the insulating layer is filled in the through hole and covers the first surface and the second surface of the first wafer 1, and the insulating layer comprises a third surface and a fourth surface which are oppositely arranged; a plurality of through array contacts disposed within the third surface; a metal pad disposed within the fourth surface; the through wafer via 111 includes a plurality of through array vias filled with through contact portions, the through contact portions are electrically connected to the through array vias in a one-to-one correspondence, and the through contact portions are electrically connected to the metal pads.
Fig. 9 is a schematic cross-sectional view of a portion of a first wafer; the first wafer comprises a through array contact part 12 electrically connected with the storage array, an insulating layer filled on two surfaces of the first wafer 1, a through contact part 17 penetrating through the first wafer and electrically connected with the through array contact part 12; metal traces 19 and metal pads 18 on the surface of the first wafer facing away from the second wafer, and a protective layer 110 on the outer region of the metal pads 18.
It should be noted that, in this embodiment, specific materials of the metal pad 18 and the metal trace 19 are not limited, and in an embodiment of the present invention, the materials of the metal pad 18 and the metal trace 19 may be aluminum.
In this embodiment, the shapes of the through wafer via 111 and the metal pad 18 are not limited, and optionally, in an embodiment of the present invention, the shape of the metal pad 18 is a circle, the shape of the through wafer via 111 is also a circle, and the centers of the two circles are overlapped.
It should be noted that, the relationship between the outline of the metal pad 18 and the outline of the through wafer via 111 is not limited, the metal pad 18 may have a partial overlapping area with the thinned wafer, may not have an overlapping area, and may have a certain distance, as shown in fig. 9, a certain distance D is provided between the outer peripheral outline of the metal pad 18 and the inner diameter of the through wafer via 111, and a specific value of the distance D is not limited in this embodiment. When the inner diameter of the through hole is smaller, the reduction degree of the parasitic capacitance is not obvious, so that the parasitic capacitance does not meet the parasitic capacitance threshold of the 3D NAND; however, when the inner diameter of the through hole 111 is larger, the layout of other metal traces may be affected, and therefore, optionally, the distance D is in a range from 5 μm to 10 μm, inclusive.
The metal pad 18 in this embodiment may have a partial overlapping area with the thinned wafer, and may be an orthographic projection of the metal pad on the first wafer overlapping with the through hole of the wafer, where the overlapping in this embodiment may include: the orthographic projection of the metal bonding pad on the first wafer covers the wafer through hole or is superposed with the wafer through hole or is positioned in the wafer through hole. May also include: there is an offset between the center of the metal pad and the center of the through wafer via such that the metal pad is offset from the through wafer via but has a portion of overlap.
The metal pad 18 and the thinned wafer have no overlapping area in the embodiment, that is, the projection of the peripheral profile of the metal pad on the thinned wafer coincides with the shape of the through hole, that is, the shapes and the sizes of the metal pad and the through hole are completely the same, so that the facing area between the metal pad and the thinned wafer is 0, and the parasitic capacitance between the metal pad and the thinned wafer is reduced.
In addition, in the embodiment, the region outside the metal pad further includes a through silicon contact 16 penetrating through the first wafer, as shown in fig. 9, and electrically connected to the metal trace 19.
It should be noted that the memory provided in this embodiment may be a 3D NAND memory structure, and further includes: a second wafer; a storage array is formed on one surface of the second wafer; the second wafer is bonded on the first surface of the first wafer, and the memory array is electrically connected with the through contact part on the first wafer.
According to the memory provided by the embodiment of the invention, the through hole penetrating through the first wafer is formed at the position of the first wafer where the metal bonding pad is arranged, so that the facing area of the first wafer and the metal bonding pad is reduced, and further the parasitic capacitance can be reduced.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for fabricating a memory, comprising:
providing a first wafer, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged; a groove is formed in the position, on the first surface of the first wafer, of the metal bonding pad of the memory to be formed, and the depth of the groove is larger than or equal to the thickness of the thinned first wafer;
forming a first insulating layer on the first surface, the first insulating layer filling the groove;
forming a plurality of through array contact parts on the surface of the first insulating layer, wherein orthographic projections of the through array contact parts on the first wafer are positioned in the grooves;
thinning the first wafer from the second surface of the first wafer, so that the groove forms a wafer through hole penetrating through the thinned first wafer;
forming a second insulating layer on the surface of the thinned first wafer, which is far away from the first surface;
forming a plurality of through array through holes in the groove, wherein the through array through holes are arranged in one-to-one correspondence to the through array contact parts and penetrate through the second insulating layer and the first insulating layer to reach the through array contact parts;
forming a through contact in the through array via;
and forming a metal pad on the surface of the second insulating layer, wherein the metal pad covers all the through array through holes in the groove.
2. The method of claim 1, wherein the step of forming the memory further comprises the step of forming a dummy pattern,
providing the first wafer specifically includes:
providing a complete first wafer;
and forming the groove at the position of the first surface of the first wafer where the metal pad is to be formed.
3. The method according to claim 1, wherein forming a plurality of through array contacts on the surface of the first insulating layer comprises:
forming a plurality of first grooves on the surface of the first insulating layer in regions corresponding to the grooves;
and filling a plurality of first grooves with conductive materials to form a plurality of penetrating array contact parts.
4. The method of claim 1, further comprising:
providing a second wafer;
forming a memory array on the second wafer;
and bonding the first wafer and the second wafer, and electrically connecting the through array contact part on the first wafer with the memory array on the second wafer.
5. A memory, comprising:
the wafer structure comprises a first wafer and a second wafer, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged, and a wafer through hole which penetrates through the first wafer;
the insulating layer is filled in the wafer through hole and covers the first surface and the second surface of the first wafer, and the insulating layer comprises a third surface and a fourth surface which are oppositely arranged;
a plurality of through array contacts disposed within the third surface;
a metal pad disposed within the fourth surface;
the wafer through hole is internally provided with a plurality of through array through holes filled with through contact parts, the through contact parts are electrically connected with the through array contact parts in a one-to-one correspondence manner, and the through contact parts are electrically connected with the metal pad.
6. The memory of claim 5, wherein an orthographic projection of the metal pad on the first wafer overlaps the through wafer via.
7. The memory of claim 6, wherein an orthographic projection of the metal pad on the first wafer covers or coincides with or is located within the wafer via.
8. The memory of claim 5, further comprising through silicon contacts through the first wafer.
9. The memory of claim 7, wherein the through contact and the through array contact are the same material.
10. The memory of claim 7, further comprising a second wafer;
a storage array is formed on one surface of the second wafer;
the second wafer is bonded on the first surface of the first wafer, and the memory array is electrically connected with the through contact part on the first wafer.
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| CN111430360B (en) * | 2020-04-08 | 2023-09-29 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device and 3D NAND memory device |
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