US8664114B2 - Image sensor and method for fabricating the same - Google Patents

Image sensor and method for fabricating the same Download PDF

Info

Publication number
US8664114B2
US8664114B2 US13/742,714 US201313742714A US8664114B2 US 8664114 B2 US8664114 B2 US 8664114B2 US 201313742714 A US201313742714 A US 201313742714A US 8664114 B2 US8664114 B2 US 8664114B2
Authority
US
United States
Prior art keywords
upper portion
semiconductor substrate
dummy pattern
forming
metal pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US13/742,714
Other versions
US20130307035A1 (en
Inventor
Ki-Jun Yun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu HitekCo Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu HitekCo Ltd filed Critical Dongbu HitekCo Ltd
Assigned to DONGBU HITEK CO., LTD. reassignment DONGBU HITEK CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YUN, KI-JUN
Publication of US20130307035A1 publication Critical patent/US20130307035A1/en
Application granted granted Critical
Publication of US8664114B2 publication Critical patent/US8664114B2/en
Assigned to DB HITEK CO., LTD. reassignment DB HITEK CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: DONGBU HITEK CO., LTD.
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing

Definitions

  • Chip scale packaging, flip chips, and multichip modules are generally applied to a variety of electronic product categories such as mobile phones, hand-held computers, chip cards, and similar applications/devices.
  • Future applications of electronic devices may require relatively complicated elements supporting various functions, which often results in the chip area being required to be relatively large to meet demands.
  • This results in challenges with manufacturing yield of chips due to an integration of multifunctional devices, an increase in cost due to complexity of device implementation, and technical limitations.
  • wirings between subsystems may be challenging due to limitations in performance, multifunctionality, reliability and similar issues of micro-electronic systems. These factors may be critical performance bottlenecks for future integrated circuit generation.
  • a 3D integration technology may have significant potential to replace an embedded system on chip (SoC) technology.
  • SoC system on chip
  • a super-contact hole may serve as a pad and a normal contact hole may serve for connecting wirings that are simultaneously patterned on a single wafer.
  • the super-contact hole may have a diameter ranging from approximately 1 ⁇ m to 2 ⁇ m and a depth ranging from approximately 6 ⁇ m to 10 ⁇ m.
  • a non-super-contact hole may have a diameter ranging from approximately 0.1 ⁇ m to 0.3 ⁇ m and a depth ranging from approximately 1 ⁇ m to 2 ⁇ m.
  • FIGS. 1A to 1E are cross-sectional views illustrating a process of forming a super-contact, according to the related art.
  • an device isolation layer (not shown) may define an active region.
  • Unit elements (such as a PMOS transistor and an NMOS transistor including a source/drain junction part and a gate 50 formed on the active region and similar elements) may be formed on a semiconductor substrate 100 .
  • an interlayer dielectric layer 102 may be formed on the entire structure with the unit elements formed thereon.
  • a photoresist pattern 104 for a super-contact hole may be formed on the interlayer dielectric layer 102 . Then the interlayer dielectric layer 102 and the semiconductor substrate 100 may be etched by an etching process using the photoresist pattern 104 as an etching mask to form a super-contact hole 106 .
  • the photoresist pattern 104 may be removed through a strip process, and an insulation film 108 may be formed on the surface of the entire structure including the super-contact hole 106 .
  • the insulation film 108 may serve as a shielding insulation film of a super-contact to be formed later and may be formed of at least one of oxide series and nitride series.
  • the super-contact hole 106 may be filled with a conductive material (e.g. tungsten (W)) to form a conductive layer 110 .
  • a photoresist pattern 111 for a normal contact hole may be formed on an upper portion of the entire structure with the conductive layer 110 filled in the super-contact hole 106 .
  • the interlayer dielectric layer 102 may be etched through an etching process using the photoresist pattern 111 as an etching mask to form a normal contact hole 112 .
  • the photoresist pattern 111 for a normal contact is removed.
  • the insulation film 108 is formed after the formation of the super contact hole 106 .
  • the interlayer dielectric layer 102 may not be etched enough when forming the normal contact hole 112 , which may cause problems with an electrical connection to the active region.
  • the interlayer dielectric layer 102 needs to be etched deeper due to the insulation film 108 , a portion A in the interlayer dielectric layer 102 may not be etched enough, which may cause problems in the electrical connection to the active region.
  • embodiments provides an image sensor in which problems of electrical connections does not arise or are minimized without changing the etching depth in an interlayer dielectric layer when forming a normal contact hole.
  • Embodiments relate to a method for fabricating the same.
  • a method for fabricating an image sensor includes at least one of the following: (1) Forming a gate on a semiconductor substrate. (2) Forming spacers on both side walls of the gate and forming a dummy pattern spaced apart from the gate on an upper portion of the semiconductor substrate. (3) Forming a metal pad for an electrical connection on an upper portion of the dummy pattern. (4) Forming an interlayer dielectric layer covering substantially the entire semiconductor substrate having the metal pad for an electrical connection formed thereon. (5) Etching portions of the interlayer dielectric layer and the semiconductor substrate to form a super-contact hole. (6) Forming an insulation film on the entire surface of the interlayer dielectric layer having the super-contact hole formed thereon. (7) Forming normal contact holes such that a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection are exposed therefrom. (8) Filling the normal contact holes with a conductive material to form normal contacts.
  • the semiconductor substrate may be an epitaxial layer.
  • said forming a metal pad for an electrical connection may include forming a metal pad for an electrical connection that covers the entirety or a portion of the upper portion of the dummy pattern.
  • said forming a dummy pattern may include forming an oxide film for a spacer on an upper portion of the semiconductor substrate having the gate formed thereon and patterning a portion of the oxide film for a spacer to form the spacers and the dummy pattern spaced apart from the gate on an upper portion of the semiconductor substrate.
  • said forming a metal pad for an electrical connection may include depositing a metal material on the entire surface of the semiconductor substrate with the dummy pattern formed thereon and patterning the deposited metal material to form the metal pad for an electrical connection covering a partial region of an upper portion of the dummy pattern and a partial upper portion of the semiconductor substrate adjacent to the dummy pattern.
  • the insulation film may be formed by using a silicon nitride film or a silicon oxide film.
  • Embodiments relate to an image sensor including at least one of: (1) A gate formed on a semiconductor substrate and spacers formed on both side walls of the gate. (2) A dummy pattern formed spaced apart from the gate on an upper portion of the semiconductor substrate. (3) A metal pad for an electrical connection, which is configured to cover an upper portion of dummy pattern. (4) An interlayer dielectric layer substantially covering the entire semiconductor substrate having the gate and the metal pad for an electrical connection formed thereon. (5) Normal contacts formed to be connected to a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection. (6) A super-contact configured formed by etching portions of the interlayer dielectric layer and the semiconductor substrate.
  • the dummy pattern may be formed by patterning a portion of an oxide film deposited to form the spacers.
  • the metal pad for an electrical connection may be formed to have a structure that covers a portion of an upper portion of the dummy pattern and a partial upper portion of the semiconductor substrate adjacent to the dummy pattern.
  • the metal pad for an electrical connection may be formed to have a structure that covers the entirety or a portion of the upper portion of the dummy pattern.
  • the process for forming the super-contact hole and the normal contact hole may be performed.
  • the thickness of the interlayer dielectric layer is relatively large due to the insulation film formed on the super-contact hole, since the interlayer dielectric layer is etched only up to an upper portion of the metal pad for an electrical connection, the normal contact hole without the problem of an electrical connection may be formed without changing an etching depth.
  • FIGS. 1A to 1E are cross sectional views illustrating a process of forming a contact in accordance with the related art.
  • FIGS. 2A to 2F are cross sectional views illustrating a process of forming a contact of a CMOS image sensor in accordance with embodiments.
  • FIGS. 2A to 2F are cross sectional views illustrating a process of forming a contact of a CMOS image sensor, in accordance with embodiments.
  • an insulation layer and a polysilicon layer may be sequentially formed on an upper portion of a semiconductor substrate 200 and then patterned to form a gate insulation film 201 and a gate 202 , in accordance with embodiments.
  • An oxide film for a spacer may then be formed on/over substantially the entire surface having the gate 202 formed thereon and then patterned to form a spacer 204 at both side walls of the gate 202 and a dummy pattern 206 spaced apart from the spacer 204 on an upper portion of the semiconductor substrate 200 , in accordance with embodiments.
  • the dummy pattern 206 is a portion connected to a normal contact hole (to be formed later) and the semiconductor substrate 200 may be an epitaxial layer formed through a silicon growth process.
  • a barrier metal material for an electrical connection may be deposited and then patterned to form a metal pad 208 for an electrical connection on a partial region of an upper portion of the dummy pattern 206 .
  • the metal pad 208 for the electrical connection may be formed to cover the partial region of the upper portion or the entire region of the dummy pattern 206 or a partial region of the upper portion of the semiconductor substrate 200 adjacent to the dummy pattern 206 .
  • an interlayer dielectric layer 210 may be formed on the entire structure on/over the metal pad 208 for an electrical connection.
  • a photoresist pattern (not shown) for a super-contact hole may be formed on an upper portion of the interlayer dielectric layer 210 .
  • the interlayer dielectric layer 210 and the semiconductor substrate 200 may be etched through an etching process using the photoresist pattern as an etch mask to from a super-contact hole 212 .
  • the photoresist pattern may be removed through a strip process, in accordance with embodiments.
  • an insulation film 214 may be formed on/over the surface of the entire structure including the super-contact hole 212 .
  • the insulation film 214 may be formed of at least one of oxide series and nitride groups.
  • the insulation film 214 may be formed by sequentially depositing a silicon nitride film 214 a and a silicon oxide film 214 b.
  • the super-contact hole 212 may be filled with a conductive material (e.g. tungsten (W)), to form a super-contact 220 .
  • a photoresist pattern for a normal contact hole may be formed on the entire structure with the super-contact 220 formed thereon.
  • the interlayer dielectric layer 210 may be etched through an etching process using the photoresist pattern as an etch mask to form normal contact holes 216 .
  • the photoresist pattern for a normal contact hole and the photoresist layer for filling-up are all removed through a strip process, thus completing the super-contact 220 and the normal contact holes 216 .
  • the normal contact holes 216 may be formed to allow a partial upper portion of the metal pad 208 for an electrical connection and an upper portion of the gate 202 to be exposed therefrom.
  • a conductive material e.g., tungsten (W)
  • W tungsten
  • a chemical mechanical polishing (CMP) process may be performed by setting an upper portion of the insulation film 214 as a polishing stop point, to form normal contacts 230 , in accordance with embodiments.
  • the process of forming the super-contact hole 212 and the normal contact hole 216 is performed.
  • the etching thickness for forming the normal contact holes 216 i.e. the thickness obtained by adding each thickness of the insulation film 214 and the interlayer dielectric layer 210
  • the interlayer dielectric layer 210 is etched only up to the upper portion of the metal pad 208 for an electrical connection, which may result in normal contact holes 216 that do not have electrical connection problems.

Abstract

A method for fabricating an image sensor includes at least one of: (1) Forming a gate on a semiconductor substrate; (2) Forming spacers on both side walls of the gate and forming a dummy pattern on an upper portion of the semiconductor substrate; and (3) Forming a metal pad for an electrical connection on an upper portion of the dummy pattern. The method may include at least one of: (1) Forming an interlayer dielectric layer covering the entire semiconductor substrate, (2) Etching portions of the interlayer dielectric layer and the semiconductor substrate to form a super-contact hole; and (3) forming an insulation film on the entire surface of the interlayer dielectric layer. The method may include forming normal contact holes such that a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection are exposed and filling up the normal contact holes with a conductive material to form normal contacts.

Description

The present application claims priority to Korean Patent Application No. 10-2012-0052101 (filed on May 16, 2012), which is hereby incorporated by reference in its entirety.
BACKGROUND
There has been a general trend in the reduction in size of micro-electronic systems. Chip scale packaging, flip chips, and multichip modules are generally applied to a variety of electronic product categories such as mobile phones, hand-held computers, chip cards, and similar applications/devices. Future applications of electronic devices may require relatively complicated elements supporting various functions, which often results in the chip area being required to be relatively large to meet demands. This results in challenges with manufacturing yield of chips due to an integration of multifunctional devices, an increase in cost due to complexity of device implementation, and technical limitations. In addition, wirings between subsystems may be challenging due to limitations in performance, multifunctionality, reliability and similar issues of micro-electronic systems. These factors may be critical performance bottlenecks for future integrated circuit generation. A 3D integration technology may have significant potential to replace an embedded system on chip (SoC) technology.
In a packaging process, a super-contact hole may serve as a pad and a normal contact hole may serve for connecting wirings that are simultaneously patterned on a single wafer. The super-contact hole may have a diameter ranging from approximately 1 μm to 2 μm and a depth ranging from approximately 6 μm to 10 μm. A non-super-contact hole may have a diameter ranging from approximately 0.1 μm to 0.3 μm and a depth ranging from approximately 1 μm to 2 μm.
A process of forming a related art super-contact can be described with reference to FIGS. 1A to 1E. Example FIGS. 1A to 1E are cross-sectional views illustrating a process of forming a super-contact, according to the related art. As shown in example FIG. 1A, an device isolation layer (not shown) may define an active region. Unit elements (such as a PMOS transistor and an NMOS transistor including a source/drain junction part and a gate 50 formed on the active region and similar elements) may be formed on a semiconductor substrate 100.
As shown in FIG. 1B, an interlayer dielectric layer 102 may be formed on the entire structure with the unit elements formed thereon. A photoresist pattern 104 for a super-contact hole may be formed on the interlayer dielectric layer 102. Then the interlayer dielectric layer 102 and the semiconductor substrate 100 may be etched by an etching process using the photoresist pattern 104 as an etching mask to form a super-contact hole 106.
As shown in FIG. 1C, the photoresist pattern 104 may be removed through a strip process, and an insulation film 108 may be formed on the surface of the entire structure including the super-contact hole 106. The insulation film 108 may serve as a shielding insulation film of a super-contact to be formed later and may be formed of at least one of oxide series and nitride series.
As shown in FIG. 1D, the super-contact hole 106 may be filled with a conductive material (e.g. tungsten (W)) to form a conductive layer 110. As shown in FIGS. 1D and 1E, a photoresist pattern 111 for a normal contact hole may be formed on an upper portion of the entire structure with the conductive layer 110 filled in the super-contact hole 106. The interlayer dielectric layer 102 may be etched through an etching process using the photoresist pattern 111 as an etching mask to form a normal contact hole 112. The photoresist pattern 111 for a normal contact is removed.
In the foregoing related art super-contact hole formation process, the insulation film 108 is formed after the formation of the super contact hole 106. However, the interlayer dielectric layer 102 may not be etched enough when forming the normal contact hole 112, which may cause problems with an electrical connection to the active region. For example, when the normal contact hole 112 is formed, since the interlayer dielectric layer 102 needs to be etched deeper due to the insulation film 108, a portion A in the interlayer dielectric layer 102 may not be etched enough, which may cause problems in the electrical connection to the active region.
SUMMARY
In view of the above, embodiments provides an image sensor in which problems of electrical connections does not arise or are minimized without changing the etching depth in an interlayer dielectric layer when forming a normal contact hole. Embodiments relate to a method for fabricating the same.
In accordance with embodiments, a method for fabricating an image sensor includes at least one of the following: (1) Forming a gate on a semiconductor substrate. (2) Forming spacers on both side walls of the gate and forming a dummy pattern spaced apart from the gate on an upper portion of the semiconductor substrate. (3) Forming a metal pad for an electrical connection on an upper portion of the dummy pattern. (4) Forming an interlayer dielectric layer covering substantially the entire semiconductor substrate having the metal pad for an electrical connection formed thereon. (5) Etching portions of the interlayer dielectric layer and the semiconductor substrate to form a super-contact hole. (6) Forming an insulation film on the entire surface of the interlayer dielectric layer having the super-contact hole formed thereon. (7) Forming normal contact holes such that a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection are exposed therefrom. (8) Filling the normal contact holes with a conductive material to form normal contacts.
In embodiments, the semiconductor substrate may be an epitaxial layer. In embodiments, said forming a metal pad for an electrical connection may include forming a metal pad for an electrical connection that covers the entirety or a portion of the upper portion of the dummy pattern. In embodiments, said forming a dummy pattern may include forming an oxide film for a spacer on an upper portion of the semiconductor substrate having the gate formed thereon and patterning a portion of the oxide film for a spacer to form the spacers and the dummy pattern spaced apart from the gate on an upper portion of the semiconductor substrate.
In embodiments, said forming a metal pad for an electrical connection may include depositing a metal material on the entire surface of the semiconductor substrate with the dummy pattern formed thereon and patterning the deposited metal material to form the metal pad for an electrical connection covering a partial region of an upper portion of the dummy pattern and a partial upper portion of the semiconductor substrate adjacent to the dummy pattern. In embodiments, the insulation film may be formed by using a silicon nitride film or a silicon oxide film.
Embodiments relate to an image sensor including at least one of: (1) A gate formed on a semiconductor substrate and spacers formed on both side walls of the gate. (2) A dummy pattern formed spaced apart from the gate on an upper portion of the semiconductor substrate. (3) A metal pad for an electrical connection, which is configured to cover an upper portion of dummy pattern. (4) An interlayer dielectric layer substantially covering the entire semiconductor substrate having the gate and the metal pad for an electrical connection formed thereon. (5) Normal contacts formed to be connected to a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection. (6) A super-contact configured formed by etching portions of the interlayer dielectric layer and the semiconductor substrate.
In embodiments, the dummy pattern may be formed by patterning a portion of an oxide film deposited to form the spacers. In embodiments, the metal pad for an electrical connection may be formed to have a structure that covers a portion of an upper portion of the dummy pattern and a partial upper portion of the semiconductor substrate adjacent to the dummy pattern. In embodiments, the metal pad for an electrical connection may be formed to have a structure that covers the entirety or a portion of the upper portion of the dummy pattern.
In accordance with embodiments, after the dummy pattern and the metal pad for an electrical connection are formed on the semiconductor substrate, the process for forming the super-contact hole and the normal contact hole may be performed. In embodiments, although the thickness of the interlayer dielectric layer is relatively large due to the insulation film formed on the super-contact hole, since the interlayer dielectric layer is etched only up to an upper portion of the metal pad for an electrical connection, the normal contact hole without the problem of an electrical connection may be formed without changing an etching depth.
DRAWINGS
The objects and features of embodiments will become apparent from the following description of embodiments, given in conjunction with the accompanying drawings, in which:
Example FIGS. 1A to 1E are cross sectional views illustrating a process of forming a contact in accordance with the related art.
Example FIGS. 2A to 2F are cross sectional views illustrating a process of forming a contact of a CMOS image sensor in accordance with embodiments.
 DESCRIPTION
Advantages and features of embodiments and methods of accomplishing the same may be understood more readily by reference to the following detailed description of embodiments and the accompanying drawings. The embodiments may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the embodiments to those skilled in the art, and the embodiments will only be defined by the appended claims.
Hereinafter, a contact of a CMOS image sensor and a formation process thereof in accordance with embodiments will be described with reference to the accompanying drawings. Example FIGS. 2A to 2F are cross sectional views illustrating a process of forming a contact of a CMOS image sensor, in accordance with embodiments.
As illustrated in FIG. 2A, an insulation layer and a polysilicon layer may be sequentially formed on an upper portion of a semiconductor substrate 200 and then patterned to form a gate insulation film 201 and a gate 202, in accordance with embodiments. An oxide film for a spacer may then be formed on/over substantially the entire surface having the gate 202 formed thereon and then patterned to form a spacer 204 at both side walls of the gate 202 and a dummy pattern 206 spaced apart from the spacer 204 on an upper portion of the semiconductor substrate 200, in accordance with embodiments. In embodiments, the dummy pattern 206 is a portion connected to a normal contact hole (to be formed later) and the semiconductor substrate 200 may be an epitaxial layer formed through a silicon growth process.
In embodiments, as illustrated in FIG. 2B, a barrier metal material for an electrical connection may be deposited and then patterned to form a metal pad 208 for an electrical connection on a partial region of an upper portion of the dummy pattern 206. In embodiments, the metal pad 208 for the electrical connection may be formed to cover the partial region of the upper portion or the entire region of the dummy pattern 206 or a partial region of the upper portion of the semiconductor substrate 200 adjacent to the dummy pattern 206.
As illustrated in FIG. 2C, an interlayer dielectric layer 210 may be formed on the entire structure on/over the metal pad 208 for an electrical connection. A photoresist pattern (not shown) for a super-contact hole may be formed on an upper portion of the interlayer dielectric layer 210. In embodiments, the interlayer dielectric layer 210 and the semiconductor substrate 200 may be etched through an etching process using the photoresist pattern as an etch mask to from a super-contact hole 212.
As illustrated in FIG. 2D, the photoresist pattern may be removed through a strip process, in accordance with embodiments. In embodiments, an insulation film 214 may be formed on/over the surface of the entire structure including the super-contact hole 212. In embodiments, the insulation film 214 may be formed of at least one of oxide series and nitride groups. In example embodiments, the insulation film 214 may be formed by sequentially depositing a silicon nitride film 214 a and a silicon oxide film 214 b.
In embodiments, as shown in FIG. 2E, the super-contact hole 212 may be filled with a conductive material (e.g. tungsten (W)), to form a super-contact 220. In embodiments, a photoresist pattern for a normal contact hole may be formed on the entire structure with the super-contact 220 formed thereon. In embodiments, the interlayer dielectric layer 210 may be etched through an etching process using the photoresist pattern as an etch mask to form normal contact holes 216. In embodiments, the photoresist pattern for a normal contact hole and the photoresist layer for filling-up are all removed through a strip process, thus completing the super-contact 220 and the normal contact holes 216. In embodiments, the normal contact holes 216 may be formed to allow a partial upper portion of the metal pad 208 for an electrical connection and an upper portion of the gate 202 to be exposed therefrom.
In embodiments, as shown in FIG. 2F, a conductive material (e.g., tungsten (W)) may be deposited such that the normal contact holes 216 are completely filled up. A chemical mechanical polishing (CMP) process may be performed by setting an upper portion of the insulation film 214 as a polishing stop point, to form normal contacts 230, in accordance with embodiments.
In embodiments, after the dummy pattern 206 and the metal pad 208 for an electrical connection are formed on the semiconductor substrate 200, the process of forming the super-contact hole 212 and the normal contact hole 216 is performed. In embodiments, although the etching thickness for forming the normal contact holes 216 (i.e. the thickness obtained by adding each thickness of the insulation film 214 and the interlayer dielectric layer 210), is increased, since the interlayer dielectric layer 210 is etched only up to the upper portion of the metal pad 208 for an electrical connection, which may result in normal contact holes 216 that do not have electrical connection problems.
While the embodiments have been shown and described with respect to the embodiments, the embodiments are not limited thereto. It will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the embodiments as defined in the following claims.

Claims (14)

What is claimed is:
1. A method comprising:
forming a gate on a semiconductor substrate;
on an upper portion of the semiconductor substrate, forming spacers on both side walls of the gate and forming a dummy pattern spaced apart from the gate;
forming a metal pad configured to provide an electrical connection on an upper portion of the dummy pattern;
forming an interlayer dielectric layer at least one of on and over the entire semiconductor substrate and the metal pad;
etching portions of the interlayer dielectric layer and the semiconductor substrate to form a super-contact hole;
forming an insulation film on the entire surface of the interlayer dielectric layer and the super-contact hole;
forming normal contact holes exposing at least a portion of an upper portion of the gate and at least a partial portion of the metal pad; and
filling the normal contact holes with a conductive material to form normal contacts.
2. The method of claim 1, wherein the method is a method of fabricating an image sensor.
3. The method of claim 1, wherein the semiconductor substrate is an epitaxial layer.
4. The method of claim 1, wherein the metal pad covers at least a portion of the upper portion of the dummy pattern.
5. The method of claim 1, wherein the metal pad covers the entire upper portion of the dummy pattern.
6. The method of claim 1, wherein said forming a dummy pattern comprises:
forming an oxide film over an upper portion of the semiconductor substrate having the gate formed thereon; and
patterning a portion of the oxide film to form the spacers and the dummy pattern spaced apart from the gate on an upper portion of the semiconductor substrate.
7. The method of claim 1, wherein said forming a metal pad comprises:
depositing a metal material on the entire surface of the semiconductor substrate with the dummy pattern formed thereon; and
patterning the deposited metal material to form the metal pad covering a partial region of an upper portion of the dummy pattern and a partial upper portion of the semiconductor substrate adjacent to the dummy pattern.
8. The method of claim 1, wherein the insulation film is formed by using a silicon nitride film or a silicon oxide film.
9. An apparatus comprising:
a gate formed on a semiconductor substrate and spacers formed on both side walls of the gate;
a dummy pattern formed spaced apart from the gate on an upper portion of the semiconductor substrate;
a metal pad covering an upper portion of dummy pattern, wherein the metal pad is configured for electrical connection;
an interlayer dielectric layer covering the entire semiconductor substrate having the gate and the metal pad for an electrical connection formed thereon;
normal contacts formed to be connected to a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection; and
a super-contact formed by etching portions of the interlayer dielectric layer and the semiconductor substrate.
10. The apparatus of claim 9, wherein the apparatus is an image sensor.
11. The apparatus of claim 9, wherein the dummy pattern is formed by patterning a portion of an oxide film deposited to form the spacers.
12. The apparatus of claim 9, wherein the metal pad is formed to have a structure that covers a portion of an upper portion of the dummy pattern and a partial upper portion of the semiconductor substrate adjacent to the dummy pattern.
13. The apparatus of claim 9, wherein the metal pad covers the entire upper portion of the dummy pattern.
14. The apparatus of claim 9, wherein the metal pad covers a portion of the upper portion of the dummy pattern.
US13/742,714 2012-05-16 2013-01-16 Image sensor and method for fabricating the same Active US8664114B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2012-0052101 2012-05-16
KR1020120052101A KR101324087B1 (en) 2012-05-16 2012-05-16 Image sensor and method for fabricating the same

Publications (2)

Publication Number Publication Date
US20130307035A1 US20130307035A1 (en) 2013-11-21
US8664114B2 true US8664114B2 (en) 2014-03-04

Family

ID=49580615

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/742,714 Active US8664114B2 (en) 2012-05-16 2013-01-16 Image sensor and method for fabricating the same

Country Status (2)

Country Link
US (1) US8664114B2 (en)
KR (1) KR101324087B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040173874A1 (en) * 2003-03-03 2004-09-09 Fujitsu Limited Semiconductor device and manufacturing method of the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100667650B1 (en) 2005-11-14 2007-01-12 삼성전자주식회사 Image device and the manufacture thereof
JP2007227445A (en) 2006-02-21 2007-09-06 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
KR100894387B1 (en) 2007-10-22 2009-04-22 주식회사 동부하이텍 Image sensor and method for manufacturing thereof
JP5853351B2 (en) 2010-03-25 2016-02-09 ソニー株式会社 SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040173874A1 (en) * 2003-03-03 2004-09-09 Fujitsu Limited Semiconductor device and manufacturing method of the same

Also Published As

Publication number Publication date
US20130307035A1 (en) 2013-11-21
KR101324087B1 (en) 2013-10-31

Similar Documents

Publication Publication Date Title
US10903316B2 (en) Radio frequency switches with air gap structures
US9953857B2 (en) Semiconductor device with buried local interconnects
CN113658868B (en) Semiconductor element and manufacturing method thereof
US9478463B2 (en) Device and method for improving RF performance
US9590059B2 (en) Interdigitated capacitor to integrate with flash memory
CN113345857A (en) Semiconductor element and method for manufacturing the same
CN112582375B (en) Semiconductor device with sidewall interconnection structure, method of manufacturing the same, and electronic apparatus
CN112582376B (en) Semiconductor device with sidewall interconnection structure, method of manufacturing the same, and electronic apparatus
US9989856B2 (en) Method of manufacturing semiconductor devices
TWI690025B (en) Semiconductor-on-insulator (soi)substrate, method for forming thereof, and integrated circuit
TWI670857B (en) Memory structure and method for forming the same
US9515133B2 (en) Inductor device and fabrication method
US9012244B2 (en) Method to form multiple trenches utilizing a grayscale mask
US9337259B2 (en) Structure and method to improve ETSOI MOSFETS with back gate
US8664114B2 (en) Image sensor and method for fabricating the same
US11411092B2 (en) Field effect transistor (FET) comprising inner spacers and voids between channels
US8927387B2 (en) Robust isolation for thin-box ETSOI MOSFETS
KR101064288B1 (en) Methode of forming a contact hole in semiconductor device
CN110911283A (en) Method for manufacturing transistor of silicon on insulator
CN103579087B (en) A kind of manufacture method of three-dimensional integrated circuit structure and three-dimensional integrated circuit structure
US20230253322A1 (en) Nano-tsv landing over buried power rail
US20210066274A1 (en) Semiconductor device and fabricating method thereof
KR101064284B1 (en) Methode of forming a contact hole in semiconductor device
CN114141751A (en) Semiconductor structure and forming method thereof
KR101024792B1 (en) Method for Manufacturing Semiconductor Device

Legal Events

Date Code Title Description
AS Assignment

Owner name: DONGBU HITEK CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YUN, KI-JUN;REEL/FRAME:029639/0896

Effective date: 20130110

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551)

Year of fee payment: 4

AS Assignment

Owner name: DB HITEK CO., LTD., KOREA, REPUBLIC OF

Free format text: CHANGE OF NAME;ASSIGNOR:DONGBU HITEK CO., LTD.;REEL/FRAME:044559/0819

Effective date: 20171101

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8