CN109585452A - A kind of memory and preparation method thereof - Google Patents
A kind of memory and preparation method thereof Download PDFInfo
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- CN109585452A CN109585452A CN201811492899.8A CN201811492899A CN109585452A CN 109585452 A CN109585452 A CN 109585452A CN 201811492899 A CN201811492899 A CN 201811492899A CN 109585452 A CN109585452 A CN 109585452A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
The application provides a kind of memory and preparation method thereof, the production method includes: to provide the first wafer, wherein, it opens up on first wafer in the corresponding place in position for being subsequently formed metal pad fluted, the depth of the groove is greater than or equal to the thickness of the first wafer after being thinned, to which after the first wafer is thinned, the groove on the first wafer to be got through to the wafer through-hole to be formed through the first wafer.In this way, after being subsequently formed metal pad, since position corresponding with metal pad is through the wafer through-hole of the first wafer, reduce with the wafer area of metal pad face, so that the parasitic capacitance between the first wafer and metal pad reduces, and groove can be formed by once etching, depth is without strict control, to expand process window, so that the mode that parasitic capacitance reduces is more easier to control, technology controlling and process required precision is reduced.
Description
Technical field
The present invention relates to semiconductor devices manufacture technology fields more particularly to a kind of memory and preparation method thereof.
Background technique
In novel 3D NAND product framework, memory cell areas (Cell) and external zones (CMOS) are produced on different wafers
On, by three-dimensional special warfare by circuit connection together, then wafer where thinning Cell from the back side picks out circuit
Come.
Usually chip internal circuits are picked out come still by the way that multiple pads are arranged in the fringe region of 3D NAND chip
When the inside wafer of pad and 3D NAND chip has electric current to pass through simultaneously, strong parasitic capacitance (CIO) can be generated, is slowed down
The speed of operation storage.
Therefore, reducing the parasitic capacitance inside 3D NAND chip between wafer and pad becomes in 3D NAND manufacturing process
The technical issues that need to address, and the 3DNAND manufacture craft of the reduction parasitic capacitance used in the prior art is more difficult to control, and
It is more demanding to craft precision.
Summary of the invention
In view of this, the present invention provides a kind of memory and preparation method thereof, to solve to reduce parasitic electricity in the prior art
The manufacture craft of appearance is difficult to control, the problem more demanding to craft precision.
To achieve the above object, the invention provides the following technical scheme:
A kind of memory production method, comprising:
The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged；Described first is brilliant
The position of memory metal pad to be formed opens up fluted on round first surface, and the depth of groove, which is greater than or equal to, to be thinned
The thickness of the first wafer afterwards；
The first insulating layer is formed on the first surface, and first insulating layer fills the groove；
Formed on the surface of first insulating layer it is multiple through array contact portion, it is described through array contact portion described
Orthographic projection on first wafer is located in the groove；
First wafer is thinned by the second surface of first wafer, so that the groove is formed after being thinned
The wafer through-hole of first wafer；
The first wafer after described be thinned forms second insulating layer away from the surface of the first surface；
Formed in the groove it is multiple through array through-hole, it is multiple described to be connect with described through array through array through-holes
Contact portion is arranged in a one-to-one correspondence, and runs through array contact portion to described through the second insulating layer and first insulating layer；
Run through contact portion in described formed in array through-hole；
Metal pad is formed on the surface of the second insulating layer, the metal pad covers all institutes in the groove
It states through array through-hole.
Preferably, the first wafer is provided to specifically include:
Complete first wafer is provided；
The position of metal pad to be formed forms the groove on the first surface of first wafer.
Preferably, the surface in first insulating layer is formed multiple through array contact portion, is specifically included:
Region corresponding with the groove forms multiple first grooves on the surface of first insulating layer；
Multiple first grooves are filled using conductive material, are formed multiple through array contact portion.
Preferably, further includes:
Second wafer is provided；
Storage array is formed on second wafer；
Be bonded first wafer and second wafer, by first wafer through array contact portion and described
Storage array on second wafer is electrically connected.
The present invention also provides a kind of memories, comprising:
First wafer, first wafer include first surface and second surface being oppositely arranged and through described first
The wafer through-hole of wafer；
The insulating layer of the first surface and second surface of the wafer through-hole and covering first wafer is filled, it is described exhausted
Edge layer includes the third surface and the 4th surface being oppositely arranged；
It is arranged in multiple through array contact portion in the third surface；
Metal pad in 4th surface is set；
Include in the wafer through-hole filled with through the multiple through array through-hole of contact portion, it is multiple described through contact
Portion and multiple described correspond through array contact portion are electrically connected, and multiple described through contact portion and the metal pad
It is electrically connected.
Preferably, orthographic projection of the metal pad on first wafer and the wafer through-hole are overlapping.
Preferably, orthographic projection of the metal pad on first wafer cover the wafer through-hole or with the crystalline substance
Round tube hole is overlapped or is located in the wafer through-hole.
It preferably, further include the through-silicon contact portion for running through first wafer.
Preferably, described identical with the material through array contact portion through contact portion.
It preferably, further include the second wafer；
One surface of second wafer is formed with storage array；
First surface of second wafer bonding in first wafer, and the storage array and first wafer
On through contact portion be electrically connected.
It can be seen via above technical scheme that memory production method provided by the invention, comprising: the first wafer is provided,
Wherein, opened up in the corresponding place in position for being subsequently formed metal pad fluted on the first wafer, the depth of the groove is big
The thickness of the first wafer after be thinned, so that the groove on the first wafer is got through shape after the first wafer is thinned
At the wafer through-hole for running through the first wafer.In this way, after being subsequently formed metal pad, since position corresponding with metal pad is
Through the wafer through-hole of the first wafer, reduce with the wafer area of metal pad face, so that the first wafer and metal welding
Parasitic capacitance between disk reduces, and groove can be formed by once etching, and depth is without strict control, therefore, uses
Memory production method provided by the invention, without by multiple etching and between strict control metal pad and the first wafer
Thickness of insulating layer realizes the reduction of parasitic capacitance, so that process window is expanded, so that the mode that parasitic capacitance reduces more is held
It is easy to control, technology controlling and process required precision is reduced.
The present invention also provides a kind of memories, due to opening up the position of the first wafer setting metal pad through the first crystalline substance
Round wafer through-hole so that the first wafer and metal pad positive area reduce, and then can reduce parasitic capacitance.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of memory the schematic diagram of the section structure provided in the prior art；
Fig. 2 is a kind of memory production method process flow chart provided in an embodiment of the present invention；
Fig. 3-Fig. 9 is memory production method processing step schematic diagram provided in an embodiment of the present invention.
Specific embodiment
Just as described in the background section, the 3D NAND manufacture craft of the reduction parasitic capacitance used in the prior art compared with
It is difficult to control and more demanding to craft precision.
The reason of above-mentioned phenomenon occurs in invention discovery is that referring to Figure 1, Fig. 1 is a kind of memory the schematic diagram of the section structure；
Memory includes silicon substrate 01, is formed in the insulating layer 03 of 01 two sides of silicon substrate, and is formed in the metal inside silicon substrate 01
Cabling 06, the through-silicon contact portion (through silicon contact, TSC) 05 through substrate, and it is electrical with TSC05
Connection runs through array contact portion (through array contact, TAC) 04, and the surface of memory construction is additionally provided with guarantor
Sheath 07.Wherein, it is formed with metal pad 02 in the partial region of protective layer 07, metal pad 02 is used for memory inside
Circuit connection goes out chip.
It is formed when passing through electric current simultaneously on metal pad 02 and silicon substrate 01, between silicon substrate 01 and metal pad 02 flat
Parasitic capacitance described in plate capacitor namely background technology part.Due to the presence of parasitic capacitance, the speed of operation storage can be slowed down
Degree.
Inventor's discovery: the basic reason that parasitic capacitance generates is, between silicon substrate when metal pad and electric current pass through
Capacity plate antenna is formed, size is according to formula:It determines, wherein d is metal pad lower surface and silicon substrate upper surface
Between thickness of insulating layer, referring to Figure 1, S be metal pad and silicon substrate overlapping area.Inventor currently reduces parasitic electricity
The method of appearance are as follows: by the thickness of the insulating layer between strict control metal pad and silicon substrate, reduce parasitic capacitance, prevent from depositing
Storage speed slows down.The method of the thickness of specific control insulating layer are as follows: growth forms thicker insulating layer on a silicon substrate, by more
Secondary etching is thinned thickness of insulating layer and needs to control uniformity and thickness in etching process, is also required to by controlling insulating layer
The precision of etching, to control the thickness of insulating layer.Since the terminal of etching is more difficult to control in technique, so that the thickness of insulating layer
Control is more difficult, if technique generates deviation, it is likely that cause the open circuit or electric leakage of 3D nand memory internal circuit.
And the uniformity of each etching insulating layer is also more difficult to control, and the etching of insulating layer needs to carry out multiple etching, to cause absolutely
The control of edge layer thickness is more difficult.
Moreover, while memory inside circuit is picked out, it is necessary to get through the insulating layer after the silicon substrate back side thickeies
03 and silicon substrate 01, and when the thickness (to more than 1.4 μm) for increasing the insulating layer 3 between silicon substrate 01 and metal pad 02 reduces
While parasitic capacitance, cause subsequent punching, and fill metal formed TSC during hole depth-to-width ratio increase, specifically by
It is constant in the diameter of punching, and depth increases, and causes the depth-to-width ratio of TSC to increase, considerably increases the difficulty of technique.And increase
After 03 thickness of insulating layer, the cost of depositing insulating layer increases therewith, simultaneously because TSC depth-to-width ratio increases, needs using more first
Into board realize, equally increase process costs.
Based on this, the embodiment of the present invention provides a kind of memory production method, comprising:
The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged；Described first is brilliant
The position of memory metal pad to be formed opens up fluted on round first surface, and the depth of groove, which is greater than or equal to, to be thinned
The thickness of the first wafer afterwards；
The first insulating layer is formed on the first surface, and first insulating layer fills the groove；
Formed on the surface of first insulating layer it is multiple through array contact portion, it is described through array contact portion described
Orthographic projection on first wafer is located in the groove；
First wafer is thinned by the second surface of first wafer, so that the groove is formed after being thinned
The wafer through-hole of first wafer；
The first wafer after described be thinned forms second insulating layer away from the surface of the first surface；
Formed in the groove it is multiple through array through-hole, it is multiple described to be connect with described through array through array through-holes
Contact portion is arranged in a one-to-one correspondence, and runs through array contact portion to described through the second insulating layer and first insulating layer；
Run through contact portion in described formed in array through-hole；
Metal pad is formed on the surface of the second insulating layer, the metal pad covers all institutes in the groove
It states through array through-hole.
Memory production method provided by the invention, comprising: provide the first wafer, wherein in subsequent shape on the first wafer
Opened up at the corresponding place in the position of metal pad fluted, the depth of the groove is greater than or equal to the first wafer after being thinned
Thickness, thus the first wafer be thinned after, the groove on the first wafer is got through to the wafer through-hole to be formed through the first wafer.
In this way, after being subsequently formed metal pad, since position corresponding with metal pad is through the wafer through-hole of the first wafer, with
The wafer area of metal pad face reduces, so that the parasitic capacitance between the first wafer and metal pad reduces, and it is recessed
Slot can be formed by once etching, and depth is without strict control, therefore, using memory production side provided by the invention
Method, without realizing parasitic capacitance by multiple etching and the thickness of insulating layer between strict control metal pad and the first wafer
Reduce, so that process window is expanded, so that the mode that parasitic capacitance reduces is more easier to control, to technology controlling and process required precision
It reduces.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of memory construction production method, refers to Fig. 2, comprising:
S101: the first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged；Described
The position of memory metal pad to be formed opens up fluted on the first surface of one wafer, and the depth of groove is greater than or equal to
The thickness of the first wafer after being thinned；
The specific structure of memory construction is not limited in the embodiment of the present invention, in one embodiment of the invention, storage
Device structure can be 3D nand memory structure.The 3D nand memory structure is using memory cell areas (Cell) and periphery
(CMOS) is produced on different wafers in area, then again by three-dimensional special warfare by circuit connection together.Therefore, the present embodiment
First wafer of middle offer is the wafer for being used to form peripheral structure, and peripheral structure includes but is not limited to CMOS structure, is being made
It can also include that the second wafer is provided, second wafer is used to form storage array during making 3D NAND.
Fig. 3 is referred to, a surface forms fluted 11 on the first wafer 1 provided in the present embodiment, and the second wafer 2
Not necessarily form groove.Peripheral structure is formed on the first wafer 1, and on the second wafer after formation storage array, by mixed
Bonding technology is closed by the first wafer and the second wafer bonding, specifically, by connecing through array for the peripheral structure on the first wafer
Storage array in contact portion and the second wafer is electrically connected.
The material of the first wafer and the second wafer is not limited in the embodiment of the present invention, optionally, in embodiments of the present invention
The material of first wafer and the second wafer is identical, and is Silicon Wafer.It should be noted that in other embodiments of the present invention,
First wafer and the second wafer can also be silicon-on-insulator substrate or other crystal circle structure materials, not make in the present embodiment to this
It limits.
Need the surface formation metal pad for deviating from the second wafer in the first wafer will be in 3DNAND memory due to subsequent
Outside the circuit connection to memory in portion, in order to reduce the parasitic capacitance being subsequently formed between metal pad and the first wafer, this
Groove is opened up by position corresponding with metal pad on the first wafer in embodiment, the depth of the groove is greater than or equal to
The thickness of the first wafer after being thinned, so that the through-hole of the first wafer after being thinned is formed, in this way, corresponding with metal pad
The area of first wafer reduces in terms of existing technologies, and then can reduce posting between metal pad and the first wafer
Raw capacitor.
It should be noted that being not construed as limiting in the present embodiment to the size of groove, but in order to reduce parasitic capacitance, reduce
The area of first wafer and metal pad face, the metal pad of 3D nand memory to be formed is in the first crystalline substance in the present embodiment
Projection on circle is with the contour convergence of the groove or in the groove.That is, by will the first wafer in the prior art
The wafer material removal in upper region corresponding with metal pad, so that the positive area of metal pad and the first wafer is reduced,
And then the parasitic capacitance of reduction between the two.
In other embodiments of the invention, throwing of the metal pad on the first wafer can also be arranged in the profile of groove
Shadow contoured interior, as long as in terms of existing technologies, it being capable of the opposite right opposite reduced between metal pad and the first wafer
Product, can reduce parasitic capacitance between the two.But in such cases, need strict control metal pad on the first wafer
Projected outline and groove profile between area, so as to greatly reduce parasitic capacitance, have preferable effect.Therefore,
In the embodiment of the present invention, more preferably, projection and the contour convergence of the groove of the metal pad on first wafer
Or it is located in the groove.
In addition, in other embodiments of the invention, there may also be overlapping namely grooves between groove and metal pad
Edge contour and metal pad edge contour between intersecting, as long as the overlapping area of groove and metal pad be less than it is existing
There is the positive area of the first wafer and metal pad in technology, then can also reduce the size of parasitic capacitance to a certain degree.
It is not limited in the present embodiment and the detailed process of the first wafer is provided, can specifically include: it is brilliant to provide complete first
Circle, after providing complete first wafer, the position of metal pad to be formed is formed described on the first surface of the first wafer
Groove, wherein the process for forming groove, which can be, carves the surface of peripheral structure to be formed on the first wafer by etching technics
Lose the groove out, it can be by being formed in the first crystal column surface with figuratum mask plate in the present embodiment, then pass through photoetching
Technique forms the groove.In other embodiments of the present invention, it can also be formed by wet-etching technology, it is right in the present embodiment
This is not construed as limiting.The layer that mask plate performs etching will be done for the first time in the present embodiment on wafer and is known as ZERO layers, that is, this implementation
Example further groove is formed on ZERO layer.
S102: forming the first insulating layer on the first surface, and first insulating layer fills the groove；
Fig. 4 is referred to, is the partial schematic diagram of the first wafer, is only had chosen in the present embodiment to be produced on the first wafer 1
The position of metal pad is illustrated, and the other parts of complete first wafer are not drawn in figure.
As shown in Figure 4, the first wafer 1 includes silicon substrate, is arranged fluted 11 on silicon substrate.Due to production periphery knot
Structure, the surface that peripheral structure is formed on silicon substrate are also formed with the first insulating layer 13, and the first insulating layer 13 fills groove 11, and covers
Lid first surface.The specific material of insulating layer is not limited in the present embodiment, in embodiments of the present invention the first insulating layer material
Matter can be oxide, especially silica.
S103: formed on the surface of first insulating layer it is multiple through array contact portion, it is described to run through array contact portion
It is located in the groove in the orthographic projection on first wafer；
Include: continuing with the detailed process through array contact portion referring to fig. 4, is made
Region corresponding with groove forms multiple first grooves on the surface of the first insulating layer 13；
Multiple first grooves are filled using conductive material, are formed multiple through array contact 12.To run through in the present embodiment
Array contact portion (TAC) 12 represents the part-structure of peripheral components.
S104: being thinned first wafer by the second surface of first wafer, subtracts so that the groove forms to run through
The wafer through-hole of the first wafer after thin；
Fig. 5 is referred to, for structural schematic diagram of first wafer after the second crystal column surface is thinned；Wherein, it is thinned first
Crystal column surface is at least to 11 bottom of groove, so that groove forms the wafer through-hole 111 for running through the first wafer, with after an action of the bowels
Continuous technique is completed.
Technique used by first wafer is thinned is not limited in the present embodiment, optionally, CMP is used in the present embodiment
(chemical mechanical grinding) technique removes extra silicon substrate, and the first wafer is thinned.
It should be noted that since what is filled in groove is the first insulating layer 13,13 He of the first insulating layer in the present embodiment
1 material of silicon substrate is different, has specific boundary between the two, can be by detecting the signal intensity polished judgement in CMP
It is no to polish to bottom portion of groove, so that the detection that terminal is thinned in the first wafer can also be simplified.
S105: the first wafer after described be thinned forms second insulating layer away from the surface of the first surface；
Fig. 6 is referred to, further includes that growth forms thicker second absolutely after the first wafer is thinned, before forming metal pad
Edge layer 14.The second insulating layer 14 grown in the present embodiment is for protecting the first wafer.
S106: formed in the groove it is multiple through array through-hole, it is multiple described to run through through array through-holes with described
Array contact portion is arranged in a one-to-one correspondence, and runs through array contact to described through the second insulating layer and first insulating layer
Portion；
The first insulating layer 13 is etched in 111 position of wafer through-hole and second insulating layer forms and runs through array through-hole 15, exposure
It is located at the TAC12 that peripheral structure is formed on the first wafer out, in order to subsequent filling metal, by the connection of 3D NAND internal circuit
To external TSC structure.
Fig. 7 is referred to, further includes the after etching second insulating layer 14 and being thinned in the region outside metal pad to be produced
One wafer exposes other grooves 16 of the TAC in other regions.
S107: run through contact portion in described formed in array through-hole；
Refer to Fig. 8, by metal fill into Fig. 7 institute it is fluted in, formed TSC17, connection be located at the first wafer it is another
On the TAC on one surface.
S108: metal pad is formed on the surface of the second insulating layer, the metal pad covers in the groove
It is all described through array through-hole.
Fig. 9 is referred to, metal pad 18 and metal routing 19 are formed on TSC17, by the circuit connection inside 3D NAND
To 3D NAND.
Finally the region outside metal pad 18 forms protective layer 110, does not limit the material of protective layer 110 in the present embodiment
Matter, optionally, the protective layer 110 are silicon nitride.
Memory production method provided by the invention, comprising: provide the first wafer, wherein in subsequent shape on the first wafer
Opened up at the corresponding place in the position of metal pad fluted, the depth of the groove is greater than or equal to the first wafer after being thinned
Thickness, thus the first wafer be thinned after, the groove on the first wafer is got through to the wafer through-hole to be formed through the first wafer.
In this way, after being subsequently formed metal pad, since position corresponding with metal pad is through the wafer through-hole of the first wafer, with
The wafer area of metal pad face reduces, so that the parasitic capacitance between the first wafer and metal pad reduces, and it is recessed
Slot can be formed by once etching, and depth is without strict control, therefore, using memory production side provided by the invention
Method, without realizing parasitic capacitance by multiple etching and the thickness of insulating layer between strict control metal pad and the first wafer
Reduce, so that process window is expanded, so that the mode that parasitic capacitance reduces is more easier to control, to technology controlling and process required precision
It reduces.
The embodiment of the present invention also provides a kind of memory, refers to Fig. 9, and Fig. 9 is that one kind provided in an embodiment of the present invention is deposited
The part-structure schematic cross-section of reservoir；The memory includes: the first wafer 1, and the first wafer 1 includes first be oppositely arranged
Surface 101 and second surface 102 and wafer through-hole 111 through the first wafer 1；It fills through-hole and covers the first wafer 1
The insulating layer of first surface and second surface, insulating layer include the third surface and the 4th surface being oppositely arranged；It is arranged in third
It is multiple through array contact portion in surface；Metal pad in 4th surface is set；It include being filled in wafer through-hole 111
Multiple through contact portion run through array through-hole, and multiple contact portions that run through electrically connect with multiple correspond through array contact portion
It connects, and multiple through contact portion and metal pad electric connection.
Fig. 9 is referred to, is the part-structure schematic cross-section of the first wafer；First wafer includes electrically connecting with storage array
What is connect runs through array contact portion 12, fills the insulating layer on first 1 two surfaces of wafer, passes through the first wafer, and run through with described
What array contact portion 12 was electrically connected runs through contact portion 17；Deviate from 19 He of metal routing of the second crystal column surface positioned at the first wafer
Metal pad 18, and the protective layer 110 of the exterior domain positioned at metal pad 18.
It should be noted that the unlimited specific material for determining metal pad 18 and metal routing 19 in the present embodiment, in this hair
In bright one embodiment, the material of metal pad 18 and metal routing 19 can be aluminium material.
The shape of wafer through-hole 111 Yu metal pad 18 is not limited in the present embodiment, optionally, in a reality of the invention
It applies in example, the shape of metal pad 18 is circle, and the shape of wafer through-hole 111 is also round, and the center of circle of the two is overlapped.
It should be noted that the relationship between the profile of metal pad 18 and the profile of wafer through-hole 111 does not limit, metal
Pad 18 can partly overlap area with having between the wafer after being thinned, and can also not have overlapping area, can also have one
Set a distance has certain distance D as shown in Figure 9 between the circumferential profile of metal pad 18 and the internal diameter of wafer through-hole 111,
The specific value of unlimited set a distance D in the present embodiment.It is unknown to the reduction degree of parasitic capacitance when the internal diameter of through-hole is smaller
It is aobvious, so that parasitic capacitance is unsatisfactory for the parasitic capacitance threshold value of 3D NAND；And when the internal diameter of through-hole 111 is larger, it is possible to influence it
The layout of its metal routing, therefore, optional in the present embodiment, the range of the distance D is 5 μm -10 μm, including endpoint value.
Metal pad 18 described in the present embodiment can partly overlap area with having between the wafer after being thinned, can be with
It is that orthographic projection of the metal pad on the first wafer and wafer through-hole are overlapping, overlapping described in the present embodiment may include: gold
Belong to pad in the orthographic projection covering wafer through-hole on the first wafer or is overlapped or is located in wafer through-hole with wafer through-hole.It can also be with
It include: to exist to deviate between the center of metal pad and the center of wafer through-hole, so that metal pad is staggered with wafer through-hole, but
It is overlapping with a part.
Metal pad 18 described in the present embodiment does not have overlapping area to refer to the wafer after being thinned, outside metal pad
Projection of all profiles on the wafer after being thinned is overlapped with the shape of through-hole, that is, the shape size of metal pad and through-hole is complete
It is exactly the same so that metal pad and be thinned after wafer between positive area be 0, to reduce parasitism between the two
Capacitor.
It further include being connect through the through-silicon of first wafer in addition, the region in the present embodiment except metal pad
Contact portion 16 is electrically connected with metal routing 19 as shown in Figure 9.
It should be noted that the memory provided in the present embodiment can be 3D nand memory structure, further includes: the
Two wafers；One surface of second wafer is formed with storage array；Second wafer bonding is in first wafer
First surface, and being electrically connected through contact portion on the storage array and first wafer.
Memory provided in an embodiment of the present invention, due to opening up the position of the first wafer setting metal pad through the
The through-hole of one wafer so that the first wafer and metal pad positive area reduce, and then can reduce parasitic capacitance.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of memory production method characterized by comprising
The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged；First wafer
The position of memory metal pad to be formed opens up fluted on first surface, the depth of groove is greater than or equal to be thinned after
The thickness of first wafer；
The first insulating layer is formed on the first surface, and first insulating layer fills the groove；
Formed on the surface of first insulating layer it is multiple through array contact portion, it is described through array contact portion described first
Orthographic projection on wafer is located in the groove；
First wafer is thinned by the second surface of first wafer, so that the groove forms first after being thinned
The wafer through-hole of wafer；
The first wafer after described be thinned forms second insulating layer away from the surface of the first surface；
Formed in the groove it is multiple through array through-hole, it is multiple described through array through-hole and described to run through array contact portion
It is arranged in a one-to-one correspondence, and runs through array contact portion to described through the second insulating layer and first insulating layer；
Run through contact portion in described formed in array through-hole；
Metal pad is formed on the surface of the second insulating layer, and what the metal pad covered in the groove all described passes through
Wear array through-hole.
2. memory production method according to claim 1, which is characterized in that
The first wafer is provided to specifically include:
Complete first wafer is provided；
The position of metal pad to be formed forms the groove on the first surface of first wafer.
3. memory production method according to claim 1, which is characterized in that the surface in first insulating layer
It is formed multiple through array contact portion, specifically included:
Region corresponding with the groove forms multiple first grooves on the surface of first insulating layer；
Multiple first grooves are filled using conductive material, are formed multiple through array contact portion.
4. memory production method according to claim 1, which is characterized in that further include:
Second wafer is provided；
Storage array is formed on second wafer；
It is bonded first wafer and second wafer, array contact portion and described second will be run through on first wafer
Storage array on wafer is electrically connected.
5. a kind of memory characterized by comprising
First wafer, first wafer include first surface and second surface being oppositely arranged and through first wafer
Wafer through-hole；
Fill the insulating layer of the first surface and second surface of the wafer through-hole and covering first wafer, the insulating layer
Including the third surface and the 4th surface being oppositely arranged；
It is arranged in multiple through array contact portion in the third surface；
Metal pad in 4th surface is set；
Include in the wafer through-hole filled with through the multiple through array through-hole of contact portion, it is multiple it is described through contact portion with
Multiple described correspond through array contact portion are electrically connected, and multiple described electrical through contact portion and the metal pad
Connection.
6. memory according to claim 5, which is characterized in that positive throwing of the metal pad on first wafer
Shadow and the wafer through-hole are overlapping.
7. memory according to claim 6, which is characterized in that positive throwing of the metal pad on first wafer
Shadow covers the wafer through-hole or is overlapped or is located in the wafer through-hole with the wafer through-hole.
8. memory according to claim 5, which is characterized in that further include the through-silicon contact through first wafer
Portion.
9. memory according to claim 7, which is characterized in that described through contact portion and described through array contact portion
Material it is identical.
10. memory according to claim 7, which is characterized in that further include the second wafer；
One surface of second wafer is formed with storage array；
Second wafer bonding first wafer first surface, and on the storage array and first wafer
It is electrically connected through contact portion.
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| CN201811492899.8A CN109585452B (en) | 2018-12-07 | 2018-12-07 | Memory and manufacturing method thereof |
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| CN111430360A (en) * | 2020-04-08 | 2020-07-17 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device and 3D NAND memory device |
| CN112867243A (en) * | 2021-01-06 | 2021-05-28 | 英韧科技(上海)有限公司 | Multilayer circuit board |
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| CN108807405A (en) * | 2018-06-12 | 2018-11-13 | 长江存储科技有限责任公司 | Three-dimensional storage and preparation method thereof |
| CN108831890A (en) * | 2018-06-21 | 2018-11-16 | 长江存储科技有限责任公司 | The preparation method of three-dimensional storage |
| CN109712986A (en) * | 2018-11-27 | 2019-05-03 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
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| US9281315B1 (en) * | 2015-03-03 | 2016-03-08 | Macronix International Co., Ltd. | Memory structure and method for manufacturing the same |
| CN108807405A (en) * | 2018-06-12 | 2018-11-13 | 长江存储科技有限责任公司 | Three-dimensional storage and preparation method thereof |
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| CN112867243A (en) * | 2021-01-06 | 2021-05-28 | 英韧科技(上海)有限公司 | Multilayer circuit board |
| US11706878B2 (en) | 2021-01-06 | 2023-07-18 | Innogrit Technologies Co., Ltd. | Multilayer circuit board |
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| CN109585452B (en) | 2020-03-03 |
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