CN110518062A - A kind of fleet plough groove isolation structure and semiconductor devices - Google Patents
A kind of fleet plough groove isolation structure and semiconductor devices Download PDFInfo
- Publication number
- CN110518062A CN110518062A CN201910919266.9A CN201910919266A CN110518062A CN 110518062 A CN110518062 A CN 110518062A CN 201910919266 A CN201910919266 A CN 201910919266A CN 110518062 A CN110518062 A CN 110518062A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- substrate
- groove
- layer
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 87
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 122
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 37
- 238000010276 construction Methods 0.000 claims description 10
- 238000003475 lamination Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 150000004767 nitrides Chemical group 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Abstract
The invention discloses a kind of fleet plough groove isolation structure and semiconductor devices, comprising: the substrate with a top；Positioned at least one groove of the top side of the substrate；Successively there are the first dielectric layer, the second dielectric layer and third dielectric layer along the inner wall of the groove, wherein, the top of first dielectric layer is lower than the top of second dielectric layer and the top of the substrate, make to form the first groove between second dielectric layer and the substrate, and the substrate corresponds at the edge angle at the top of the groove in cambered surface.As shown in the above, technical solution provided by the invention, the edge at the top of substrate respective grooves is in cambered surface, so that the edge at the top of substrate respective grooves is rounder and more smooth without precipitous wedge angle, and then the point discharge problem of fleet plough groove isolation structure can be improved, improve the reliability of fleet plough groove isolation structure.
Description
Technical field
The present invention relates to technical field of semiconductor device, more specifically, are related to a kind of fleet plough groove isolation structure and half
Conductor device.
Background technique
With the continuous development of semiconductor fabrication process, the requirement to device isolation performance is also higher and higher, researches and develops therewith
Shallow trench isolation (Shallow Trench Isolation:STI) technology out；Shallow trench isolation is made among isolating device
Structure is isolated, and insulant is filled in fleet plough groove isolation structure and achievees the purpose that the device to be isolated that insulate.Now half
In the preparation process of conductor chip, fleet plough groove isolation structure plays very important status, due to its be able to achieve it is highdensity
Isolation, is widely used in the high-density semiconductor devices such as Deep submicron devi8 and memory.Although fleet plough groove isolation structure has
There are many advantages, but the reliability of existing fleet plough groove isolation structure is to be improved.
Summary of the invention
In view of this, efficiently solving existing skill the present invention provides a kind of fleet plough groove isolation structure and semiconductor devices
Art improves the point discharge problem of fleet plough groove isolation structure, and improve fleet plough groove isolation structure can
By property.
To achieve the above object, technical solution provided by the invention is as follows:
A kind of fleet plough groove isolation structure, comprising:
Substrate with a top；
Positioned at least one groove of the top side of the substrate；
Successively there are the first dielectric layer, the second dielectric layer and third dielectric layer along the inner wall of the groove, wherein described first
The top of dielectric layer makes second dielectric layer and the lining lower than the top of second dielectric layer and the top of the substrate
The first groove is formed between bottom, and the substrate corresponds at the edge angle at the top of the groove in cambered surface.
Optionally, the fleet plough groove isolation structure further include:
Inner wall along first groove has the 4th dielectric layer.
Optionally, the 4th dielectric layer of the adjacent groove is connected and the surface of the top side that covers the substrate.
Optionally, in first groove, the fleet plough groove isolation structure further include:
The 5th dielectric layer in the inboard wall groove of the 4th dielectric layer.
Optionally, the material of the 5th dielectric layer is identical as the second dielectric layer material.
Optionally, the fleet plough groove isolation structure further include:
Deviate from the polysilicon layer of the one side of substrate positioned at the 4th dielectric layer, wherein the material of the 5th dielectric layer
Matter is identical as the polysilicon layer material.
Optionally, the top of the third dielectric layer has recess, and the concave bottom of third dielectric layer is lower than described the
The top of two dielectric layers.
Correspondingly, the present invention also provides a kind of semiconductor devices, the semiconductor devices includes:
Substrate with a top；
Positioned at least one groove of the top side of the substrate；
Successively there are the first dielectric layer, the second dielectric layer and third dielectric layer along the inner wall of the groove, wherein described first
The top of dielectric layer makes second dielectric layer and the lining lower than the top of second dielectric layer and the top of the substrate
The first groove is formed between bottom, and the substrate corresponds at the edge angle at the top of the groove in cambered surface.
Optionally, the semiconductor devices further include:
Inner wall along first groove has the 4th dielectric layer.
Optionally, the 4th dielectric layer of the adjacent groove is connected and the surface of the top side that covers the substrate.
Optionally, in first groove, the semiconductor devices further include:
The 5th dielectric layer in the inboard wall groove of the 4th dielectric layer.
Optionally, the material of the 5th dielectric layer is identical as the second dielectric layer material.
Optionally, the semiconductor devices further include:
Deviate from the polysilicon layer of the one side of substrate positioned at the 4th dielectric layer, wherein the material of the 5th dielectric layer
Matter is identical as the polysilicon layer material.
Optionally, the polysilicon layer extends over the top of second dielectric layer and the part of the third dielectric layer
Top.
Optionally, the polysilicon layer corresponds to the surface at the groove lower than the table at the top of the corresponding substrate
Face.
Optionally, the polysilicon layer at the adjacent groove is connected and covers at the top corresponding region of the substrate.
Optionally, the top of the third dielectric layer has recess, and the concave bottom of third dielectric layer is lower than described the
The top of two dielectric layers.
Optionally, have one side surface of groove up to the rare First Line being sequentially overlapped positioned at the semiconductor devices
The laminated construction of road floor, the second line layer and hard mask layer, and there is the laminated construction the exposed at least partly described third to be situated between
The hollowed out area at the top of electric layer.
Optionally, the first line layer corresponds to the surface at the groove lower than the table at the top of the corresponding substrate
Face；
And the hard mask layer is coplanar away from the one side of substrate surface.
Compared to the prior art, technical solution provided by the invention has at least the following advantages:
The present invention provides a kind of fleet plough groove isolation structure and semiconductor devices, comprising: the substrate with a top；It is located at
At least one groove of the top side of the substrate；Successively there are the first dielectric layer, the second dielectric layer along the inner wall of the groove
With third dielectric layer, wherein the top of first dielectric layer is lower than the top of second dielectric layer and the top of the substrate
Portion makes to form the first groove between second dielectric layer and the substrate, and the substrate corresponds to the top of the groove
It is in cambered surface at edge angle.As shown in the above, technical solution provided by the invention, the edge at the top of substrate respective grooves
In cambered surface, so that the edge at the top of substrate respective grooves is rounder and more smooth without precipitous wedge angle, and then shallow trench can be improved
The point discharge problem of isolation structure, improves the reliability of fleet plough groove isolation structure.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of fleet plough groove isolation structure provided by the embodiments of the present application；
Fig. 2 is the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application；
Fig. 3 is the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application；
Fig. 4 is the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application；
Fig. 5 is the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application；
Fig. 6 is a kind of structural schematic diagram of semiconductor devices provided by the embodiments of the present application；
Fig. 7 is the structural schematic diagram of another semiconductor devices provided by the embodiments of the present application；
Fig. 8 is the structural schematic diagram of another semiconductor devices provided by the embodiments of the present application.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As described in background, in the preparation process of contemporary semiconductor chip, fleet plough groove isolation structure plays act
The status of sufficient weight is widely used in the high density such as Deep submicron devi8 and memory since it is able to achieve highdensity isolation
In semiconductor devices.Although fleet plough groove isolation structure has many advantages, the reliability of existing fleet plough groove isolation structure
It is to be improved.
Based on this, the embodiment of the present application provides a kind of fleet plough groove isolation structure and semiconductor devices, efficiently solves existing
The technical issues of with the presence of technology, improves the point discharge problem of fleet plough groove isolation structure, improves fleet plough groove isolation structure
Reliability.To achieve the above object, technical solution provided by the embodiments of the present application is as follows, specifically combines Fig. 1 to Fig. 8 to this Shen
Please embodiment provide technical solution be described in detail.
Refering to what is shown in Fig. 1, being a kind of structural schematic diagram of fleet plough groove isolation structure provided by the embodiments of the present application, wherein
Fleet plough groove isolation structure includes:
Substrate 100 with a top；
Positioned at least one groove 110 of the top side of the substrate 100；
Successively there are the first dielectric layer 210, the second dielectric layer 220 and third dielectric layer 230 along the inner wall of the groove 110,
Wherein, the top of first dielectric layer 210 makes lower than the top of second dielectric layer 220 and the top of the substrate 100
The first groove 211, and the corresponding groove of the substrate 100 are formed between second dielectric layer 220 and the substrate 100
It is in cambered surface 120 at the edge angle at 110 top.
In one embodiment of the application, when making fleet plough groove isolation structure, the first dielectric that top flushes can be formed
Layer and the second dielectric layer then to form the first groove to performing etching at the top of the first dielectric layer；Also, to the first dielectric layer
Subsidiary etching processing can be carried out at the edge angle to the top of substrate respective grooves while performing etching, so that the first groove
It is formed simultaneously with the globoidal structure at the top edge angle of substrate respective grooves, and then production process can be simplified, reduction is fabricated to
This.
It should be noted that the globoidal structure of the edge angle at the top of substrate respective grooves provided by the present application does not limit to
In above-mentioned manufacture craft, in the application other embodiments, the edge angle at the top of the first groove and substrate respective grooves
Globoidal structure can also independently make, and be not specifically limited to this application, need specifically to be set according to practical application
Meter.
In one embodiment of the application, the first dielectric layer 210, the second dielectric layer 220 and third dielectric provided by the present application
The top of layer 230 is below the top of substrate 100, is not specifically limited to this application.
It should be understood that technical solution provided by the embodiments of the present application, the edge at the top of substrate respective grooves is in arc
Face so that the edge at the top of substrate respective grooves is rounder and more smooth without precipitous wedge angle, and then can improve shallow trench isolation
Point discharge problem of the structure at the top edge of substrate, improves the reliability of fleet plough groove isolation structure.
Optionally, it can be oxide dielectric that substrate provided by the embodiments of the present application, which can be silicon substrate, the first dielectric layer,
Layer, the second dielectric layer can be nitride dielectric and third dielectric layer can be oxide dielectric layer, does not make to this application
Concrete restriction, in the application other embodiments, substrate, the first dielectric layer, the second dielectric layer and third dielectric layer can also be
Other materials.
Refering to what is shown in Fig. 2, for the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application,
In, the fleet plough groove isolation structure provided by the embodiments of the present application further include:
Inner wall along first groove 211 has the 4th dielectric layer 240.
It should be understood that fleet plough groove isolation structure provided by the embodiments of the present application is also formed with along the inner wall of the first groove
Four dielectric layers are located at the edge angle at the top of substrate respective grooves due to the first groove, the 4th dielectric layer and substrate pair
Answering has overlapping region at the edge angle at the top of groove, and makes the top of fourth node layer at least covering part substrate respective grooves
The edge angle in portion further improves point discharge problem of the fleet plough groove isolation structure at the top edge of substrate, improves shallow ridges
The reliability of recess isolating structure.
Further, refering to what is shown in Fig. 3, the structure for another fleet plough groove isolation structure provided by the embodiments of the present application is shown
It is intended to, wherein the 4th dielectric layer 240 of the adjacent groove 110 is connected and the table of the top side that covers the substrate 100
Face.
In one embodiment of the application, the material of the 4th dielectric layer provided by the present application can be gate oxide, to this
Application is not specifically limited；Wherein, in the application other embodiments, the 4th dielectric layer can also be polysilicon etc..
It should be understood that while making four dielectric layers in the first groove, by the 4th dielectric layer by adjacent trenches
Between substrate the covering of top side surface, and then the top side surface of substrate is covered it is not necessary that dielectric layer is fabricated separately again
Lid, simplifies the processing procedure of fleet plough groove isolation structure, reduces the production cost.
It should be noted that can be by the top side surface of the 4th dielectric layer and substrate in the application other embodiments
Dielectric layer individually make, this application is not specifically limited, needs to carry out setting for specific processing procedure according to practical application
Meter.
Refering to what is shown in Fig. 4, be the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application,
In, at first groove 211, the fleet plough groove isolation structure further include:
The 5th dielectric layer 250 in the inboard wall groove of the 4th dielectric layer 240.
In one embodiment of the application, the material of the 5th dielectric layer provided by the present application and the second dielectric layer material
Matter can be identical, is not specifically limited to this application.
Alternatively, refering to what is shown in Fig. 5, being the structural representation of another fleet plough groove isolation structure provided by the embodiments of the present application
Figure, wherein the fleet plough groove isolation structure further include:
Deviate from the polysilicon layer 300 of the one side of substrate positioned at the 4th dielectric layer 240, wherein the 5th dielectric
The material of layer 250 is identical as 300 material of polysilicon layer.
It should be understood that fleet plough groove isolation structure provided by the embodiments of the present application includes positioned at the 4th dielectric layer away from lining
The polysilicon layer of bottom side, wherein polysilicon layer, which corresponds to, has hollowed out area at third dielectric layer, to expose third dielectric layer
Top.It wherein, can be more in production when the 5th dielectric layer provided by the embodiments of the present application is identical as the material of polysilicon layer
While crystal silicon layer, the inboard wall groove of the 4th dielectric layer is filled to obtain the 5th dielectric layer, so that the 5th dielectric layer and more
Crystal silicon layer makes simultaneously, simplifies the processing procedure of fleet plough groove isolation structure, reduces cost of manufacture.
It should be noted that in the application other embodiments, when the 5th dielectric layer is identical as the material of polysilicon layer,
5th dielectric layer and polysilicon layer can also individually be made, this application is not specifically limited.
In one embodiment of the application, as shown in Figures 1 to 5, the third dielectric layer 230 provided by the embodiments of the present application
Top have recess, and the concave bottom of third dielectric layer 230 be lower than second dielectric layer 220 top.
Correspondingly, the embodiment of the present application also provides a kind of semiconductor devices, semiconductor device provided by the embodiments of the present application
Part can be semiconductor memory etc., be not specifically limited to this application.Wherein, provided by the embodiments of the present application described partly to lead
Body device includes the fleet plough groove isolation structure that above-mentioned any one embodiment provides, specifically can be refering to what is shown in Fig. 1, the application is implemented
Example provide the semiconductor devices include:
Substrate 100 with a top；
Positioned at least one groove 110 of the top side of the substrate 100；
Successively there are the first dielectric layer 210, the second dielectric layer 220 and third dielectric layer 230 along the inner wall of the groove 110,
Wherein, the top of first dielectric layer 210 makes lower than the top of second dielectric layer 220 and the top of the substrate 100
The first groove 211, and the corresponding groove of the substrate 100 are formed between second dielectric layer 220 and the substrate 100
It is in cambered surface 120 at the edge angle at 110 top.
In one embodiment of the application, when making the fleet plough groove isolation structure in semiconductor devices, top can be formed
The first dielectric layer and the second dielectric layer flushed then to form the first groove to performing etching at the top of the first dielectric layer；And
And it can be carried out at subsidiary etching at the edge angle to the top of substrate respective grooves while being performed etching to the first dielectric layer
Reason, so that the globoidal structure at the top edge angle of the first groove and substrate respective grooves is formed simultaneously, and then can simplify production
Process reduces cost of manufacture.
It should be noted that the globoidal structure of the edge angle at the top of substrate respective grooves provided by the present application does not limit to
In above-mentioned manufacture craft, in the application other embodiments, the edge angle at the top of the first groove and substrate respective grooves
Globoidal structure can also independently make, and be not specifically limited to this application, need specifically to be set according to practical application
Meter.
In one embodiment of the application, the first dielectric layer 210, the second dielectric layer 220 and third dielectric provided by the present application
The top of layer 230 is below the top of substrate 100, is not specifically limited to this application.
It should be understood that technical solution provided by the embodiments of the present application, the edge at the top of substrate respective grooves is in arc
Face so that the edge at the top of substrate respective grooves is rounder and more smooth without precipitous wedge angle, and then can improve semiconductor devices
In point discharge problem of the fleet plough groove isolation structure at the top edge of substrate, improve the reliable of fleet plough groove isolation structure
Property.
Optionally, it can be oxide dielectric that substrate provided by the embodiments of the present application, which can be silicon substrate, the first dielectric layer,
Layer, the second dielectric layer can be nitride dielectric and third dielectric layer can be oxide dielectric layer, does not make to this application
Concrete restriction, in the application other embodiments, substrate, the first dielectric layer, the second dielectric layer and third dielectric layer can also be
Other materials.
Refering to what is shown in Fig. 2, for the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application,
In, the semiconductor devices provided by the embodiments of the present application further include:
Inner wall along first groove 211 has the 4th dielectric layer 240.
It should be understood that the fleet plough groove isolation structure in semiconductor devices provided by the embodiments of the present application is along the first groove
Inner wall is also formed with the 4th dielectric layer, is located at the edge angle at the top of substrate respective grooves due to the first groove, the 4th
There is overlapping region at the edge angle at the top of dielectric layer and substrate respective grooves, and fourth node layer at least covering part is served as a contrast
The edge angle at the top of bottom respective grooves further improves point discharge of the fleet plough groove isolation structure at the top edge of substrate
Problem improves the reliability of fleet plough groove isolation structure.
Further, refering to what is shown in Fig. 3, the structure for another fleet plough groove isolation structure provided by the embodiments of the present application is shown
It is intended to, wherein the 4th dielectric layer 240 of the adjacent groove 110 is connected and the table of the top side that covers the substrate 100
Face.
In one embodiment of the application, the material of the 4th dielectric layer provided by the present application can be gate oxide, to this
Application is not specifically limited；Wherein, in the application other embodiments, the 4th dielectric layer can also be polysilicon etc..
It should be understood that while making four dielectric layers in the first groove, by the 4th dielectric layer by adjacent trenches
Between substrate the covering of top side surface, and then the top side surface of substrate is covered it is not necessary that dielectric layer is fabricated separately again
Lid, simplifies the processing procedure of the fleet plough groove isolation structure in semiconductor devices, reduces the production cost.
It should be noted that can be by the top side surface of the 4th dielectric layer and substrate in the application other embodiments
Dielectric layer individually make, this application is not specifically limited, needs to carry out setting for specific processing procedure according to practical application
Meter.
Refering to what is shown in Fig. 4, be the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application,
In, at first groove 211, the semiconductor devices further include:
The 5th dielectric layer 250 in the inboard wall groove of the 4th dielectric layer 240.
The fleet plough groove isolation structure in semiconductor devices is it is found that the 5th dielectric layer provided by the present application as shown in Figure 4
Material can be identical with the second dielectric layer material；Alternatively, the 5th dielectric layer can also be other materials, with specific reference to figure
It is the structural schematic diagram of another fleet plough groove isolation structure provided by the embodiments of the present application, wherein the semiconductor device shown in 5
Part further include:
Deviate from the polysilicon layer 300 of the one side of substrate positioned at the 4th dielectric layer 240, wherein the 5th dielectric
The material of layer 250 is identical as 300 material of polysilicon layer.
It should be understood that the fleet plough groove isolation structure in semiconductor devices provided by the embodiments of the present application includes positioned at
Four dielectric layers deviate from the polysilicon layer of one side of substrate, wherein the polysilicon layer provided by the embodiments of the present application, which can extend, to be covered
Cover the top of second dielectric layer and the top of the third dielectric layer.That is, polysilicon layer provided by the embodiments of the present application covers
The top of the second dielectric layer of lid, and polysilicon layer is corresponded to hollowed out area at third dielectric layer, to cover third dielectric layer
Atop part, and expose at the top of another part of third dielectric layer that (its exposed part can correspond to the center of third dielectric layer
Region).It wherein, can be more in production when the 5th dielectric layer provided by the embodiments of the present application is identical as the material of polysilicon layer
While crystal silicon layer, the inboard wall groove of the 4th dielectric layer is filled to obtain the 5th dielectric layer, so that the 5th dielectric layer and more
Crystal silicon layer makes simultaneously, simplifies the processing procedure of fleet plough groove isolation structure, reduces cost of manufacture.
In one embodiment of the application, the polysilicon layer provided by the present application can be the layer structure of uniform thickness, i.e.,
As shown in connection with fig. 5, the surface at the correspondence of the polysilicon layer 300 provided by the embodiments of the present application groove 110 is lower than described in correspondence
Surface at the top of substrate 100.
It should be noted that in the application other embodiments, when the 5th dielectric layer is identical as the material of polysilicon layer,
5th dielectric layer and polysilicon layer can also individually be made, this application is not specifically limited.
In one embodiment of the application, the embodiment of the present application is located at position in semiconductor devices for fleet plough groove isolation structure
It is not specifically limited, wherein fleet plough groove isolation structure is located at position difference in semiconductor devices, at fleet plough groove isolation structure
Corresponding construction is not also identical.That is, provided by the embodiments of the present application be located at the semiconductor devices with one side surface of groove
Upper to have functional film layer, functional film layer can be laminated construction；I.e. functional film layer can be located at the 4th dielectric layer and deviate from substrate one
Side surface, functional film layer may be located on polysilicon layer away from one side of substrate surface, be not specifically limited to this application.Specifically
, in technical solution provided by the embodiments of the present application, being located at that the semiconductor devices has can be on one side surface of groove
The laminated construction of the first line layer, the second line layer and hard mask layer that are at least sequentially overlapped, and the laminated construction has
The hollowed out area at the top of the exposed at least partly described third dielectric layer.
It is located at polysilicon layer below with functional film layer to carry out technical solution provided by the present application away from one side of substrate surface
It specifically describes.As shown in fig. 6, being a kind of structural schematic diagram of semiconductor devices provided by the embodiments of the present application, wherein in shallow ridges
When 4th dielectric layer 240 of recess isolating structure is provided with polysilicon layer 300 away from one side of substrate, in polysilicon layer 300 away from lining
100 side of bottom is also formed with functional film layer 400, wherein has hollowed out area at the corresponding third dielectric layer 230 of functional film layer 400.
It should be understood that as shown in fig. 6, the 4th dielectric layer 240 of adjacent trenches provided by the embodiments of the present application 110 can be with
It is connected and covers and is at the surface and the adjacent groove 110 provided by the embodiments of the present application of the top side of substrate 100 more
Crystal silicon layer 300 is connected and covers at the top corresponding region of the substrate 100.That is, polysilicon provided by the embodiments of the present application
Layer 300 can cover the 4th dielectric layer 240 and extend over into adjacent trenches 110 at the top of third dielectric layer 230, and more
There is hollowed out area at the corresponding third dielectric layer 230 of crystal silicon layer 300.And functional film layer 400 provided by the embodiments of the present application
Deviate from 100 side of substrate in polysilicon layer 300, wherein functional film layer 400 can cover polysilicon layer 300, and functional film layer
Equally there is hollowed out area at 400 corresponding third dielectric layers 230, also that is, functional film layer 400 can across adjacent two groove 110,
And adjacent two groove 110 is connected.In one embodiment of the application, fleet plough groove isolation structure provided by the present application is in and partly leads
Position is different in body device, and the structure of functional film layer is not also identical.Wherein, provided by the embodiments of the present application to be located at the polysilicon
First line layer, the second line layer and the hard mask layer that layer is at least sequentially overlapped away from the one side of substrate, wherein First Line
Road floor, the second line layer and hard mask layer have hollowed out area identical with polysilicon layer.It is i.e. as shown in fig. 7, real for the application
Apply the structural schematic diagram of another semiconductor devices of example offer, wherein functional film layer provided by the embodiments of the present application can be down to
It less include the first line layer 410 being sequentially overlapped from polysilicon layer 300, the second line layer 420 and hard mask layer 430.Wherein,
The material of first line layer 410 provided by the embodiments of the present application can include but is not limited to titanium or titanium nitride, the second line layer 420
Material can be metal (such as tungsten), and the material of hard mask layer 430 can include but is not limited to nitride.
In one embodiment of the application, the surface that the first line layer that the application passes through corresponds at the groove is lower than
Surface at the top of the corresponding substrate；And the hard mask layer is coplanar away from the one side of substrate surface.
It should be understood that as shown in fig. 7, the thickness of polysilicon layer provided by the embodiments of the present application 300 is uniform, and due to
The first dielectric layer 210, the second dielectric layer 220 and third dielectric layer at groove 110 with top lower than the top of substrate 100
230, so, polysilicon layer 300 makes polysilicon layer 300 away from substrate away from the surface of 100 side of substrate and non-planar
The surface of 100 sides is in face shape of the surface at groove 110 lower than the surface at the top of substrate 100.And due to
First line layer 410 and the second line layer 420 equally can be layer structure in homogeneous thickness, so that first line layer 410 and the
Two line layers 420 are similarly the surface at groove 110 away from 100 1 side surface of substrate and are lower than at the top of substrate 100
Surface structure.And hard mask layer 430 provided by the embodiments of the present application can be flatness layer, deviate from 100 side of substrate
Surface be it is coplanar, this application is not specifically limited.
And as shown in figure 8, being the structural schematic diagram of another semiconductor devices provided by the embodiments of the present application, wherein this
The semiconductor devices that application embodiment provides can also be directly filled in the 4th dielectric layer 240 away from 100 side of substrate
To filled layer 500, wherein the material of filled layer 500 provided by the embodiments of the present application includes but is not limited to oxide.
It should be noted that semiconductor device structure shown in above-mentioned Fig. 6 to Fig. 8 be only the application be suitable for shallow trench every
From several in corresponding construction had at structure, this application is not specifically limited, is needed according to semiconductor device type, shallow
Groove isolation construction is located at position in semiconductor devices and is specifically designed.
In one embodiment of the application, as shown in Figures 1 to 8, the third dielectric layer 230 provided by the embodiments of the present application
Top have recess, and the concave bottom of third dielectric layer 230 be lower than second dielectric layer 220 top.
The embodiment of the present application provides a kind of fleet plough groove isolation structure and semiconductor devices, comprising: the lining with a top
Bottom；Positioned at least one groove of the top side of the substrate；Inner wall along the groove successively has the first dielectric layer, second
Dielectric layer and third dielectric layer, wherein top of the top of first dielectric layer lower than second dielectric layer and the lining
The top at bottom makes to form the first groove between second dielectric layer and the substrate, and the substrate corresponds to the groove
It is in cambered surface at the edge angle at top.As shown in the above, technical solution provided by the embodiments of the present application, substrate respective grooves
The edge at top be in cambered surface so that the edge at the top of substrate respective grooves without precipitous wedge angle rounder and more smooth, Jin Erneng
The point discharge problem for enough improving fleet plough groove isolation structure, improves the reliability of fleet plough groove isolation structure.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (19)
1. a kind of fleet plough groove isolation structure characterized by comprising
Substrate with a top；
Positioned at least one groove of the top side of the substrate；
Successively there are the first dielectric layer, the second dielectric layer and third dielectric layer along the inner wall of the groove, wherein first dielectric
The top of layer lower than the top of second dielectric layer and the top of the substrate, make second dielectric layer and the substrate it
Between form the first groove, and the substrate corresponds at the edge angle at the top of the groove in cambered surface.
2. fleet plough groove isolation structure according to claim 1, which is characterized in that the fleet plough groove isolation structure further include:
Inner wall along first groove has the 4th dielectric layer.
3. fleet plough groove isolation structure according to claim 2, which is characterized in that the 4th dielectric layer phase of the adjacent groove
It is connected to and covers the surface of the top side of the substrate.
4. fleet plough groove isolation structure according to claim 2 or 3, which is characterized in that described shallow in first groove
Groove isolation construction further include:
The 5th dielectric layer in the inboard wall groove of the 4th dielectric layer.
5. fleet plough groove isolation structure according to claim 4, which is characterized in that the material of the 5th dielectric layer with it is described
Second dielectric layer material is identical.
6. fleet plough groove isolation structure according to claim 4, which is characterized in that the fleet plough groove isolation structure further include:
Positioned at the 4th dielectric layer deviate from the one side of substrate polysilicon layer, wherein the material of the 5th dielectric layer with
The polysilicon layer material is identical.
7. fleet plough groove isolation structure according to claim 1, which is characterized in that the top of the third dielectric layer has recessed
It falls into, and the concave bottom of third dielectric layer is lower than the top of second dielectric layer.
8. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes:
Substrate with a top；
Positioned at least one groove of the top side of the substrate；
Successively there are the first dielectric layer, the second dielectric layer and third dielectric layer along the inner wall of the groove, wherein first dielectric
The top of layer lower than the top of second dielectric layer and the top of the substrate, make second dielectric layer and the substrate it
Between form the first groove, and the substrate corresponds at the edge angle at the top of the groove in cambered surface.
9. semiconductor devices according to claim 8, which is characterized in that the semiconductor devices further include:
Inner wall along first groove has the 4th dielectric layer.
10. semiconductor devices according to claim 9, which is characterized in that the 4th dielectric layer of the adjacent groove is connected
The surface of top side that is logical and covering the substrate.
11. semiconductor devices according to claim 9, which is characterized in that in first groove, the semiconductor device
Part further include:
The 5th dielectric layer in the inboard wall groove of the 4th dielectric layer.
12. semiconductor devices according to claim 11, which is characterized in that the material of the 5th dielectric layer and described the
Two dielectric layer materials are identical.
13. semiconductor devices according to claim 11, which is characterized in that the semiconductor devices further include:
Positioned at the 4th dielectric layer deviate from the one side of substrate polysilicon layer, wherein the material of the 5th dielectric layer with
The polysilicon layer material is identical.
14. semiconductor devices according to claim 13, which is characterized in that the polysilicon layer extends over described second
The atop part of the top of dielectric layer and the third dielectric layer.
15. semiconductor devices according to claim 14, which is characterized in that the polysilicon layer corresponds at the groove
Surface is lower than the surface at the top of the corresponding substrate.
16. semiconductor devices according to claim 14, which is characterized in that the polysilicon layer at the adjacent groove is connected
At top corresponding region that is logical and covering the substrate.
17. semiconductor devices according to claim 14, which is characterized in that the top of the third dielectric layer has recessed
It falls into, and the concave bottom of third dielectric layer is lower than the top of second dielectric layer.
18. according to semiconductor devices described in claim 9-17 any one, which is characterized in that be located at the semiconductor devices
With one side surface of groove up to the rare first line layer being sequentially overlapped, the lamination knot of the second line layer and hard mask layer
Structure, and the laminated construction has the hollowed out area at the top of the exposed at least partly described third dielectric layer.
19. semiconductor devices according to claim 18, which is characterized in that the first line layer corresponds at the groove
Surface lower than the surface at the top of the corresponding substrate；
And the hard mask layer is coplanar away from the one side of substrate surface.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910919266.9A CN110518062A (en) | 2019-09-26 | 2019-09-26 | A kind of fleet plough groove isolation structure and semiconductor devices |
| US16/696,765 US11069774B2 (en) | 2019-09-26 | 2019-11-26 | Shallow trench isolation structure and semiconductor device with the same |
| US17/349,906 US11824087B2 (en) | 2019-09-26 | 2021-06-16 | Shallow trench isolation structure and semiconductor device with the same |
| US18/380,616 US20240047519A1 (en) | 2019-09-26 | 2023-10-16 | Shallow trench isolation structure and semiconductor device with the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910919266.9A CN110518062A (en) | 2019-09-26 | 2019-09-26 | A kind of fleet plough groove isolation structure and semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110518062A true CN110518062A (en) | 2019-11-29 |
Family
ID=68633757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910919266.9A Pending CN110518062A (en) | 2019-09-26 | 2019-09-26 | A kind of fleet plough groove isolation structure and semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110518062A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113437134A (en) * | 2021-06-22 | 2021-09-24 | 福建省晋华集成电路有限公司 | Semiconductor structure, semiconductor structure preparation method and semiconductor device |
| WO2022147986A1 (en) * | 2021-01-05 | 2022-07-14 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11881428B2 (en) | 2021-01-05 | 2024-01-23 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000002925A (en) * | 1998-06-24 | 2000-01-15 | 윤종용 | Trench isolation structure for semiconductor device and production method thereof |
| US6165854A (en) * | 1998-05-04 | 2000-12-26 | Texas Instruments - Acer Incorporated | Method to form shallow trench isolation with an oxynitride buffer layer |
| US6709924B1 (en) * | 2002-11-12 | 2004-03-23 | Advanced Micro Devices, Inc. | Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate |
| US20050151183A1 (en) * | 2004-01-14 | 2005-07-14 | Taiwan Semiconductor Manufacturing Co. | Novel random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes |
| US20050167778A1 (en) * | 2004-02-03 | 2005-08-04 | Shin-Hye Kim | Shallow trench isolation structure with converted liner layer |
| CN101000910A (en) * | 2006-01-13 | 2007-07-18 | 三星电子株式会社 | Trench isolation type semiconductor device and related method of manufacture |
| US20070205489A1 (en) * | 2006-03-01 | 2007-09-06 | Armin Tilke | Methods of fabricating isolation regions of semiconductor devices and structures thereof |
| CN102456606A (en) * | 2010-10-19 | 2012-05-16 | 上海宏力半导体制造有限公司 | Forming method of shallow trough insulation structure |
| CN104078412A (en) * | 2014-07-25 | 2014-10-01 | 上海华力微电子有限公司 | Shallow groove isolation technology |
| CN107134486A (en) * | 2017-04-28 | 2017-09-05 | 睿力集成电路有限公司 | Memory |
| CN108269804A (en) * | 2016-12-30 | 2018-07-10 | 联华电子股份有限公司 | The production method of semiconductor storage |
| CN210142652U (en) * | 2019-09-26 | 2020-03-13 | 福建省晋华集成电路有限公司 | Shallow trench isolation structure and semiconductor device |
-
2019
- 2019-09-26 CN CN201910919266.9A patent/CN110518062A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6165854A (en) * | 1998-05-04 | 2000-12-26 | Texas Instruments - Acer Incorporated | Method to form shallow trench isolation with an oxynitride buffer layer |
| KR20000002925A (en) * | 1998-06-24 | 2000-01-15 | 윤종용 | Trench isolation structure for semiconductor device and production method thereof |
| US6709924B1 (en) * | 2002-11-12 | 2004-03-23 | Advanced Micro Devices, Inc. | Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate |
| US20050151183A1 (en) * | 2004-01-14 | 2005-07-14 | Taiwan Semiconductor Manufacturing Co. | Novel random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes |
| US20050167778A1 (en) * | 2004-02-03 | 2005-08-04 | Shin-Hye Kim | Shallow trench isolation structure with converted liner layer |
| CN101000910A (en) * | 2006-01-13 | 2007-07-18 | 三星电子株式会社 | Trench isolation type semiconductor device and related method of manufacture |
| US20070205489A1 (en) * | 2006-03-01 | 2007-09-06 | Armin Tilke | Methods of fabricating isolation regions of semiconductor devices and structures thereof |
| CN102456606A (en) * | 2010-10-19 | 2012-05-16 | 上海宏力半导体制造有限公司 | Forming method of shallow trough insulation structure |
| CN104078412A (en) * | 2014-07-25 | 2014-10-01 | 上海华力微电子有限公司 | Shallow groove isolation technology |
| CN108269804A (en) * | 2016-12-30 | 2018-07-10 | 联华电子股份有限公司 | The production method of semiconductor storage |
| CN107134486A (en) * | 2017-04-28 | 2017-09-05 | 睿力集成电路有限公司 | Memory |
| CN210142652U (en) * | 2019-09-26 | 2020-03-13 | 福建省晋华集成电路有限公司 | Shallow trench isolation structure and semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022147986A1 (en) * | 2021-01-05 | 2022-07-14 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11881428B2 (en) | 2021-01-05 | 2024-01-23 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| CN113437134A (en) * | 2021-06-22 | 2021-09-24 | 福建省晋华集成电路有限公司 | Semiconductor structure, semiconductor structure preparation method and semiconductor device |
| CN113437134B (en) * | 2021-06-22 | 2022-09-02 | 福建省晋华集成电路有限公司 | Semiconductor structure, semiconductor structure preparation method and semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110518062A (en) | A kind of fleet plough groove isolation structure and semiconductor devices | |
| CN104465565B (en) | Semiconductor device | |
| US20110101450A1 (en) | Semiconductor device with buried gates and buried bit lines and method for fabricating the same | |
| KR20110121360A (en) | Method for manufacturing semiconductor device prevented pattern leaning | |
| WO2022198831A1 (en) | Capacitor contact structure of memory device and preparation method therefor | |
| US20120264268A1 (en) | Methods of forming electrical isolation regions between gate electrodes | |
| KR100660030B1 (en) | Trench isolation structure and method of forming the same | |
| EP3021360A1 (en) | Contact structure for memory device and a method of manufacture | |
| US20060118883A1 (en) | Trench in semiconductor device and formation method thereof | |
| KR100723767B1 (en) | Flash memory device and manufacturing method thereof | |
| JP5090619B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6621117B2 (en) | Semiconductor device having memory cell and peripheral circuitry with dummy electrode | |
| KR100445506B1 (en) | Method of producing semiconductor device | |
| CN210142652U (en) | Shallow trench isolation structure and semiconductor device | |
| CN110896047A (en) | Shallow trench isolation structure and preparation method of semiconductor device | |
| CN112614849B (en) | Three-dimensional memory structure and preparation method thereof | |
| TW200414327A (en) | Semiconductor memory device and method for fabricating the same | |
| US20040002209A1 (en) | Method for forming contact plug of semiconductor device | |
| US11824087B2 (en) | Shallow trench isolation structure and semiconductor device with the same | |
| KR20070063821A (en) | Method for forming isolation layer of semiconductor device | |
| US7508029B2 (en) | Semiconductor device and method for fabricating the same | |
| US20240105788A1 (en) | Local interconnect at backside to enable flexible routing across different cell | |
| JP2012060035A (en) | Semiconductor device and method of manufacturing the same | |
| US20240112948A1 (en) | Semiconductor device and method having deep trench isolation | |
| US6423612B1 (en) | Method of fabricating a shallow trench isolation structure with reduced topography |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |