KR20000002925A - Trench isolation structure for semiconductor device and production method thereof - Google Patents

Abstract

PURPOSE: A trench isolation structure is provided to improve the device characteristic of a semiconductor device by repressing the stress generated in the side wall of the trench. CONSTITUTION: The trench isolation structure comprises the steps of forming; a trench(400) on the semiconductor substrate(100); a spacer(530) by an amorphous carbon or an organic polymer in the part of the side wall of the trench; a first isolation film to cover the spacer; a void formed the part of the side wall of the trench and the space between the first isolation film in the part of the side wall by removing the spacer; the second isolation film on the first isolation film.

Description

Trench isolation structure of semiconductor device and manufacturing method

TECHNICAL FIELD This invention relates to a semiconductor device. Specifically, It is related with a trench isolation structure and its manufacturing method.

Device isolation methods used in semiconductor devices include a method of separating devices based on a LOCOS (LOCal Oxidation of Silicon) device isolation structure and a method of using a trench device isolation structure. A method using a trench isolation structure is implemented by directly forming a trench in a semiconductor substrate and filling the trench with an insulator. Such a trench isolation structure is considered to be one of methods for overcoming a reduction in isolation structure due to high integration of semiconductor devices.

1 schematically illustrates a conventional trench device isolation structure.

Specifically, various problems may occur when the trench isolation structure is applied to a semiconductor device. For example, a problem of high junction leakage current may be derived. One of the important factors of the problem such as the generation of junction leakage current occurs when forming the trench. For example, when a trench is formed in the semiconductor substrate 10, a damage layer or the like occurs in a side wall of the trench or the like by an etching process or the like. Such a damage film may act as a path of leakage current.

In addition, the insulating film 20 filling the trench generally uses a CVD-oxide film or the like formed by a chemical vapor deposition (hereinafter referred to as "CVD") method. When the insulating film 20 such as the CVD-oxide film fills the trench, a stress change of the insulating film 20 may occur. That is, a stress change may occur due to a difference in thermal expansion coefficient between the semiconductor substrate 10 and the insulating film 20. Moreover, such stress change can be deepened in a subsequent heat treatment process of heat treating the CVD oxide film or the like. Such a change in stress may generate a pit or the like in the semiconductor substrate 10. That is, dislocations and the like may be concentrated at a site where stress may be concentrated, such as an edge or a corner of the trench. Accordingly, a defect such as a pit such as a crack may occur in the corner or edge portion. Such a defect, such as a fit, can be a path of the junction leakage current, which increases the junction leakage current.

The present invention is to provide a trench isolation structure of a semiconductor device that can improve the electrical characteristics of the semiconductor device, such as junction leakage current by preventing stress, such as fit to suppress the stress caused on the sidewalls of the trench There is.

Another technical problem to be solved by the present invention is to suppress the occurrence of stress on the sidewalls of the trench to prevent defects such as pit, etc. to improve the electrical characteristics of the semiconductor device such as junction leakage current manufacturing method of the trench device isolation structure of the semiconductor device To provide.

1 is a cross-sectional view schematically illustrating a conventional trench device isolation structure.

2 is a cross-sectional view schematically showing an embodiment of the trench device isolation structure according to the present invention.

3 to 8 are cross-sectional views schematically illustrating a first embodiment of the method for manufacturing a trench isolation structure according to the present invention.

9 to 13 are cross-sectional views schematically illustrating a second embodiment of a method for fabricating a trench isolation structure according to the present invention.

One aspect of the present invention for achieving the above technical problem is a trench isolation structure of a semiconductor device having a semiconductor substrate having a trench and an insulating film pattern to form a void in the sidewall portion of the trench and fill the trench To provide. A diffusion barrier layer is further provided to cover an inner wall of the trench with a silicon nitride layer and the lower layer of the insulating layer pattern and the void to prevent material movement to the semiconductor substrate.

One aspect of the present invention for achieving the above another technical problem is to form a trench in a semiconductor substrate. Spacers are formed on the sidewalls of the trench with amorphous carbon or organic polymer. As the amorphous carbon, amorphous hydrated carbon, amorphous fluorinated carbon, or the like is used. In addition, as the organic polymer, parylene, parylene fluoride, polyarylether, fluorinated polyarylether or silk may be used.

Prior to forming the spacers, a first insulating layer is formed to cover the inner wall of the trench with a silicon nitride film or the like to form a diffusion barrier layer to prevent material movement to the semiconductor substrate. Forming the spacer

The spacer layer may be formed to cover the inner wall of the trench, and the spacer layer may be patterned by an anisotropic etching method to form a spacer remaining on the sidewall of the trench.

Next, the spacer is removed to form a void including a space between the sidewall portion of the trench and the first insulating layer in the sidewall portion. The removing of the spacer may include oxidizing the amorphous carbon or the organic polymer by performing an oxidation process on a resultant in which the first insulating layer is formed, and discharging the vapor phase by the oxidation through the first insulating layer. Is performed. As the oxidation process, an oxygen annealing process, a wet oxidation process, an oxygen plasma treatment process, or the like is used. A second insulating layer filling the trench is formed on the first insulating layer. Thereafter, the second insulating layer is densified.

Another aspect of the present invention for achieving the above technical problem is to form a trench in a semiconductor substrate. A spacer film covering the sidewalls of the trench is formed of an organic polymer containing carbon or amorphous carbon. Before forming the spacer layer, a diffusion barrier layer covering the inner wall of the trench to prevent material movement to the semiconductor substrate is formed of a silicon nitride layer or the like. A third insulating film is formed to cover the spacer film. The third insulating layer and the spacer layer are patterned by an anisotropic etching method to form a third insulating layer pattern exposing the spacer and a portion of the spacer on the sidewall portion of the trench. A first insulating layer is formed to cover the exposed spacers and the third insulating layer pattern.

Next, the spacers are removed to form voids formed in the sidewalls of the trench, which are spaces between the sidewalls of the trench and the third insulating layer pattern. The removing of the spacer may be performed by oxidizing the amorphous carbon or the organic polymer by performing an oxidation process on the resultant in which the first insulating layer is formed, and discharging the gaseous phase by the oxidation through the first insulating layer. As the oxidation process, an oxygen annealing process, a wet oxidation process, an oxygen plasma treatment process, or the like is used. A second insulating layer filling the trench is formed on the first insulating layer. Thereafter, the second insulating film is densified.

According to the present invention, it is possible to suppress the occurrence of stress on the sidewalls of the trench. Therefore, it is possible to prevent defects such as pitting and the like and to improve electrical characteristics of the semiconductor device such as junction leakage current.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the thickness of the film and the like in the drawings are exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings mean the same elements. Also, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.

2 is a cross-sectional view schematically showing an embodiment of the trench device isolation structure according to the present invention.

Specifically, according to the present invention, the trench isolation structure includes a semiconductor substrate 100 having a trench formed therein and an insulating layer pattern 500 filling the trench. The insulating layer pattern 500 forms a void 535 including a space between a lower surface of the insulating layer pattern 500 and an inner wall of the trench, on a side wall of the trench. In addition, a diffusion barrier layer covering an inner wall of the trench may be provided as a lower layer such as the insulating layer pattern 500 and the void 535, or the like, using a silicon nitride layer (SiN layer). The diffusion barrier serves to prevent material movement or diffusion into the semiconductor substrate 100.

Embodiments of the trench isolation structure according to the present invention as described above can prevent the occurrence of defects such as stress or fit, etc. in the semiconductor substrate 100 forming the trench inner wall. That is, even if stress or the like is caused by the process of forming the insulating film pattern 500, the void 535 is alleviated. As such, the stress is alleviated, and defects such as fit and the like in the edge portion or the corner portion of the trench are suppressed. Accordingly, poor electrical characteristics such as junction leakage current can be suppressed, so that the reliability of the semiconductor device can be improved.

3 to 8 are cross-sectional views schematically illustrating a first embodiment of the method for manufacturing a trench isolation structure according to the present invention.

3 schematically illustrates a step of forming a trench 400 in a semiconductor substrate 100.

Specifically, after forming a pad oxide layer 200 or the like on the semiconductor substrate 100, a mask pattern 300 exposing a part of the surface of the semiconductor substrate 100 is formed. SiN film or the like is used as the mask pattern 300. Next, the trench 400 is formed by etching the exposed semiconductor substrate 100 using the mask pattern 300 as an etch mask.

Thereafter, the inner wall of the trench is oxidized by an oxidation process or the like to form a relaxed film (not shown). As the relaxed film, a silicon oxide film formed by the oxidation process or the like is used. The alleviation layer serves to alleviate a damage layer or the like generated in the etching process of forming the trench 400.

Next, a diffusion barrier 510 may be formed on the alleviation layer to cover the inner wall of the trench 400. The diffusion barrier 510 serves to prevent material migration or diffusion into the semiconductor substrate 100 forming the sidewalls of the trench 400, which may occur in a subsequent process. That is, the diffusion barrier layer 510 serves to prevent impurity movement or diffusion from the spacer layer 530 of FIG. 4 or the insulating film 570 of FIG. 8 to the semiconductor substrate 100. ). Therefore, the diffusion barrier 510 is formed using a film that can prevent material migration or diffusion such as a SiN film.

4 schematically illustrates a step of forming a spacer layer 530 covering an inner wall of the trench 400.

In detail, a spacer layer 530 is formed on the inner wall of the trench 400, that is, on the alleviation layer or the diffusion barrier layer 510. The spacer layer 530 is formed of a film that can be easily discharged and removed by a gaseous phase in a subsequent process. For example, the spacer layer may be formed by depositing amorphous carbon, that is, amorphous carbon such as hydrogen-containing amorphous C: H or fluorine-containing amorphous C: F. 530).

Or parylene as represented by formula (1), parylene fluoride as represented by formula (2), polyarylether as represented by formula (3), fluorinated polyaryl as represented by formula (4) An organic polymer containing carbon such as a fluoronated polyarylether or the like is deposited by CVD or the like to form a spacer film 530.

As the organic polymer, a polymer or silk formed from a monomer as shown in Chemical Formula 5 may be used.

The film formed of amorphous carbon or organic polymer containing carbon as described above can be converted into a gaseous phase such as carbon dioxide gas (CO ₂ ) by an oxidation process or the like. Therefore, it can be effectively removed in the process of removing the subsequent spacer 535.

5 schematically illustrates a step of patterning the spacer film 530 to form the spacer 533.

In detail, the spacer layer 530 is patterned by an anisotropic etching method until the bottom surface of the trench 400 or the diffusion barrier layer 510 is exposed. Accordingly, a part of the spacer layer 530 remains in the sidewall portion of the trench 400, more specifically, the corner portion of the trench 400. That is, the spacer 533 is formed.

6 schematically illustrates a step of forming the first insulating film 550 covering the spacer 533.

Specifically, the first insulating film 550 covering the spacer 533 is thinly formed. After the first insulating layer 550 is formed, the spacer 533 is changed to a vapor phase or a gas phase and removed. At this time, the gaseous phase must be removed by passing through or passing through the first insulating layer 550. Therefore, the first insulating layer 550 is thinly formed with a film having a high transmittance to the gas phase. For example, a silicon oxide film formed by a CVD method, a bias sputtering method, or the like is used as the first insulating film 550. In general, the transmittance is a function of the path through which it is transmitted. Therefore, the thickness of the first insulating layer 550 may be thin enough to be supported without changing the shape of the first insulating layer 550 when the spacer 533 is removed. Do.

FIG. 7 schematically illustrates a step of removing the spacer 533 to form a void 535.

In detail, an oxidation process is performed on a resultant in which the first insulating layer 550 is formed. For example, it performs a process that can lead to oxidation, such as oxygen annealing (O ₂ annealing) process, the wet oxidation (wet oxidation) process or an oxygen plasma treatment (O ₂ plasma treatment) step. By such an oxidation process, the carbon-containing material constituting the spacer 533 is oxidized and converted into a gaseous phase. That is, the amorphous carbon or organic polymer is oxidized and converted into a gaseous phase such as an oxide gas such as carbon dioxide (CO ₂ ) or the like. The gaseous phase passes through the first insulating film 550 by the gas pressure and is discharged to the outside. Since the spacer 533 is vaporized and removed as described above, the space occupied by the spacer 533 is left as an empty space, that is, a void 535.

The gaseous phase generated in the oxidation process as described above may be removed through the first insulating layer 550 and moved to the lower semiconductor substrate 100. In order to prevent this, the diffusion barrier 510 is formed as described above to protect the inner wall of the trench 400 from the gas phase. The diffusion barrier 500 is formed to be dense so as to prevent the movement or diffusion of a material, such as a SiN film, to prevent diffusion of the gas phase into the semiconductor substrate 100.

8 schematically illustrates a step of forming the second insulating layer 570 on the first insulating layer 550.

In detail, a second insulating layer 570 is formed on the first insulating layer 550 to fill the trench 400. For example, the trench 400 is buried by depositing a silicon oxide film or the like using a CVD method. Next, the second insulating film 570 and the like are planarized to form an insulating film pattern 500 as shown in FIG. 2. That is, the insulating film made of the first insulating film 550, the second insulating film 570, or the like is planarized by chemical mechanical polishing (hereinafter referred to as "CMP") method.

Densification of the second insulating layer 570 may be further performed. Such densification improves the film quality of the second insulating film 570 and the like. In the trench isolation structure according to the present invention, the semiconductor substrate 100 forming the inner wall of the trench 400 may be damaged due to the stress change that may occur in the densification process or the process of forming the second insulating layer 270. Is prevented. That is, in the exemplary embodiment of the present invention, the void 535 is introduced, and thus, a role of alleviating or buffering the stress generated in the above-described process may be implemented. Accordingly, defects such as cracks or pits may be suppressed in the inner wall of the trench 400, particularly, the semiconductor substrate 100 in the corner portion. Therefore, it is possible to prevent the junction leakage current from occurring when the semiconductor device is driven.

9 to 13 are cross-sectional views schematically illustrating a second embodiment of a method for fabricating a trench isolation structure according to the present invention.

In the second embodiment, the spacer 533 is formed by a method different from that in the first embodiment. Further, in the second embodiment, the same reference numerals as in the first embodiment denote the same elements.

9 schematically illustrates a process of forming a spacer layer 530 and a third insulating layer 540 covering an inner wall of the trench 400.

Specifically, the trench 400 and the like are formed as described with reference to FIG. 3. As described with reference to FIG. 4, a spacer film 530 is formed on the inner wall of the trench 400, that is, on the relief layer or the diffusion barrier layer 510. That is, as described with reference to FIG. 4, the spacer film 530 is formed by depositing a film quality, for example, amorphous carbon or an organic polymer, which can be easily discharged and removed in the gas phase.

Next, a third insulating film 540 is formed to cover the spacer film 530. The third insulating layer 540 may be formed using the same method as the method of forming the first insulating layer 550 described with reference to FIG. 5. For example, a thin silicon oxide film or the like is formed by the CVD method or the bias sputtering method to be used as the third insulating film 540.

FIG. 10 schematically illustrates a step of forming the third insulating layer pattern 545 and the spacer 533 by patterning the third insulating layer 540 and the spacer layer 530.

In detail, the third insulating layer 540 and the spacer layer 530 are patterned by anisotropic etching or the like until the bottom surface of the trench 400 or the diffusion barrier layer 510 is exposed. Accordingly, a part of the spacer layer 530 remains in the sidewall portion of the trench 400, more specifically, the corner portion of the trench 400. That is, the spacer 533 is formed. A third insulating film pattern 545 is formed to expose a portion of the spacer 533. As the third insulating layer pattern 545 is formed, the setting of the area of the spacer 533 covering the sidewall portion of the trench 400, for example, the corner portion, becomes clear. And, the area can be secured to be wider than in the first embodiment. Therefore, the area of the semiconductor substrate 100 to which the stress relaxation effect or the buffer effect by the voids formed later (535 in FIG. 12) is affected also increases. Therefore, the stress relaxation effect or the buffer effect can be more effectively implemented.

FIG. 11 schematically illustrates a step of forming the first insulating layer 550 covering the spacer 533 and the third insulating layer pattern 545.

In detail, the first insulating layer 550 covering the spacer 533 and the third insulating layer pattern 545 is thinly formed as described with reference to FIG. 6. That is, the first insulating layer 550 is formed to have a thickness or a film quality such that the gaseous phase generated by the conversion of the spacer 533 is transmitted or passed through the discharge. For example, a silicon oxide film formed by the CVD method, the bias sputtering method, or the like is used as the first insulating film 550.

FIG. 12 schematically illustrates a step of removing the spacer 533 to form a void 535.

Specifically, the void 535 is formed by performing an oxidation process on the resultant formed with the first insulating layer 550 as described with reference to FIG. 7. That is, a process capable of causing an oxidation reaction such as an oxygen annealing process, a wet oxidation process, or an oxygen plasma treatment process is performed. By the oxidation process, the carbon-containing material constituting the spacer 533 is oxidized and converted into a gaseous phase. That is, the amorphous carbon or organic polymer is oxidized and converted into a gaseous phase such as an oxide gas such as carbon dioxide (CO ₂ ) or the like. The gaseous phase passes through the first insulating film 550 or the third insulating film 545 by the gas pressure and is discharged to the outside. In this case, the transmittance of the gaseous phase is a function of a path through which the gaseous phase transmits through the first insulating layer 550 more than the amount emitted through the third insulating layer 545. Since the spacer 533 is vaporized and removed as described above, the space occupied by the spacer 533 is left as an empty space, that is, the void 535.

FIG. 13 schematically illustrates a step of forming a second insulating film 570 on the first insulating film 550.

Specifically, as described with reference to FIG. 8, a second insulating layer 570 is formed on the first insulating layer 550 to fill the trench 400. For example, the trench 400 is buried by depositing a silicon oxide film or the like using a CVD method. Next, the second insulating film 570 and the like are planarized to form an insulating film pattern 500 as shown in FIG. 2. That is, the insulating film made of the first insulating film 550, the second insulating film 570, the third insulating film pattern 545, and the like is planarized by the CMP method or the like.

Thereafter, as described with reference to FIG. 8, the densification of the second insulating layer 570 may be further performed. In addition, defects in the semiconductor substrate 100 forming the inner wall of the trench 400 may be prevented due to stress changes that may occur in the densification process or the process of forming the second insulating layer 270. Therefore, it is possible to suppress the occurrence of defects such as cracks or pits in the inner wall of the trench 400, particularly the semiconductor substrate 100 at the corners, thereby preventing the generation of junction leakage current when the semiconductor device is driven. .

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, an insulating film serving as an element isolation film for forming voids in the trench sidewall and the like may be formed by forming and removing a spacer made of an organic polymer containing carbon or amorphous carbon or the like on the sidewall of the trench. Accordingly, stress or the like, which may occur due to a difference in thermal expansion rate of the semiconductor substrate forming the inner wall of the insulating layer and the trench, may be alleviated or buffered. Therefore, defects such as cracks or pits that may occur in the sidewalls of the trenches, for example, the edges or corners of the trenches, may be suppressed by the stress or the like. Therefore, the junction leakage current and the like can be suppressed and the electrical characteristics of the semiconductor device can be improved.

Claims (18)

A semiconductor substrate having a trench; And And an insulating layer pattern forming voids on the sidewalls of the trench and filling the trench. The trench device isolation structure of claim 1, further comprising a diffusion barrier layer covering the inner wall of the trench with the insulating layer pattern and the lower layer of the void to prevent material movement to the semiconductor substrate. The trench isolation structure of claim 2, wherein the diffusion barrier is a silicon nitride film. Forming a trench in the semiconductor substrate; Forming a spacer with amorphous carbon or an organic polymer in the sidewall portion of the trench; Forming a first insulating layer covering the spacer; Removing the spacers to form voids in the sidewalls, the voids comprising a space between the sidewalls of the trench and the first insulating layer; And And forming a second insulating film filling the trench on the first insulating film. 5. The method of claim 4, prior to forming said spacers. Forming a diffusion barrier layer covering the inner wall of the trench to prevent material movement to the semiconductor substrate. 6. The method of claim 5, wherein the diffusion barrier is formed of a silicon nitride film. The method of claim 4, wherein forming the spacer Forming a spacer film covering an inner wall of the trench; And Patterning the spacer film by an anisotropic etching method to form a spacer remaining on sidewalls of the trench. The monomer of claim 4, wherein the organic polymer is represented by <Formula 5> A method for producing a trench device isolation structure for a semiconductor device, characterized in that it is any one selected from the group consisting of polymers, parylene, parylene fluoride, polyarylides, silks and fluorinated polyarylides. The method of claim 4, wherein the amorphous carbon is any one selected from the group consisting of amorphous hydrated carbon and amorphous fluorinated carbon. The method of claim 4, wherein removing the spacers And a step of oxidizing the amorphous carbon or the organic polymer by performing an oxidation process on the resultant in which the first insulating film is formed, and discharging the gaseous phase by the oxidation through the first insulating film. Device isolation structure manufacturing method. The method of claim 10, wherein the oxidation process A method for manufacturing a trench element isolation structure for a semiconductor device, characterized in that the step is any one selected from the group consisting of an oxygen annealing step, a wet oxidation step, and an oxygen plasma treatment step. The method of claim 4, after the forming of the second insulating layer And densifying the second insulating layer. Forming a trench in the semiconductor substrate; Forming a spacer film covering the sidewalls of the trench with organic polymer or amorphous carbon including carbon; Forming a third insulating film covering the spacer film; Patterning the third insulating layer and the spacer layer to form a third insulating layer pattern exposing the spacer and a portion of the spacer on a sidewall portion of the trench; Forming a first insulating layer covering the exposed spacers and the third insulating layer pattern; Removing the spacers to form voids on the sidewalls of the trench, the voids formed between the sidewalls of the trench and the third insulating layer pattern; And And forming a second insulating film filling the trench on the first insulating film. 15. The method of claim 13, prior to forming the spacer film. Forming a diffusion barrier layer covering the inner wall of the trench to prevent material movement to the semiconductor substrate. 15. The method of claim 14, wherein the diffusion barrier is formed of a silicon nitride film. The method of claim 13, wherein removing the spacers And a step of oxidizing the amorphous carbon or the organic polymer by performing an oxidation process on the resultant in which the first insulating film is formed, and discharging the gaseous phase by the oxidation through the first insulating film. Device isolation fabrication structure method. The method of claim 16, wherein the oxidation process A method for manufacturing a trench element isolation structure for a semiconductor device, characterized in that the step is any one selected from the group consisting of an oxygen annealing step, a wet oxidation step, and an oxygen plasma treatment step. The method of claim 13, after the forming of the second insulating film And densifying the second insulating layer.