JPH08213392A - Semiconductor element and its manufacture - Google Patents
Semiconductor element and its manufactureInfo
- Publication number
- JPH08213392A JPH08213392A JP7014831A JP1483195A JPH08213392A JP H08213392 A JPH08213392 A JP H08213392A JP 7014831 A JP7014831 A JP 7014831A JP 1483195 A JP1483195 A JP 1483195A JP H08213392 A JPH08213392 A JP H08213392A
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- forming
- film
- oxide film
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子及びその製
造方法に係り、特にその最終保護膜の構造及びその製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to the structure of its final protective film and its manufacturing method.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、以下に示すようなものがあった。図４はかかる
従来の半導体素子の断面図である。この図において、半
導体基板１０１上には絶縁膜１０２が形成され、この絶
縁膜１０２上に最上層の配線パターン１０３が形成され
た後に、最終保護膜１０５が生成されるのが一般的であ
る。2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there were the following. FIG. 4 is a sectional view of such a conventional semiconductor device. In this figure, an insulating film 102 is formed on a semiconductor substrate 101, and a final protective film 105 is generally formed after the wiring pattern 103 of the uppermost layer is formed on the insulating film 102.
【０００３】この最終保護膜１０５としては、耐水性に
優れたシリコン窒化膜が多く使われている。As the final protective film 105, a silicon nitride film excellent in water resistance is often used.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記し
た従来の最上層配線の場合、隣り合った配線間を考える
と、配線間にシリコン窒化膜１０５が存在する寄生容量
１０８が形成される。このシリコン窒化膜１０５は誘電
率が７．５と、シリコン酸化膜３．９に比較して大き
く、特に、最小スリット部ではこの寄生容量１０８によ
り伝送される信号の伝達スピードの低下を引き起こし、
タイミングがずれることにより、技術的に満足できるも
のが得られなかった。However, in the case of the conventional uppermost layer wiring described above, a parasitic capacitance 108 in which the silicon nitride film 105 exists between the wirings is formed considering the space between adjacent wirings. The silicon nitride film 105 has a dielectric constant of 7.5, which is larger than that of the silicon oxide film 3.9, and particularly, in the minimum slit portion, the transmission speed of the signal transmitted by the parasitic capacitance 108 is lowered,
Due to the deviation of the timing, we could not obtain a technically satisfactory product.
【０００５】つまり、シリコン窒化膜以外の材料を使用
した場合、十分な耐水性が得られず信頼性の低下をもた
らすという問題点があった。本発明は、上記問題点を除
去し、配線間のスリットがシリコン酸化膜ですべて被わ
れておらず、中に空洞部を形成することにより、配線間
のスリットにおける寄生容量の減少を図り得る半導体素
子及びその製造方法を提供することを目的とする。That is, when a material other than the silicon nitride film is used, there is a problem that sufficient water resistance cannot be obtained and reliability is lowered. The present invention eliminates the above-mentioned problems, and a slit between wirings is not entirely covered with a silicon oxide film, and a cavity is formed therein, so that a parasitic capacitance in the slit between wirings can be reduced. An object is to provide an element and a manufacturing method thereof.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 （１）請求項１記載の半導体素子において、最上層配線
２０３が逆台形状をしており、かつ、その最上層配線２
０３を被うシリコン酸化膜２０４により、空洞部２０７
が形成されるようにしたものである。In order to achieve the above object, the present invention provides: (1) In the semiconductor device according to claim 1, the uppermost layer wiring 203 has an inverted trapezoidal shape, and Upper layer wiring 2
The silicon oxide film 204 covering the cavity 03 forms the cavity 207.
Are formed.
【０００７】（２）請求項２記載の半導体素子の製造方
法において、半導体基板２０１上に絶縁膜２０２を形成
し、この絶縁膜２０２上に逆台形となるように最上層配
線２０３を形成する工程と、次いで、シリコン酸化膜２
０４を常圧ＣＶＤ法により形成する工程と、次に、シリ
コン酸化膜２０４を最小スリット部の上部において接触
させ、この最小スリット部に空洞部２０７を形成工程
と、次に、最終保護膜となるシリコン窒化膜２０５を形
成する工程とを施すようにしたものである。(2) In the method of manufacturing a semiconductor device according to claim 2, a step of forming an insulating film 202 on the semiconductor substrate 201 and forming an uppermost layer wiring 203 on the insulating film 202 so as to form an inverted trapezoid. And then the silicon oxide film 2
04 by the atmospheric pressure CVD method, the silicon oxide film 204 is then brought into contact with the upper portion of the minimum slit portion, and the cavity portion 207 is formed in this minimum slit portion, and then the final protective film is formed. The step of forming the silicon nitride film 205 is performed.
【０００８】（３）請求項３記載の半導体素子の製造方
法において、半導体基板２０１上に絶縁膜２０２を形成
し、この絶縁膜２０２上に逆台形となるように最上層配
線２０３を形成する工程と、次いで、シリコン酸化膜３
０１を減圧ＣＶＤ法により形成する工程と、次に、シリ
コン酸化膜３０１を最小スリット部の上部において接触
させ、この最小スリット部に空洞部３０２を形成工程
と、次に、最終保護膜となるシリコン窒化膜３０３を形
成する工程とを施すようにしたものである。(3) In the method of manufacturing a semiconductor device according to claim 3, a step of forming an insulating film 202 on the semiconductor substrate 201, and forming an uppermost layer wiring 203 on the insulating film 202 so as to form an inverted trapezoid. And then the silicon oxide film 3
01 by a low pressure CVD method, a silicon oxide film 301 is brought into contact with the upper portion of the minimum slit portion, and a cavity portion 302 is formed in the minimum slit portion, and then a silicon film to be a final protective film. The step of forming the nitride film 303 is performed.
【０００９】[0009]
【作用】本発明によれば、上記のように構成したので、 （１）配線間のスリットがシリコン酸化膜ですべて被わ
れておらず、中に空洞部が形成されるため、配線間のス
リットにおける寄生容量の減少を図ることができる。According to the present invention, since it is configured as described above, (1) the slits between the wirings are not covered with the silicon oxide film and a cavity is formed in the slits. It is possible to reduce the parasitic capacitance in.
【００１０】（２）シリコン酸化を常圧ＣＶＤ法で形成
しているため、逆台形部上面及び角での生成レートが大
きく膜厚が厚くなるため、スリット側壁及び底部での膜
厚を薄くすることができ、空洞部が大きくなるため寄生
容量を、更に低減することができる。 （３）シリコン酸化膜を減圧ＣＶＤ法で形成しているた
め、空洞部での余分なガスが少なく、より真空に近い状
態となり、その後の熱処理での膨張を抑えることができ
る。(2) Since the silicon oxide is formed by the atmospheric pressure CVD method, the film formation rate is large on the upper surface and the corners of the inverted trapezoidal portion, and the film thickness is increased. Therefore, the film thickness is reduced on the side wall and the bottom of the slit. Since the cavity is large, the parasitic capacitance can be further reduced. (3) Since the silicon oxide film is formed by the low pressure CVD method, the amount of extra gas in the cavity is small, the state becomes closer to a vacuum, and expansion in the subsequent heat treatment can be suppressed.
【００１１】[0011]
【実施例】本発明の実施例について図を参照しながら説
明する。図１は本発明の第１実施例を示す半導体素子の
断面図である。この図において、２０１は半導体基板、
２０２はその半導体基板２０１上に形成される絶縁膜、
２０３は最上層配線、２０４はシリコン酸化膜、２０５
はシリコン窒化膜、２０７は空洞部である。Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention. In this figure, 201 is a semiconductor substrate,
202 is an insulating film formed on the semiconductor substrate 201,
203 is the uppermost wiring, 204 is a silicon oxide film, 205
Is a silicon nitride film, and 207 is a cavity.
【００１２】この実施例では、最上層配線２０３は、逆
台形の形状をしており、かつ、スリットはすべてシリコ
ン酸化膜２０４で埋め込まれず、中に空洞部２０７が形
成されている。以下、本発明の第１実施例を示す半導体
素子の製造方法について説明する。図２は本発明の第１
実施例を示す半導体素子の製造工程断面図である。In this embodiment, the uppermost layer wiring 203 has an inverted trapezoidal shape, and all the slits are not filled with the silicon oxide film 204, and a hollow portion 207 is formed therein. Hereinafter, a method for manufacturing a semiconductor device showing the first embodiment of the present invention will be described. FIG. 2 shows the first of the present invention.
FIG. 7 is a sectional view of a semiconductor element in the manufacturing process showing the example.
【００１３】（１）まず、図２（ａ）に示すように、半
導体基板２０１上に絶縁膜２０２を形成し、この絶縁膜
２０２上に最上層配線２０３を形成する。この時、最上
層配線２０３を逆台形となるように形成する。 （２）次に、図２（ｂ）に示すように、シリコン酸化膜
２０４を常圧ＣＶＤ法により形成する。(1) First, as shown in FIG. 2A, an insulating film 202 is formed on a semiconductor substrate 201, and an uppermost layer wiring 203 is formed on the insulating film 202. At this time, the uppermost layer wiring 203 is formed so as to have an inverted trapezoidal shape. (2) Next, as shown in FIG. 2B, a silicon oxide film 204 is formed by an atmospheric pressure CVD method.
【００１４】（３）次いで、図２（ｃ）に示すように、
シリコン酸化膜２０４を最小スリット部の上部において
接触させる。 （４）この後は、反応ガスがスリット部へは入らないた
め、図２（ｄ）に示すように、スリット部に空洞部２０
７が形成される。 （５）しかる後に、図２（ｅ）に示すように、最終保護
膜となるシリコン窒化膜２０５をＣＶＤ法において形成
することにより、本発明の半導体素子を得ることができ
る。(3) Next, as shown in FIG.
The silicon oxide film 204 is brought into contact with the upper part of the minimum slit portion. (4) After that, since the reaction gas does not enter the slit portion, as shown in FIG. 2D, the hollow portion 20 is formed in the slit portion.
7 is formed. (5) Then, as shown in FIG. 2E, a silicon nitride film 205 to be a final protective film is formed by a CVD method, whereby the semiconductor element of the present invention can be obtained.
【００１５】次に、本発明の第２実施例を示す半導体素
子の製造方法について説明する。図３は本発明の第２実
施例を示す半導体素子の製造工程断面図である。 （１）まず、図３（ａ）に示すように、半導体基板２０
１上に絶縁膜２０２を形成し、この絶縁膜２０２上に最
上層配線２０３を形成する。この時、最上層配線２０３
を逆台形となるように形成する。Next, a method of manufacturing a semiconductor device showing the second embodiment of the present invention will be described. FIG. 3 is a sectional view of a semiconductor device manufacturing process showing a second embodiment of the present invention. (1) First, as shown in FIG.
The insulating film 202 is formed on the insulating film 202, and the uppermost wiring 203 is formed on the insulating film 202. At this time, the uppermost layer wiring 203
Is formed into an inverted trapezoid.
【００１６】（２）次に、図３（ｂ）に示すように、シ
リコン酸化膜３０１を減圧ＣＶＤ法により形成する。 （３）次いで、図３（ｃ）に示すように、シリコン酸化
膜３０１を最小スリット部の上部において接触させる。 （４）この後は、反応ガスがスリット部へは入らないた
め、図３（ｄ）に示すように、スリット部に空洞部３０
２が形成される。(2) Next, as shown in FIG. 3B, a silicon oxide film 301 is formed by a low pressure CVD method. (3) Next, as shown in FIG. 3C, the silicon oxide film 301 is brought into contact with the upper part of the minimum slit portion. (4) After that, since the reaction gas does not enter the slit portion, as shown in FIG. 3D, the cavity portion 30 is formed in the slit portion.
2 is formed.
【００１７】（５）しかる後に、図３（ｅ）に示すよう
に、最終保護膜となるシリコン窒化膜３０３をＣＶＤ法
において形成することにより、本発明の半導体素子を得
ることができる。 この実施例においては、シリコン酸化膜３０１を減圧Ｃ
ＶＤ法において、形成するようにしたので、減圧雰囲気
のため、常圧ＣＶＤ法での生成時と比較して、空洞部３
０２のガス圧力を小さくすることができる。(5) Then, as shown in FIG. 3 (e), the silicon nitride film 303 to be the final protective film is formed by the CVD method, whereby the semiconductor element of the present invention can be obtained. In this embodiment, the silicon oxide film 301 is reduced in pressure C
Since it is formed in the VD method, the cavity 3 is formed in a reduced pressure atmosphere, as compared with the time of generation in the atmospheric pressure CVD method.
The gas pressure of 02 can be reduced.
【００１８】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.
【００１９】[0019]
【発明の効果】以上、詳細に説明したように、 （１）請求項１記載の発明によれば、配線間のスリット
がシリコン酸化膜ですべて被われておらず、中に空洞部
が形成されるため、配線間のスリットにおける寄生容量
の減少を図ることができる。As described above in detail, (1) According to the invention described in claim 1, the slits between the wirings are not entirely covered with the silicon oxide film, and a cavity is formed therein. Therefore, the parasitic capacitance in the slit between the wirings can be reduced.
【００２０】（２）請求項２記載の発明によれば、シリ
コン酸化を常圧ＣＶＤ法で形成しているため、逆台形部
上面及び角での生成レートが大きく膜厚が厚くなるた
め、スリット側壁及び底部での膜厚を薄くすることがで
き、空洞部が大きくなるため寄生容量を更に低減するこ
とができる。 （３）請求項３記載の発明によれば、シリコン酸化膜を
減圧ＣＶＤ法で形成しているため、空洞部での余分なガ
スが少なく、より真空に近い状態となり、その後の熱処
理での膨張を抑えることができる。(2) According to the second aspect of the present invention, since the silicon oxide is formed by the atmospheric pressure CVD method, the production rate is large on the upper surface and the corners of the inverted trapezoidal portion, and the film thickness becomes large. Since the film thickness on the side wall and the bottom can be reduced and the cavity becomes large, the parasitic capacitance can be further reduced. (3) According to the invention as set forth in claim 3, since the silicon oxide film is formed by the low pressure CVD method, the amount of extra gas in the cavity is small and the state becomes closer to a vacuum and the expansion in the subsequent heat treatment. Can be suppressed.
【図１】本発明の第１実施例を示す半導体素子の断面図
である。FIG. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention.
【図２】本発明の第１実施例を示す半導体素子の製造工
程断面図である。FIG. 2 is a sectional view of a semiconductor device in the manufacturing process showing the first embodiment of the present invention.
【図３】本発明の第２実施例を示す半導体素子の製造工
程断面図である。FIG. 3 is a sectional view of a semiconductor device in the manufacturing process showing the second embodiment of the present invention.
【図４】従来の半導体素子の断面図である。FIG. 4 is a sectional view of a conventional semiconductor device.
２０１ 半導体基板 ２０２ 絶縁膜 ２０３ 最上層配線（逆台形） ２０４ シリコン酸化膜（常圧ＣＶＤ法） ２０５，３０３ シリコン窒化膜 ２０７ 空洞部（常圧） ３０１ シリコン酸化膜（減圧ＣＶＤ法） ３０２ 空洞部（ガス圧小） 201 Semiconductor Substrate 202 Insulating Film 203 Top Wiring (Inverted Trapezoid) 204 Silicon Oxide Film (Normal Pressure CVD Method) 205, 303 Silicon Nitride Film 207 Cavity (Normal Pressure) 301 Silicon Oxide Film (Low Pressure CVD Method) 302 Cavity ( (Small gas pressure)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/768 Ｈ０１Ｌ 21/90 Ｖ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 21/768 H01L 21/90 V
Claims (3)
つ、該最上層配線を被うシリコン酸化膜により空洞部が
形成されていることを特徴とする半導体素子。1. A semiconductor device, wherein the uppermost layer wiring has an inverted trapezoidal shape, and a cavity is formed by a silicon oxide film covering the uppermost layer wiring.
の絶縁膜上に逆台形となるように最上層配線を形成する
工程と、（ｂ）シリコン酸化膜を常圧ＣＶＤ法により形
成する工程と、（ｃ）シリコン酸化膜を最小スリット部
の上部において接触させ、該最小スリット部に空洞部を
形成工程と、（ｄ）最終保護膜となるシリコン窒化膜を
形成する工程とを順次施すことを特徴とする半導体素子
の製造方法。2. A step of (a) forming an insulating film on a semiconductor substrate and forming an uppermost layer wiring on the insulating film so as to form an inverted trapezoid, and (b) forming a silicon oxide film by an atmospheric pressure CVD method. A step of forming, a step of (c) bringing the silicon oxide film into contact with the upper portion of the minimum slit portion to form a cavity in the minimum slit portion, and (d) a step of forming a silicon nitride film to be a final protective film. A method for manufacturing a semiconductor device, which comprises sequentially performing the steps.
の絶縁膜上に逆台形となるように最上層配線を形成する
工程と、（ｂ）シリコン酸化膜を減圧ＣＶＤ法により形
成する工程と、（ｃ）シリコン酸化膜を最小スリット部
の上部において接触させ、該最小スリット部に空洞部を
形成工程と、（ｄ）最終保護膜となるシリコン窒化膜を
形成する工程とを順次施すことを特徴とする半導体素子
の製造方法。3. A step of (a) forming an insulating film on a semiconductor substrate and forming an uppermost layer wiring on the insulating film so as to form an inverted trapezoid, and (b) forming a silicon oxide film by a low pressure CVD method. Step, (c) contacting the silicon oxide film at the upper part of the minimum slit part to form a cavity in the minimum slit part, and (d) forming a silicon nitride film to be the final protective film in this order. A method of manufacturing a semiconductor element, which comprises applying the method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7014831A JPH08213392A (en) | 1995-02-01 | 1995-02-01 | Semiconductor element and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7014831A JPH08213392A (en) | 1995-02-01 | 1995-02-01 | Semiconductor element and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08213392A true JPH08213392A (en) | 1996-08-20 |
Family
ID=11871989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7014831A Pending JPH08213392A (en) | 1995-02-01 | 1995-02-01 | Semiconductor element and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08213392A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0978875A1 (en) * | 1998-08-07 | 2000-02-09 | STMicroelectronics S.r.l. | Integrated circuit comprising conductive lines with "negative" profile and related method of fabrication |
| US6242336B1 (en) | 1997-11-06 | 2001-06-05 | Matsushita Electronics Corporation | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
| WO2002054493A1 (en) * | 2000-12-28 | 2002-07-11 | Infineon Technologies North America Corp. | Conductive lines with reduced pitch |
| KR100355867B1 (en) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | a manufacturing method of a semiconductor device |
| JP2003521757A (en) * | 1999-04-19 | 2003-07-15 | シュラムバーガー システムズ | A device having an integrated circuit protected against attacks made by the controlled destruction of additional thin films. |
| KR100505608B1 (en) * | 1998-06-24 | 2005-09-26 | 삼성전자주식회사 | Trench isolation structure for semiconductor device & manufacturing method thereof |
| US6992394B2 (en) | 2000-12-28 | 2006-01-31 | Infineon Technologies Ag | Multi-level conductive lines with reduced pitch |
| JP2009503814A (en) * | 2005-07-19 | 2009-01-29 | マイクロン テクノロジー， インク． | Semiconductor structure, memory array, electronic system, and method for forming semiconductor structure |
| US7557029B2 (en) | 2002-11-15 | 2009-07-07 | Sharp Kabushiki Kaisha | Semiconductor device and fabrication process thereof |
| US7867890B2 (en) | 2006-10-27 | 2011-01-11 | Oki Semiconductor Co., Ltd. | Manufacturing method of semiconductor device and semiconductor device |
| US8598043B2 (en) | 2006-04-11 | 2013-12-03 | Micron Technology Inc. | Methods of forming semiconductor constructions |
| US8829643B2 (en) | 2005-09-01 | 2014-09-09 | Micron Technology, Inc. | Memory arrays |
-
1995
- 1995-02-01 JP JP7014831A patent/JPH08213392A/en active Pending
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6242336B1 (en) | 1997-11-06 | 2001-06-05 | Matsushita Electronics Corporation | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
| US6545361B2 (en) | 1997-11-06 | 2003-04-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
| KR100505608B1 (en) * | 1998-06-24 | 2005-09-26 | 삼성전자주식회사 | Trench isolation structure for semiconductor device & manufacturing method thereof |
| EP0978875A1 (en) * | 1998-08-07 | 2000-02-09 | STMicroelectronics S.r.l. | Integrated circuit comprising conductive lines with "negative" profile and related method of fabrication |
| JP2003521757A (en) * | 1999-04-19 | 2003-07-15 | シュラムバーガー システムズ | A device having an integrated circuit protected against attacks made by the controlled destruction of additional thin films. |
| KR100355867B1 (en) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | a manufacturing method of a semiconductor device |
| WO2002054493A1 (en) * | 2000-12-28 | 2002-07-11 | Infineon Technologies North America Corp. | Conductive lines with reduced pitch |
| US6992394B2 (en) | 2000-12-28 | 2006-01-31 | Infineon Technologies Ag | Multi-level conductive lines with reduced pitch |
| US7557029B2 (en) | 2002-11-15 | 2009-07-07 | Sharp Kabushiki Kaisha | Semiconductor device and fabrication process thereof |
| JP2009503814A (en) * | 2005-07-19 | 2009-01-29 | マイクロン テクノロジー， インク． | Semiconductor structure, memory array, electronic system, and method for forming semiconductor structure |
| US8829643B2 (en) | 2005-09-01 | 2014-09-09 | Micron Technology, Inc. | Memory arrays |
| US9559163B2 (en) | 2005-09-01 | 2017-01-31 | Micron Technology, Inc. | Memory arrays |
| US9929233B2 (en) | 2005-09-01 | 2018-03-27 | Micron Technology, Inc. | Memory arrays |
| US10622442B2 (en) | 2005-09-01 | 2020-04-14 | Micron Technology, Inc. | Electronic systems and methods of forming semiconductor constructions |
| US11171205B2 (en) | 2005-09-01 | 2021-11-09 | Micron Technology, Inc. | Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions |
| US11626481B2 (en) | 2005-09-01 | 2023-04-11 | Micron Technology, Inc. | Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions |
| US8598043B2 (en) | 2006-04-11 | 2013-12-03 | Micron Technology Inc. | Methods of forming semiconductor constructions |
| US7867890B2 (en) | 2006-10-27 | 2011-01-11 | Oki Semiconductor Co., Ltd. | Manufacturing method of semiconductor device and semiconductor device |
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