KR100355867B1 - a manufacturing method of a semiconductor device - Google Patents

a manufacturing method of a semiconductor device Download PDF

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KR100355867B1
KR100355867B1 KR1019990067739A KR19990067739A KR100355867B1 KR 100355867 B1 KR100355867 B1 KR 100355867B1 KR 1019990067739 A KR1019990067739 A KR 1019990067739A KR 19990067739 A KR19990067739 A KR 19990067739A KR 100355867 B1 KR100355867 B1 KR 100355867B1
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wiring
wirings
oxide film
insulating film
space
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KR1019990067739A
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KR20010066154A (en
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고한석
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아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

절연막 위에 다수의 배선을 형성하고, 이들을 덮는 산화막을 증착한다. 이때, 산화막 증착 시 플라스마 화학 기상 증착법을 이용하면 산화막이 배선을 따라 균일하게 증착되지 않고 배선의 모서리 부분에 돌출부의 형태로 증착된다. 이어, 산화막을 증착함과 동시에 식각하는 고밀도 플라스마 공정을 이용하여 배선 사이를 산화막으로 완전히 채우지 않고 배선의 높이보다 낮은 공백을 형성시킨다. 이렇게 하면, 배선 사이에 산화막이 완전히 채워져 이루는 정전 용량보다 작게 되어 신호의 지연을 줄일 수 있어 소자의 동작 속도를 개선할 수 있다. 공백의 높이를 배선보다 낮게 하여 이후 평탄화 공정에서 산화막의 손상을 방지할 수 있으며, 공백의 크기를 조절하여 유전율을 조절할 수 있다.A plurality of wirings are formed on the insulating film, and an oxide film covering them is deposited. At this time, when the plasma chemical vapor deposition method is used in the deposition of the oxide film, the oxide film is not deposited uniformly along the wiring, but is deposited in the form of a protrusion on the edge of the wiring. Subsequently, a high-density plasma process in which an oxide film is deposited and simultaneously etched is used to form a space lower than the height of the wiring without completely filling the wiring with oxide films. In this way, the capacitance is smaller than the capacitance formed by the oxide film being completely filled between the wirings, thereby reducing the signal delay and improving the operation speed of the device. Since the height of the space is lower than the wiring, the damage of the oxide layer may be prevented in the subsequent planarization process, and the dielectric constant may be controlled by adjusting the size of the space.

Description

반도체 소자의 제조 방법{a manufacturing method of a semiconductor device}A manufacturing method of a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device.

일반적으로 반도체 소자에는 n형 또는 p형의 기판 위에 채널, 소스, 드레인 영역 등의 불순물이 도핑되어 있는 활성(active) 영역이 형성되어 있으며, 그 위에는 각각의 영역 상부에 접촉 구멍(contact)을 가지는 절연막이 형성되어 있으며 절연막 위에는 접촉 구멍을 통하여 각각의 영역과 연결되는 배선이 형성되어 있다.In general, a semiconductor device is formed with an active region doped with impurities such as a channel, a source, and a drain region on an n-type or p-type substrate, and a contact hole is formed over each region. An insulating film is formed, and wirings connected to the respective regions are formed on the insulating film through contact holes.

여기서, 반도체 소자가 점점 집적화될수록 반도체 소자의 면적이 줄어들기 때문에 배선을 무한정 길게 형성하는 데는 한계가 있다. 따라서, 이를 해결하기 위해서는 배선 층간에 절연막을 형성하고 절연막에 뚫린 접촉 구멍(via)을 통해 배선을 서로 연결하는 다층 배선을 형성하는 것이 효과적이다.Here, there is a limit to forming the wiring indefinitely because the area of the semiconductor element is reduced as the semiconductor element is gradually integrated. Therefore, in order to solve this problem, it is effective to form an insulating film between the wiring layers and to form a multilayer wiring connecting the wirings to each other through contact holes (vias) formed in the insulating film.

여기서, 하나의 층간 절연막 위에는 각각의 영역과 연결되어 있는 다수의 배선이 형성되어 있으며, 반도체 소자가 점점 집적화될수록 다수의 배선들 사이의 간격이 좁아지게 되어 배선 사이에 채워져 있는 절연막을 사이에 두고 이루어지는 기생 정전 용량이 커지게 된다. 이로 인해 배선을 따라 흐르는 신호의 지연이 생기게 되어 소자의 동작 속도가 느려지게 된다.Here, a plurality of wirings connected to respective regions are formed on one interlayer insulating film, and as semiconductor devices are increasingly integrated, a gap between the plurality of wirings is narrowed so that an insulating film filled between the wirings is interposed therebetween. The parasitic capacitance becomes large. This causes a delay of the signal flowing along the wiring, which slows down the operation speed of the device.

본 발명이 이루고자 하는 기술적 과제는 배선 사이의 기생 정전 용량을 줄이는 것이다.The technical problem to be achieved by the present invention is to reduce the parasitic capacitance between the wiring.

도 1 내지 도 4는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention according to a process sequence thereof.

이러한 과제를 달성하기 위하여 본 발명에서는 배선 사이를 산화막으로 채우되, 산화막 내에 배선의 높이보다 낮게 공백을 형성한다.In order to achieve the above object, in the present invention, the wiring is filled with an oxide film, and a gap is formed in the oxide film below the height of the wiring.

본 발명에 따르면, 제1 절연막 위에 다수의 배선을 형성하고 다수의 배선을 덮는 제2 절연막을 형성한다. 이어, 제2 절연막 위에 배선 사이에 공백을 갖는 제3 절연막을 형성하며 공백은 배선의 높이보다 낮은 것이 바람직하다.According to the present invention, a plurality of wirings are formed on the first insulating film and a second insulating film covering the plurality of wirings is formed. Next, a third insulating film having a space between the wirings is formed on the second insulating film, and the space is preferably lower than the height of the wiring.

이러한 반도체 소자를 제조할 때 제2 절연막은 PECVD법으로 형성되며 배선의 위쪽 모서리 부분에 돌출부를 가질 수 있다.In manufacturing such a semiconductor device, the second insulating film is formed by PECVD and may have a protrusion at an upper edge portion of the wiring.

제3 절연막을 형성하는 단계에서는 증착 및 식각을 동시에 실시하는 고밀도 플라스마 공정을 이용하고, 사용하는 기체는 사일렌 기체와 산소 기체, 아르곤 기체를 사용할 수도 있다.In the step of forming the third insulating film, a high density plasma process for simultaneously performing deposition and etching may be used, and the gas used may include xylene gas, oxygen gas, and argon gas.

이러한 본 발명의 제조 방법에서는 배선 사이에 산화막과 공백을 형성하여 이때 이루어지는 용량의 크기를 작게 하여 신호의 지연을 줄이며, 공백의 높이를배선보다 낮게 하여 이후 평탄화 공정에서 산화막이 손상되는 것을 방지할 수 있다.In the manufacturing method of the present invention, by forming an oxide film and a space between the wirings, the size of the capacitance formed at this time is reduced to reduce the signal delay, and the height of the space is lower than the wiring to prevent the oxide film from being damaged in the subsequent planarization process. have.

그러면, 첨부한 도면을 참조하여 본 발명의 실시예에 따른 반도체 소자의 제조 방법에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있을 정도로 상세히 설명한다.Next, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same.

도 1 내지 도 4를 참조하여 본 발명의 실시예에 따른 반도체 소자의 제조 방법에 대하여 상세히 설명한다.A method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4.

먼저, 도 1에서와 같이 절연막(1) 위에 배선용 도전체 또는 금속을 스퍼터링(sputtering) 따위의 방법을 써서 증착한 후 패터닝하여 다수의 배선(2)을 형성한다.First, as shown in FIG. 1, a wiring conductor or a metal is deposited on the insulating film 1 by a method such as sputtering, and then patterned to form a plurality of wirings 2.

이어, 도 2에서와 같이 배선(2) 위에 TEOS(tetraethoxysilane) 혹은 사일렌(SiH4) 기체 따위를 이용하여 플라스마 화학 기상 증착법(PECVD; plasma enhanced chemical vapor deposition) 따위의 방법을 써서 제1 산화막(3)을 증착한다. 이때, 제1 산화막(3)은 배선(2)을 따라 균일하게 증착되지 않고 배선(2)의 위쪽 모서리 부분에는 돌출부(4)의 형태로 증착되는데, 돌출부(4)의 크기나 모양은 공정 조건에 따라 달리할 수 있다.Next, as shown in FIG. 2, a plasma enhanced chemical vapor deposition (PECVD) method using a tetraethoxysilane (TEOS) or a silica (SiH 4 ) gas on the wiring 2 is used to form a first oxide film (PECVD). 3) deposit. At this time, the first oxide film 3 is not uniformly deposited along the wiring 2, but is deposited in the form of a protrusion 4 at the upper edge portion of the wiring 2, and the size or shape of the protrusion 4 is a process condition. It can vary depending on.

이어, 도 3에서와 같이 사일렌 기체와 산소 기체(O2), 아르곤 기체(Ar) 등의 기체를 반응실에 주입한 후 고밀도 플라스마(HDP; high density plasma) 공정을 이용하여 제2 산화막(13)을 증착함과 동시에 식각하여 배선(2) 사이에 제2산화막(13)을 완전히 채우지 않고 공백(5)을 형성한다. 이에 대해서 자세히 살펴보면 다음과 같다. 기체를 주입한 후 LF RF(low frequency RF) 전원을 공급하여 플라스마를 발생시키고 사일렌 기체와 산소 기체의 반응에 의한 제2 산화막(13)을 증착하며, 동시에 HF RF(high frequency RF) 전원을 공급하여 이온화된 아르곤 기체가 제2 산화막(13)을 떼내도록 한다. 이때, 제2 산화막(13)의 증착이 아르곤 기체에 의한 제2 산화막(13)의 식각보다 더 잘 일어나게 하여 공백(5)을 배선(2)의 높이보다 낮게 형성한다.Subsequently, as shown in FIG. 3, gases such as xylene gas, oxygen gas (O 2 ), argon gas (Ar), and the like are injected into the reaction chamber, and then a second oxide film (HDP) is performed using a high density plasma (HDP) process. 13 is deposited and simultaneously etched to form a space 5 between the wirings 2 without completely filling the second oxide film 13. The details are as follows. After injecting the gas, LF RF (low frequency RF) power is supplied to generate plasma, and the second oxide film 13 is deposited by the reaction of the xylene gas and oxygen gas, and at the same time, HF RF (high frequency RF) power is supplied. The supplying ionized argon gas separates the second oxide film 13. At this time, the deposition of the second oxide film 13 occurs better than the etching of the second oxide film 13 by argon gas, so that the voids 5 are formed lower than the height of the wiring 2.

이와 같은 공정을 통해 도 2에서와 같이 배선(2) 사이에는 산화막(3, 13)이 완전히 채워지지 않고 공백(5)이 형성되며, 배선(2) 사이에 산화막(3, 13)만으로 채워진 경우에 비해 기생 정전 용량은 줄어든다.In this process, as shown in FIG. 2, when the oxide films 3 and 13 are not completely filled between the wirings 2, a blank 5 is formed, and only the oxide films 3 and 13 are filled between the wirings 2. In comparison, parasitic capacitance is reduced.

따라서, 기생 정전 용량이 줄어들기 때문에 신호의 지연을 줄일 수 있으며 소자의 동작 속도가 줄어드는 것을 방지할 수 있다.Therefore, the parasitic capacitance is reduced, so that the delay of the signal can be reduced and the operation speed of the device can be prevented from decreasing.

그리고, 제1 산화막(3)의 두께를 조절하거나 고밀도 플라스마 공정에서 증착과 식각의 비율을 조절함으로써 공백(5)의 크기를 조절할 수 있으므로 배선(2) 간의 유전율을 조절할 수 있다. 또한 공백(5)의 높이를 조절할 수 있는데, 공백(5)의 높이를 배선(2)의 높이보다 낮게 형성하여 이후 공정인 평탄화 공정에서 가해지는 압력에 의해 공백(5) 위의 산화막(3, 13)이 깨져 공백(5)이 노출되거나 손상되는 것을 방지할 수 있다.In addition, since the size of the space 5 may be adjusted by controlling the thickness of the first oxide layer 3 or by controlling the ratio of deposition and etching in the high density plasma process, the dielectric constant between the wirings 2 may be controlled. In addition, the height of the space 5 may be adjusted. The height of the space 5 may be lower than the height of the wiring 2 so that the oxide film 3 on the space 5 may be affected by the pressure applied in the subsequent planarization process. 13) can be broken to prevent the void 5 from being exposed or damaged.

이와 같이 본 발명에서는 배선 사이에 산화막으로 완전히 채우지 않고 공백을 형성함으로써 기생 용량을 줄여 소자의 동작 속도를 개선할 수 있으며, 공백의 크기를 조절하여 유전율을 조절할 수 있으며 높이를 배선보다 낮게 하여 이후 평탄화 공정에서 산화막의 손상을 방지할 수 있다.As described above, in the present invention, a gap is formed between the wirings without filling the oxide film to reduce the parasitic capacitance, thereby improving the operation speed of the device, and controlling the dielectric constant by adjusting the size of the gap, and making the height lower than the wiring, thereby flattening. Damage to the oxide film can be prevented in the process.

Claims (5)

(정정) 배선 사이에 공백을 포함하는 반도체 소자의 제조방법에 있어서,In the semiconductor device manufacturing method including a space between wirings, 제1절연막 위에 다수의 배선을 형성하는 단계와,Forming a plurality of wirings on the first insulating film; PECVD법으로 상기 배선의 위쪽 모서리 부분에 돌출부가 위치하도록 상기 다수의 배선을 덮는 절연막을 형성하는 단계,Forming an insulating film covering the plurality of wirings such that the protrusions are positioned at the upper corners of the wirings by PECVD; 증착 및 식각을 동시에 실시하는 고밀도 플라스마 공정을 이용하여 상기 제2절연막 위에 상기 배선 사이에 공백을 갖는 제3절연막을 형성하는 단계,Forming a third insulating film having a space between the wirings on the second insulating film by using a high density plasma process for simultaneously performing deposition and etching; 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에서,In claim 1, 상기 공백은 상기 배선의 높이보다 낮은 반도체 소자의 제조 방법.And said void is lower than a height of said wiring. (삭제)(delete) (삭제)(delete) 제1항에서,In claim 1, 상기 제3 절연막 형성 단계에서 사용하는 기체는 사일렌 기체와 산소 기체, 아르곤 기체를 사용하는 반도체 소자의 제조 방법.The gas used in the third insulating film forming step is a method of manufacturing a semiconductor device using a xylene gas, oxygen gas, argon gas.
KR1019990067739A 1999-12-31 1999-12-31 a manufacturing method of a semiconductor device KR100355867B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03237721A (en) * 1990-02-15 1991-10-23 Fujitsu Ltd Method of flattening multilayer wiring
JPH08213392A (en) * 1995-02-01 1996-08-20 Oki Electric Ind Co Ltd Semiconductor element and its manufacture
JPH09172079A (en) * 1995-12-20 1997-06-30 Nec Corp Semiconductor device and its manufacture
KR19990062465A (en) * 1997-12-31 1999-07-26 구본준 Wiring structure and method of forming semiconductor device
KR20000040316A (en) * 1998-12-17 2000-07-05 윤종용 Manufacturing method of protective film in semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03237721A (en) * 1990-02-15 1991-10-23 Fujitsu Ltd Method of flattening multilayer wiring
JPH08213392A (en) * 1995-02-01 1996-08-20 Oki Electric Ind Co Ltd Semiconductor element and its manufacture
JPH09172079A (en) * 1995-12-20 1997-06-30 Nec Corp Semiconductor device and its manufacture
KR19990062465A (en) * 1997-12-31 1999-07-26 구본준 Wiring structure and method of forming semiconductor device
KR20000040316A (en) * 1998-12-17 2000-07-05 윤종용 Manufacturing method of protective film in semiconductor device

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