JPH03237721A - Method of flattening multilayer wiring - Google Patents
Method of flattening multilayer wiringInfo
- Publication number
- JPH03237721A JPH03237721A JP3436590A JP3436590A JPH03237721A JP H03237721 A JPH03237721 A JP H03237721A JP 3436590 A JP3436590 A JP 3436590A JP 3436590 A JP3436590 A JP 3436590A JP H03237721 A JPH03237721 A JP H03237721A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- insulating film
- layer
- cvd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052782 aluminium Inorganic materials 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 26
- 239000011800 void material Substances 0.000 abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000005012 migration Effects 0.000 abstract description 2
- 238000013508 migration Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009331 sowing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は、半導体装置の製造方法、特に、集積回路素子
のアルミニウム多層配線形成プロセスにに関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a process for forming an aluminum multilayer wiring for an integrated circuit element.
アルミニウム配線間の凹部を覆う層間絶縁膜の平坦化を
目的とし。The purpose is to flatten the interlayer insulating film that covers the recesses between aluminum wiring lines.
■アルミニウム配線膜間の凹部を覆って形成する層間絶
縁膜を、該凹部の両側から成長する層間絶縁膜の端部が
接触して、該層間絶縁膜の表面が平坦化する厚さまで成
長するように。■The interlayer insulating film to be formed to cover the recess between the aluminum wiring films is grown to a thickness such that the ends of the interlayer insulating film grown from both sides of the recess come into contact and the surface of the interlayer insulating film is flattened. To.
■アルミニウム配線膜間の凹部を覆って、該アルミニウ
ム配線膜上にＳＯＧ膜を被覆し、該凹部上にレジスト膜
のパターンを形成し、該レジスト膜をマスクとして９等
方性エツチングにより、該アルミニウム配線膜上のＳＯ
Ｇ膜を工・ソチング除去して、該凹部内のみに該ＳＯＧ
膜を平坦に残すように構成する。(2) Covering the recesses between the aluminum wiring films, coat the aluminum wiring film with an SOG film, form a resist film pattern on the recesses, and use the resist film as a mask to perform 9 isotropic etching to remove the aluminum. SO on wiring film
The G film is removed by machining and sowing, and the SOG is applied only inside the recess.
The membrane is configured to remain flat.
本発明は、半導体装置の製造方法、特に、集積回路素子
のアルミニウム多層配線形成プロセスに関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a process for forming an aluminum multilayer interconnection for an integrated circuit element.
近年、多層配線の平坦化はパターン形成上、その細配線
の断線防止上から、その技術的な改善の要求がますます
高まっている。In recent years, there has been an increasing demand for technical improvements in flattening multilayer interconnects in terms of pattern formation and prevention of disconnection of thin interconnects.
そのため、多層配線の平坦化に対する種々の方法が提案
されている。Therefore, various methods have been proposed for planarizing multilayer wiring.
第４図は従来例の説明図である。 FIG. 4 is an explanatory diagram of a conventional example.
図において、２３は下地Ｓｉｎ、膜、２４は第１層のＡ
／配線膜、 ２５ハ凹部、２６は第１ ノＣＶＤ−３ｉ
Ｏｔ膜。In the figure, 23 is the underlying Sin film, and 24 is the first layer A.
/wiring film, 25 is a recess, 26 is the first CVD-3i
Ot film.
２７はＳＯＧ膜、２８は第２ ノＣＶＤ−３ｉＯｔ膜、
２９ハ第２層のＡｌ配線膜である。27 is a SOG film, 28 is a second CVD-3iOt film,
29C is the second layer Al wiring film.
通常、従来のアルミニウム（ＡＩ）等の多層配線の平坦
化には、第４図に示すような方法が採られてきた。Conventionally, a method as shown in FIG. 4 has been adopted for planarizing multilayer wiring made of aluminum (AI) or the like.
先ず、半導体基板の下地ＳｉＯ□膜２３の表面上に配設
された第１層のＡｊ７配線膜２４上の全面に第１のＣＣ
ＶＤ−３ｔｏ膜２６を被覆し、ソノあと、 Ａｌ配線
膜２４の間の凹部２５を覆って、半導体基板全面に、シ
リコン（Ｓｉ）の有機物からなるＳＯＧ膜２７を塗布し
、ベーキングしてＳｉ絶縁膜となし、ついで反応性イオ
ンエツチング（ＲＩＥ）によりＳＯＧ膜２７全面をエツ
チングして、第１層のＡｌ配線膜２４の凹部２５の側壁
にのみＳＯＧ膜２７が残るようにして、側壁の勾配。First, a first CC is applied over the entire surface of the first layer Aj7 wiring film 24 disposed on the surface of the underlying SiO□ film 23 of the semiconductor substrate.
After coating the VD-3TO film 26, an SOG film 27 made of an organic material of silicon (Si) is applied to the entire surface of the semiconductor substrate, covering the recesses 25 between the Al wiring films 24, and baked to form an Si insulator. Then, the entire surface of the SOG film 27 is etched by reactive ion etching (RIE) so that the SOG film 27 remains only on the side walls of the recesses 25 of the first layer Al wiring film 24, thereby forming a slope of the side walls.
即ちステップの角度を和らげた後、その上に第２（７）
ＣＶＤ−３ｉＯａ膜２８を形成し、ソノ上に第２層（７
） Ａｌ配線膜２９を形成する方法が採られてきた。That is, after softening the angle of the step, the second (7)
A CVD-3iOa film 28 is formed, and a second layer (7
) A method of forming an Al wiring film 29 has been adopted.
しかし、この方法によると、第１層のＡＩ！配線膜２４
の隙間の間隔が１．５μｍ以下と微細に形成された場合
には、凹部２５内に第２のＣＶＤ−３ｔｏ２膜？８が落
ち込んで、その表面に大きな段差が生じて、第２層目の
ＡＩ！配線のステップカバレッジが悪くなる傾向にあっ
た。However, according to this method, the first layer AI! Wiring film 24
When the gap is formed finely with a gap of 1.5 μm or less, the second CVD-3to2 film is formed in the recess 25. 8 fell down, a large step appeared on the surface, and the second layer AI! The step coverage of wiring tended to deteriorate.
このように、第１層目のＡｊ７配線膜とＡｌ配線膜との
スペース間隔か１．５μｍ以下であると、第２層目のＡ
Ｉ配線のステップカバレッジが悪くなる。In this way, if the space interval between the Aj7 wiring film of the first layer and the Al wiring film is 1.5 μm or less, the Aj7 wiring film of the second layer
The step coverage of I wiring deteriorates.
本発明はこの問題を解決する手段を提供することにある
。The purpose of the present invention is to provide a means to solve this problem.
第１図は本発明の原理説明図である。 FIG. 1 is a diagram explaining the principle of the present invention.
図において、ｌは下地絶縁膜、２はＡｌ配線膜。In the figure, l is a base insulating film, and 2 is an Al wiring film.
３は凹部、４は層間絶縁膜、５はボイド、６はＳＯＧ膜
、７はレジスト膜である。3 is a recess, 4 is an interlayer insulating film, 5 is a void, 6 is an SOG film, and 7 is a resist film.
上記の問題点は９本発明の手段により層間絶縁膜の平坦
化を達成するものである。The above-mentioned problems are solved by the means of the present invention, which achieves planarization of the interlayer insulating film.
まず、第１の方法は、第１図（ａ）に示すように、
Ａｌ配線膜２上にＣＶＤ法により層間絶縁膜４を形成す
るが１層間絶縁膜４．特に、常圧で形成したＣＶＤの層
間絶縁膜４は、凹部３では角の部分のみ厚くなり、側面
や底面にはあまり絶縁膜が付かない。First, the first method is as shown in Figure 1(a),
An interlayer insulating film 4 is formed on the Al wiring film 2 by the CVD method, but one interlayer insulating film 4. In particular, the interlayer insulating film 4 formed by CVD under normal pressure is thick only at the corners of the recess 3, and the insulating film is not much attached to the side and bottom surfaces.
このままでは、上層のＡｆ配線を形成した場合にステッ
プカバレッジが悪くなり、断線の恐れがある。If this continues, step coverage will deteriorate when upper-layer Af wiring is formed, and there is a risk of disconnection.
そこで、 ＣＶＤによる層間絶縁膜４をその上に更なる
。この場合、眉間絶縁膜４の内部にボイド５と称する空
隙ができるが、 ＡＩ！配線膜２に接する程大きくな
ければ、絶縁に影響はない。Therefore, an interlayer insulating film 4 is further formed thereon by CVD. In this case, a void called a void 5 is created inside the glabellar insulating film 4, but AI! If it is not so large that it comes into contact with the wiring film 2, it will not affect the insulation.
上記のようにすると、Ａ／配線膜２の間の凹部３が層間
絶縁膜４により平坦化し、その上に形成する上層のＡｌ
配線膜のカバレッジが良くなる。By doing the above, the recess 3 between the A/wiring film 2 is flattened by the interlayer insulating film 4, and the upper layer Al formed thereon is flattened by the interlayer insulating film 4.
The coverage of the wiring film is improved.
また、第２の方法は、第１図（ｂ）に示すように、Ａ１
配線間の凹部にレジストパターンを形成して９等方性エ
ツチングを行い、 Ａｉ７配線膜上のＳＯＧ膜を除去
する。その際９等方性エツチングであるため、レジスト
下の端部でのＳＯＧ膜の突起が生じなくなり、 Ａｌ
配線膜とＳＯＧ膜の面が平坦化して、その上に成長する
層間絶縁膜の平坦化が達成できる。In addition, the second method is as shown in FIG. 1(b).
A resist pattern is formed in the recesses between the wirings, and 9 isotropic etching is performed to remove the SOG film on the Ai7 wiring film. At this time, since it is an isotropic etching, protrusions of the SOG film do not occur at the edges under the resist, and the Al
The surfaces of the wiring film and the SOG film are flattened, and the interlayer insulating film grown thereon can be flattened.
〔作用〕
このようにすると、第１の方法では、 ＣＶＤ絶縁膜の
厚い被覆により、絶縁膜がボイドを内包して平坦化し、
多層配線の平坦化が達成できる。[Function] In this way, in the first method, the thick coating of the CVD insulating film causes the insulating film to contain voids and become flat.
Planarization of multilayer wiring can be achieved.
また、第２の方法では、 Ａｆ配線間の凹部に。In addition, in the second method, in the recess between Af wiring.
確実にＳＯＧ膜が埋まり、しかも等方性エツチングを採
用しているため、 ＡＩ！配線の端でＳＯＧ膜が盛り
上がる心配がなく、平坦化が達成できる。Since the SOG film is reliably filled and isotropic etching is used, AI! There is no need to worry about the SOG film rising at the ends of the wiring, and flattening can be achieved.
第２図は本発明の第１の実施例の工程順模式断面図、第
３図は本発明の第２の実施例の工程順模式断面図である
。FIG. 2 is a schematic cross-sectional view of the first embodiment of the present invention in the order of steps, and FIG. 3 is a schematic cross-sectional view of the second embodiment of the present invention in the order of steps.
図において。In fig.
８は下地ＳｉＯ□膜、９は第１層のＡｆ配線膜、１０は
凹部、 １１は第１ （７）ＣＶＤ−３ｉＯｚ膜、 １
２は第２ ＜７）ＣＩ／Ｄ−３ｉＯｚ膜、 １３はボイ
ド、 １４は第２層のＡ１配線膜。8 is the base SiO□ film, 9 is the first layer Af wiring film, 10 is the recess, 11 is the first (7) CVD-3iOz film, 1
2 is a second <7) CI/D-3iOz film, 13 is a void, and 14 is a second layer A1 wiring film.
１５は下地５ｉＯｚ膜、 １６は第を層のＡｆ配線膜、
１７は凹部、 １８は第１ （７）ＣＶＤ−３ｉＯｚ
膜、 １９ハＳＯＧ膜、２０ハレジスト膜、 ２１は第
２のＣＶＤ−３ｉＯ□膜、２２は第２層のＡｆ配線膜で
ある。15 is the base 5iOz film, 16 is the second layer Af wiring film,
17 is the concave portion, 18 is the first (7) CVD-3iOz
19 is a SOG film, 20 is a resist film, 21 is a second CVD-3iO□ film, and 22 is a second layer Af wiring film.
本発明の第１の実施例を、第２図の工程順模式断面図に
より説明する。A first embodiment of the present invention will be described with reference to the schematic cross-sectional views in the order of steps shown in FIG.
第２図（ａ）に示すように、まず、半導体基板の下地５
ｉＯｚ膜８上にパタニングされた１μｍの厚さの第１層
のＡｊ７配線膜９上にＣＶＤ法により第１のＣＶＤ−３
ｉｆｔ膜１１を１，０ＯＯＡの厚さに被覆する。As shown in FIG. 2(a), first, the base 5 of the semiconductor substrate is
A first CVD-3 is deposited by CVD on the first layer Aj7 wiring film 9 with a thickness of 1 μm patterned on the iOz film 8.
Ift film 11 is coated to a thickness of 1,000A.
この場合、 ５ｉＯｚ膜の厚さが薄いので、 Ａｆ配
線膜９の間の凹部ＩＯを含めて、均一にＳｉｎ、膜が被
覆される。In this case, since the thickness of the 5iOz film is thin, the Sin film is uniformly coated, including the recesses IO between the Af wiring films 9.
その上に、第２のＣＶＤ−３ｉｆｔ膜１２を被覆してい
くが、その厚さが５．００ＯＡを越すと、第２図（ａ）
に示すように、 ＡＩ！配線膜９の角部に集中的にＳ
ｉＯ□膜が形成され、凹部１０内の側面や底面には薄く
しか堆積しない。A second CVD-3ift film 12 is coated on top of it, and when the thickness exceeds 5.00OA, as shown in Fig. 2(a).
As shown in AI! S is concentrated on the corners of the wiring film 9.
An iO□ film is formed and is deposited only thinly on the side surfaces and bottom surface of the recess 10.
ここで、更に、 ＣＣＶＤ−５ｔｏ膜を成長していくと
。Here, we will further grow a CCVD-5to film.
第２図（ｂ）４こ示すように、 ７．００ＯＡを超えて
。As shown in Figure 2(b) 4, it exceeds 7.00OA.
Ａｊ２配線膜９の角部上の５ｉｎ２膜が両方からお互い
に接触して内部にボイド１３を内包した状態になる。The 5in2 films on the corners of the Aj2 wiring film 9 come into contact with each other from both sides, resulting in a state in which voids 13 are included inside.
この時、第２のＣＶＤ−３ｉＯ□膜の表面は殆ど平坦な
形になっている。At this time, the surface of the second CVD-3iO□ film is almost flat.
第２図（Ｃ）に示すように、この平坦な第２のＣＶＤ−
３ｉｆｔ膜の上にＡｌ膜をスパッタニより７．０００人
の厚さに被覆し、パタニングして第２層のＡｊ７配線膜
１４を形成する。As shown in FIG. 2(C), this flat second CVD-
An Al film is coated on the 3ift film to a thickness of 7,000 mm by sputtering, and patterned to form a second layer Aj7 wiring film 14.
第２の実施例を、第３図の工程順模式断面図により説明
する。The second embodiment will be explained with reference to the schematic sectional views in the order of steps shown in FIG. 3.
第３図（ａ）に示すように、半導体基板の下地ＳｉＯ□
膜１５上にパタニングされた１μｍの厚さの第１層のＡ
ｌ配線膜１６上にＣＶＤ法により第１のＣＶＤ−３ｉＯ
ｚ膜１８を１．０００人の厚さに被覆する。As shown in FIG. 3(a), the underlying layer of the semiconductor substrate is SiO□.
A 1 μm thick first layer patterned on the film 15
A first CVD-3iO film is deposited on the l wiring film 16 by the CVD method.
Coat the z-film 18 to a thickness of 1.000 mm.
この場合、 Ｓｉ０ｇ膜の厚さが薄いので、 Ａｆ配
線膜Ｉ６の間の凹部１７を含めて、均一に５ｉ０２膜が
被覆される。In this case, since the Si0g film is thin, the 5i02 film is evenly coated, including the recesses 17 between the Af wiring films I6.
その上に、スピナーによりＳＯＧ膜１９を基板全面に５
．０ＯＯＡの厚さに被覆する。塗布されたＳＯＧ膜１９
は凹部１７内を完全に埋めつ＜Ｌ、ＡＩ！配線膜１６上
に比して僅かに低く被覆される。塗布したＳＯＧ膜は４
５０℃で３０分間、空気中でベーキングして。On top of that, a spinner is used to coat the entire surface of the substrate with an SOG film 19.
．． Coat to a thickness of 0OOA. Coated SOG film 19
completely fills the inside of the recess 17 <L, AI! The coating is slightly lower than that on the wiring film 16. The applied SOG film was 4
Bake in air at 50°C for 30 minutes.
Ｓｉｎ、膜にする。Sin, make it into a film.
続いて、第３図（ｂ）に示すように、レジストを塗布し
、パタニングして、凹部上のみレジスト膜２０のマスク
パターンを形成する。Subsequently, as shown in FIG. 3(b), a resist is applied and patterned to form a mask pattern of the resist film 20 only on the recessed portions.
第３図（Ｃ）に示すように、レジスト膜２０をマスクと
して、ウェットエツチング等の等方性エッングにより、
Ａｌ配線膜１６上のＳＯＧ膜をエツチング除去する。As shown in FIG. 3(C), by isotropic etching such as wet etching using the resist film 20 as a mask,
The SOG film on the Al wiring film 16 is removed by etching.
この時９等方性エツチングであるため、レジスト膜２０
の下の端部で、 ＳＯＧ膜１９が多少エツチングされ
て、 ＳＯＧ膜Ｉ９の端の突起が生じなくなって。At this time, since the etching is isotropic, the resist film 20
At the lower end of the SOG film 19, the SOG film 19 is etched to some extent, and the protrusion at the end of the SOG film I9 no longer appears.
ＡＩ配線膜１６とＳＯＧ膜１９の面が水平面上に並んで
平坦化する。The surfaces of the AI wiring film 16 and the SOG film 19 are aligned on a horizontal plane and are flattened.
このため、第３図（ｄ）に示すように、この上に第２
（７）ＣＶＤ−３ｉＯｔ膜２１を７．００ＯＡ（７）厚
すニ平坦状に形成することができる。Therefore, as shown in FIG. 3(d), a second
(7) The CVD-3iOt film 21 can be formed in a flat shape with a thickness of 7.00 OA (7).
更に、第３図（ｅ）に示すように、第２のＣＶＤ−３ｉ
Ｏ□膜２１の上にスパッタによりＡｌ膜を７，０ＯＯＡ
の厚さに被覆し、パタニングして第２層のＡＩ配線膜２
２を形成する。Furthermore, as shown in FIG. 3(e), a second CVD-3i
An Al film of 7,0OOA is formed on the O□ film 21 by sputtering.
The second layer of AI wiring film 2 is coated with a thickness of
form 2.
以上説明したように９本発明によれば、多層配線のＡＩ
！配線とＡｊ７配線の間隔が１．５μｍ以下になっても
、多層配線上の絶縁膜の平坦化が容易にでき、断線防止
、パターンの微細形成、マイグレーションの防止ができ
、従って、多層配線の形成及び信頼性の向上に寄与する
ところが第である。As explained above, according to the present invention, AI of multilayer wiring
! Even if the distance between the wiring and the Aj7 wiring is 1.5 μm or less, the insulating film on the multilayer wiring can be easily flattened, preventing disconnection, fine pattern formation, and migration. Therefore, the formation of multilayer wiring is possible. The first is that it contributes to improved reliability.
第１図は本発明の原理説明図。
第２図は本発明の第１の実施例の工程順模式断面図。
第３図は本発明の第２の実施例の工程順模式断面図。
第４図は従来例の説明図である。
図において。
ｌは下地絶縁膜、 ２はＡｌ配線膜。
３は凹部、 ４は層間絶縁膜。
５はボイド、 ６はＳＯＧ膜。
７まレジスト膜、 ８は下地Ｓｉｎ、膜。
９よ第１層のＡｌ配線膜。
１０；！凹部、 ｔｉｌｔ第１ ノＣＶＤ
−３ｉＯｘ膜。
１２１第２ （７）ＣＶＤ−ＳｉＯｘ膜。
１３ｉボイド、 １４は第２層のＡｊ７Ａ７配
線膜５は下地ＳｉＯｘ膜、 １６は第１層のＡＩ！
配線膜。
１７マ凹部、１８ハ第１ ノＣＶＤ−３ｉＯｔ膜。
１９はＳＯＣ膜、２０はレジスト膜。
２１ハ第２ （７）ＣＶＤ−３ｉＯｚ膜。
２２は第２層のＡ１配線膜
本発明の第１の実旭脅・１のニオＬ噂目菓式前面同第
２ 図
本発明の原１！誂四゛図
解 １［！ｌ
デ紬−束例 ｆ）盲愛＝ ロ月 同
第 ４ｔ２］FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a schematic sectional view of the process order of the first embodiment of the present invention. FIG. 3 is a schematic sectional view of a second embodiment of the present invention in the order of steps. FIG. 4 is an explanatory diagram of a conventional example. In fig. 1 is a base insulating film, and 2 is an Al wiring film. 3 is a recess, and 4 is an interlayer insulating film. 5 is void, 6 is SOG film. 7 is a resist film, and 8 is an underlying Sin film. 9, first layer Al wiring film. 10;! Recess, tilt 1st CVD
-3iOx film. 121 2nd (7) CVD-SiOx film. 13i void, 14 is the second layer Aj7A7 wiring film 5 is the base SiOx film, 16 is the first layer AI!
Wiring film. CVD-3iOt film with 17mm concave portion and 18mm first CVD-3iOt film. 19 is an SOC film, and 20 is a resist film. 21C2 (7) CVD-3iOz film. 22 is the second layer A1 wiring film of the first actuality of the present invention.
2 Figure Origin of the present invention 1! Illustration 1 [! l De Tsumugi - bundle example f) Blind love = Rozuki same No. 4t2]
Claims (1)
形成する層間絶縁膜（４）を、該凹部（３）の両側から
成長する層間絶縁膜（４）の端部が接触して、該層間絶
縁膜（４）の表面が平坦化する厚さまで成長することを
特徴とする多層配線の平坦化方法。 ２）アルミニウム配線膜（２）間の凹部（３）を覆って
、該アルミニウム配線膜（２）上にスピン・オン・グラ
ス（ＳＯＧ）膜（６）を被覆し、該凹部（３）上にレジ
スト膜（７）のパターンを形成し、該レジスト膜（７）
をマスクとして、等方性エッチングにより、該アルミニ
ウム配線膜（２）上のＳＯＧ膜（６）をエッチング除去
して、該凹部（３）内のみに該ＳＯＧ膜（６）を平坦に
残すことを特徴とする多層配線の平坦化方法。[Claims] 1) An interlayer insulating film (4) formed to cover a recess (3) between aluminum wiring films (2) is formed by forming an interlayer insulating film (4) that grows from both sides of the recess (3). A method for planarizing multilayer wiring, characterized in that the interlayer insulating film (4) is grown to a thickness such that the ends thereof are in contact and the surface of the interlayer insulating film (4) is planarized. 2) A spin-on-glass (SOG) film (6) is coated on the aluminum wiring film (2), covering the recess (3) between the aluminum wiring films (2), and A pattern of a resist film (7) is formed, and the resist film (7)
Using as a mask, the SOG film (6) on the aluminum wiring film (2) is etched away by isotropic etching, leaving the SOG film (6) flat only in the recess (3). Features a method for flattening multilayer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3436590A JPH03237721A (en) | 1990-02-15 | 1990-02-15 | Method of flattening multilayer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3436590A JPH03237721A (en) | 1990-02-15 | 1990-02-15 | Method of flattening multilayer wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03237721A true JPH03237721A (en) | 1991-10-23 |
Family
ID=12412141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3436590A Pending JPH03237721A (en) | 1990-02-15 | 1990-02-15 | Method of flattening multilayer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03237721A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100355867B1 (en) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | a manufacturing method of a semiconductor device |
| DE102012106780A1 (en) | 2011-08-10 | 2013-02-14 | Daido Kogyo Co., Ltd. | spoked |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6334956A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Manufacture of semiconductor device |
| JPS63318752A (en) * | 1987-06-22 | 1988-12-27 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1990
- 1990-02-15 JP JP3436590A patent/JPH03237721A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6334956A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Manufacture of semiconductor device |
| JPS63318752A (en) * | 1987-06-22 | 1988-12-27 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100355867B1 (en) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | a manufacturing method of a semiconductor device |
| DE102012106780A1 (en) | 2011-08-10 | 2013-02-14 | Daido Kogyo Co., Ltd. | spoked |
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