JPS6334956A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a thin portion at the layer and a wedge-shaped crack at an upper-layer wire formed on the surface of the second interlayer insulation film by a method wherein a protruding portion at the first interlayer insulation film formed on an underlayer wire is removed to make the portion flat and then the second interlayer insulation film is formed. CONSTITUTION:An underlayer wire 3 is selectively formed on an oxide film which covers a semiconductor substrate 1 and has a selectively made opening. The first interlayer insulation film 4 covering the surface is formed. Then, the portion excluding a protruding part 4A at the first interlayer insulation film 4 located on the underlayer wire 3 is covered with a photoresist mask 7 so that the protruding part 4A at the first interlayer insulation film 4 can be etched to make it flat. After the mask 7 has been removed, the second interlayer insulation film 5 is formed on the surface. Then, an opening is formed at the part which is prescribed on the first interlayer insulation film 4 located on the underlayer wire 3 and the second interlayer insulation film 5. After that, an upperlayer wire 6 made of aluminium, etc. is formed in such a way that it can cover this opening and can be extended over the second interlayer insulation film 5, and a two-layer wire can be completed. Through this constitution, a thin portion at the layer or a wedge-shaped crack can not be produced on the upper-layer wire 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure.

[Conventional technology]

2. Description of the Related Art In recent years, semiconductor devices have become increasingly highly integrated and densely packed, and as a result, circuit elements and wiring patterns have become finer and wiring has become more multilayered. However, it has conventionally been difficult to achieve both miniaturization of wiring patterns and multilayered wiring. In other words, from the standpoint of miniaturization, it is desirable that the side surfaces of the lower layer wiring be perpendicular to the underlying layer, but if the side surfaces of the lower layer wiring are made perpendicular to the underlying layer, a steep step will be created in the interlayer insulating film above the lower layer wiring. It is formed. This will be explained below using FIGS. 2(a) to 2(c).

FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining a conventional method of manufacturing a semiconductor device.

First, as shown in FIG. 2(a), an oxide film 2 covering a semiconductor substrate 1 including a plurality of circuit elements (not shown in the figure) and having selectively provided openings is formed on the upper surface of the oxide film 2. A lower layer wiring 3 made of A1 or the like is selectively formed.

Next, as shown in FIG. 2(b), the lower layer wiring 3 and the oxide film 2 are
An interlayer insulating film 4 is formed to cover the surface.

Next, as shown in FIG. 2(c), an opening is formed in the interlayer insulating film 14, and an upper layer wiring 6 is selectively formed to cover the opening and extend over the interlayer insulating film 14. do.

In the conventional semiconductor device formed in this way, since the side surface of the lower layer wiring 3 is perpendicular to the underlying layer, a steep step is formed in the interlayer insulating film 14, and the upper layer wiring 6 is formed on this steep layer. As a result, thin portions and wedge-shaped cracks 10 are likely to occur in the upper layer wiring 6. The thinner portions and wedge-shaped cracks 10 become more pronounced as the steps of the interlayer insulating film 14 become steeper, and there is a risk of disconnection in the wiring.

Even if this wedge-shaped crack 10 does not break the upper layer wiring 6, there is a risk that the wire will break due to electric field concentration during long-term use, reducing the lifespan of the semiconductor device. .

As a solution to the above-mentioned problem, the side surfaces of the lower layer wiring are sloped so that they are not perpendicular to the underlying layer, thereby preventing the formation of steep steps in the interlayer insulating film.

As another solution, a method has been proposed and implemented in which a phosphor glass film is used as an interlayer insulating film, and after the phosphor glass film is formed, it is reflowed by high-temperature heat treatment at around 1000° C. to smooth the stepped portion.

[Problems to be Solved by the Invention] In the above-mentioned method of making the side surface of the lower layer wiring slope, there is a limit to making the side surface of the lower layer wiring sloped from the viewpoint of miniaturization of the wiring pattern. This is an inappropriate method to achieve this.

In addition, although the method of using a phosphorus glass film as an interlayer insulating film has certain effects, it requires high-temperature heat treatment or 4 pins, and is limited to a phosphorus glass film as an interlayer insulating film. Therefore, it has the problem that its range of use is limited.In other words, due to the high temperature heat treatment at around 1000℃, the characteristics of circuit elements are likely to change due to re-diffusion of the impurity diffusion region. Since the materials used, such as gold (1) and aluminum (A1), are not used due to their melting points, the materials for the lower layer wiring are also limited.

Furthermore, interlayer insulating films include not only phosphor glass films, but also oxide films produced by vapor phase growth, oxide films produced by plasma chemical reactions, nitride films, etc., and these insulating films have better moisture resistance and passivation than phosphor glass films. Although some have excellent properties in terms of effectiveness and adhesion with wiring, the method of using the above-mentioned phosphorus glass film as an interlayer insulating film limits the amount of interlayer insulating film, making it difficult to improve the quality of semiconductor devices. There is also the problem that quality cannot be achieved.

It is an object of the present invention to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device that allows fine patterning of the wiring pattern of a semiconductor device having a multilayer wiring structure and that does not pose the risk of disconnection in the wiring. There is a particular thing.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a lower wiring on an insulating film on a semiconductor substrate, and providing a first interlayer insulating film on the lower wiring, and then protruding the first interlayer insulating film. forming a second interlayer insulating film on the planarized first interlayer insulating film; and forming an upper layer wiring on the second interlayer insulating film. It consists of a process.

1. Example] Next, embodiments of the present invention will be described using the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps to explain one embodiment of the present invention.

First, as shown in FIG. 1 (a), an oxide film 2 covering a semiconductor substrate 1 including a plurality of circuit elements (not shown in the figure) and having selectively provided openings is formed. Then, a lower layer wiring 3 made of AI or the like is selectively formed to cover this opening.

Next, as shown in FIG. 1(b), a first interlayer insulating film 4 covering the surfaces of the lower wiring 3 and the oxide film 2 is formed. Subsequently, a portion of the first interlayer insulating film 4 on the lower wiring 3 except for the protrusion 4A is covered with a mask 7 made of photoresist 1.

Next, as shown in FIG. 1(c), the protrusion 4A of the first interlayer insulating film 4 is etched and planarized by wet or dry etching, and then the mask 7 is removed.

Next, as shown in FIG. 1(d), a second interlayer insulating film 5 is formed on the surface of the first interlayer insulating film 4.

Subsequently, after forming an opening in a predetermined portion of the first interlayer insulating film 4 and the second interlayer insulating film 5 on the lower wiring 3, the opening is covered and the second interlayer insulating film 5 is covered. An upper layer wiring 6 made of A1 or the like is formed so as to extend from the upper layer to complete the two-layer wiring.

As described above, in this embodiment, by removing part or all of the protrusion 4A of the first interlayer insulating film 4, the first
The interlayer insulating film 4 has no steep steps and is flattened.

Even if the second interlayer insulating film 5 is formed on the flattened surface of the first interlayer insulating film 4, no steep steps will be formed. Therefore, thin portions and wedge-shaped cracks do not occur in the upper layer wiring 6 formed on the upper surface of the second interlayer insulating film 5. Further, the effect is the same even if the side surfaces of the lower layer wiring are perpendicular, and it is effective for miniaturizing the lower layer wiring pattern. Furthermore, according to this embodiment, there are no restrictions on the materials of the interlayer insulating film and the lower wiring.

In the above embodiment, the first interlayer insulating film and the second interlayer insulating film are
The material of the interlayer insulating film is not limited, but it may be the same material or different materials.

〔Effect of the invention〕

As explained above, the present invention removes and flattens the protruding portion of the first interlayer insulating film on the lower wiring, and subsequently forms the second interlayer insulating film, thereby improving the surface of the second interlayer insulating film. A semiconductor with a multilayer wiring structure that allows for finer wiring patterns and eliminates the risk of disconnection in the wiring because thin film parts and wedge-shaped cracks do not occur in the upper layer wiring formed in the process. A method for manufacturing the device is obtained.

[Brief explanation of the drawing]

1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining one embodiment of the present invention;
Figures (a) to (C) are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining a conventional method of manufacturing a semiconductor device. ]...Semiconductor substrate, 2...Oxide film, 3...Lower wiring, /-1...First interlayer insulating film, 4A...Protrusion, 5...Second interlayer insulation Film, 6... Upper layer wiring, 7.
...Mask, 10... Wedge-shaped crack, 14... Interlayer insulating film. Agent Patent Attorney Uchihara A long time ago, ′ （、・′

Claims (1)

[Claims] a step of forming a lower layer wiring on an insulating film on a semiconductor substrate;
After providing a first interlayer insulating film on the lower wiring, the first
a step of etching and planarizing the protrusion of the interlayer insulating film; a step of forming a second interlayer insulating film on the planarized first interlayer insulating film; and a step of forming a second interlayer insulating film on the planarized first interlayer insulating film; 1. A method of manufacturing a semiconductor device, comprising the steps of: forming an upper layer wiring;