JPS63318752A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain aluminum-wiring isolation structure, in which electrical interaction among aluminum wirings on the same layer is reduced, by using a cavity having a small dielectric constant as at least one part of isolation among the wirings formed onto a semiconductor substrate. CONSTITUTION:An insulator is buried between wirings 11 shaped onto a semiconductor substrate 17, and at least one part of the insulator consists of a cavity 100. A plasma CVDSiN film, a plasma CVDSiO film, a normal pressure CVDSiO film, a normal pressure CVDPSG film, etc., formed while selecting conditions, in which the cavity 100 is shaped only in a narrow region, in which a space between the aluminum wirings 11 extends over 2mum or less, are employed as an insulating film 13 on the aluminum wirings 11. For form said cavity, the film may be shaped under the conditions of the inferior stepped coat-ability. Accordingly, a mean free path lambda in the vapor phase of an intermediate product or atoms and an atomic group (a reactant) and the mean free path sigma of the surface motion of the reactant reaching the surface of the semiconductor substrate are reduced normally in a plasma CVD method and a normal pressure CVD method.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and in particular provides a structure for separating aluminum wiring on the same layer in a semiconductor device that can be highly integrated.

BACKGROUND OF THE INVENTION The isolation structure between aluminum interconnects on the same layer in a conventional semiconductor device includes a plasma SiO film, a plasma SiN film, a bias spa, a 7-ter SiO film formed on an aluminum interconnect 61, as shown in FIG. An insulating film 62 of one type may be buried between the aluminum layers 51, or a 5oG (spin-on glass) film 63 or the like may be formed on a thin insulating film 62 such as a plasma SiO film or a plasma SiN film as shown in FIG. The two or more types of insulating films formed are buried between the aluminum wiring lines 61. 54.64 is an insulating film, 5
5.65 is a semiconductor substrate.

Problems to be Solved by the Invention However, in such a structure, as the spacing between the aluminum wiring lines 61°61 becomes narrower, the electrical interaction between the aluminum wiring lines will increase, making it difficult to achieve high integration and miniaturization of semiconductor devices. This is a major hindrance.

In view of these problems, the present invention provides an aluminum wiring isolation structure that reduces electrical interaction between aluminum wirings on the same layer.

Means for Solving the Problems The technical means of the present invention for solving the above-mentioned problems is to use a cavity with a small dielectric constant in at least a part of the separation between the wirings formed on the semiconductor substrate. The goal is to create a structure with small electrical interaction.

Effect: According to this technical means, it is possible to reduce the parasitic capacitance between the wirings, which becomes a problem when the spacing between the wirings becomes narrow, so that the influence of electrical interaction between the wirings can be reduced.

EXAMPLE A first example of the present invention will be described below with reference to FIG. In FIG. 1, an insulating film 13 on an aluminum wiring 11
is a plasma (
jVDsiN film, plasma CVD SiO film, normal pressure C
These include a VD5iO film, a normal pressure CjVDPSG film, and the like. In order to form the cavity, the film may be formed under conditions that provide poor step coverage. For this purpose, in general, in the plasma CvD method and atmospheric pressure CVO method, the mean free path λ of intermediate products, atoms, or atomic groups (hereinafter referred to as reactants) in the gas phase, and the reactants that have reached the surface of the semiconductor substrate are determined. It is sufficient to reduce the mean free path σ of the surface motion of . λ tends to decrease as the deposition pressure increases, and σ tends to decrease as the concentration of adsorbed molecules on the substrate surface per unit time increases and as the substrate temperature decreases. Therefore, in order to form the cavity 100, plasma C
In the vD method, it is sufficient to increase the deposition pressure to several rorr or more or to increase the plasma power, and in the atmospheric pressure CVD method, it is sufficient to mainly increase the reaction gas flow rate. When the insulating film 13 is formed on the aluminum wiring 11 under these conditions, the cavity size 18 will be 0.5±0.3 μm in the case of aluminum wiring with a film thickness of 0.8 to 1 μm and an interval of 2 to 1 μm. , and in the aluminum wiring 11 with a spacing of 1 μm or less, the wiring spacing is approximately A
−%. The size of the cavity 18 is equal to the mul wiring 1
1, the larger the film thickness of the multilayer wiring 11, and the conditions for forming the insulating film 13, the conditions under which λ and σ become smaller can be made larger. Also, regarding the multilayer wiring 11, the cavity 13 can be made larger as the shape of the side wall becomes inversely tapered. 14 is a 5OG (spin-on-glass) film for planarization, and 16 is an insulating film formed by atmospheric pressure CVD or plasma CVD.

A second embodiment will be explained based on FIG.

This embodiment uses aluminum wiring 2 corresponding to the first embodiment.
This embodiment further improves the reliability of the semiconductor device by forming a thin plasma 8iN film 22 between the semiconductor device 1 and the insulating film 23, and other points are the same as the first embodiment. 24 is SOG
25 and 26 are insulating films, and 27 is a semiconductor substrate.

A third embodiment will be explained based on FIG.

The steps up to the formation of the insulating film on the aluminum wiring 31 are as follows. This is similar to the second embodiment. Thereafter, in this embodiment, the insulating film 33 is planarized by an etch-back method, and an insulating film 34 of the same type or different type as the insulating film 33 is formed thereon. 36 is an underlying insulating film, and 37 is a semiconductor substrate.

The fourth embodiment will be explained based on FIGS. 4a and 4b. In this example, a plasma SiN film 42 is formed between an aluminum wiring 41 and an insulating film 43 corresponding to the third example, and other points are the same as the third example. In Example A, the plasma 81N film 42 on the top of the aluminum wiring 41 is etched by the etch pack method, and in the second example, the plasma 8iN film 42 is left. 44.46 is an insulating film,
47 is a semiconductor substrate.

As described above, according to the device structures of the first to fourth embodiments, plasma 3i)1 is applied only to the narrow area between the aluminum wirings.
(permittivity ~6), plasma 810, atmospheric pressure CVNSI
o, atmospheric pressure cvnpse (both have a dielectric constant of ~4), it is possible to form a cavity 100 of air or nitrogen (dielectric constant ~1), which has a lower dielectric constant than an insulating film with a dielectric constant of ~1, Parasitic capacitance between wiring lines can be reduced. Also, regarding the dielectric strength between aluminum wiring lines, the structure in which a cavity is formed has a higher voltage than the conventional structure in which an insulating film is buried between the wiring lines.

Effects of the Invention As described above, according to the present invention, it is possible to reduce the parasitic capacitance between wirings made of aluminum or the like with fine wiring intervals, thereby reducing the influence of electrical interaction between fine wirings. This will greatly contribute to the miniaturization of semiconductor devices.

[Brief explanation of drawings]

1 to 4 are structural cross-sectional views of semiconductor devices according to first to fourth embodiments of the present invention, and FIG. FIG. 6 is a structural sectional view of a conventional semiconductor device. 11.21.31. 41... Aluminum wiring, 2
2゜42...Plasma SiN film, 13, 15,
16゜23.25, 26, 33, 34, 36, 43゜4
4.46... Insulating film, 14.24...
5OG (spin-on glass) film, 7, 27, 37.47
・・・・・・Semiconductor substrate, 18.28, 38.48...
...Cavity size, 1oo...Cavity. Name of agent: Patent attorney Toshio Nakao and 1 other person #-
7rL miro zi'jc

Claims (1)

[Claims] A semiconductor device characterized in that an insulating material is buried between wirings formed on a semiconductor substrate, and at least a portion of the insulating material is formed as a cavity.