JPH1022389A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase or decrease the capacitance between identical or different wiring layers by preventing wirings from corroding due to external water content, etc. SOLUTION: First and second wiring layers 3, 6 are formed on, a wiring layer base substrate 2. A low-dielectric const. layer 4 is formed in portions between the wiring layers 3, 6 where the capacitance is to be reduced. A high- dielectric const. layer 8 is formed in portions between the wiring layers 3, 6 where the capacitance is to be increased. Other portions are covered with a first and second protective films 5, 7 usually made of silicon oxide.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing or increasing the relative permittivity while securing the waterproofness of an insulating film between wirings and between wiring layers to increase the capacity between wirings and between wiring layers. The present invention relates to a semiconductor device which is reduced or increased.

[0002]

2. Description of the Related Art Conventionally, in a high-density integrated circuit such as an LSI,
Semiconductor elements, pad electrodes, and the like are connected by these wiring layers while two or more wiring layers are bordered by using an insulating layer such as a silicon oxide film. In this case, when the relative dielectric constant of the insulating film is approximately 4.1 as the silicon oxide film, a main material gas such as tetraethoxysilane containing no impurities is vapor-grown on a silicon substrate by a plasma CVD method. Is used, and the dielectric constant of the insulating film is about 3.9. When necessary, a silicon substrate oxidized by a thermal oxidation method or the like is used.

[0003]

In recent years, however, there has been a demand for higher speed semiconductor devices.
No. 302704, “Semiconductor device”, JP-A-3-21
Techniques such as "Semiconductor Device with Low Wiring Parasitic Capacitance and Manufacturing Method thereof" in Japanese Patent No. 026 aim to reduce the capacitance between each wiring layer and the amount of static electricity between each wiring in each wiring layer. In this case, in the “semiconductor device” described in JP-A-6-302704, a semiconductor substrate 102 having a plurality of semiconductor elements formed on its surface as shown in FIG. A plurality of metal wiring films 103 for connecting the semiconductor elements to each other and each of the semiconductor elements and an external device; and fluorine formed to cover the metal wiring films 103 and to insulate the metal wiring films 103 from each other. And a silicon oxide film 105 formed on the silicon oxide film 104 and containing nitrogen for preventing moisture from entering the silicon oxide film 104 from the outside. This prevents moisture from entering the silicon oxide film 104 containing fluorine, which has high water absorption due to the silicon oxide film 105 containing nitrogen. Et al., Placing the silicon oxide film 104 containing fluorine dielectric constant is smaller between the metal wiring film 103 is made smaller these electrostatic capacitance between each of the metal wiring film 103.

Further, in Japanese Unexamined Patent Publication No. Hei 3-21026, "Semiconductor device having low wiring parasitic capacitance and method of manufacturing the same", a semiconductor substrate 112 having a plurality of semiconductor elements formed on its surface as shown in FIG. And this semiconductor substrate 1
12, an insulating layer 113 formed on
A lower conductor layer 114 that is stacked and etched on the upper conductor layer 114; an upper conductor layer 115 that is formed of a material having an etching rate different from that of the lower conductor layer 114 and is stacked on the lower conductor layer 14 and etched; Upper conductor layer 115
And an insulating layer 117 formed so as to cover the upper conductor layer 115 and the like.
Thus, the semiconductor device 111 is configured. By etching the lower conductor layer 114 using the sidewalls 116 and the upper conductor layer 115 as a mask, each wiring formed by the lower conductor layer 114 and the upper conductor layer 115 can be formed while increasing the margin for misalignment. In this case, the capacitance between these wirings is reduced.

However, Japanese Patent Application Laid-Open No.
Japanese Patent Application Laid-Open No. 04-21026 and Japanese Unexamined Patent Application Publication No. Hei 3-21026 have the following problems.
First, a "semiconductor device" disclosed in JP-A-6-302704 is disclosed.
Here, the silicon oxide film 10 to which fluorine is added is used to reduce the capacitance between the metal wiring films 103.
Because of the high hygroscopicity of No. 4, the silicon oxide film 105 containing nitrogen must be entirely covered with the silicon oxide film 105 containing nitrogen, and there is a problem that the number of manufacturing steps increases by that much. Even if the silicon oxide film 104 containing fluorine is covered with the silicon oxide film 105 containing nitrogen, the silicon oxide film
When a slight scratch or the like is made on the silicon nitride film 5, the moisture penetrates from the scratch, the moisture is absorbed by the silicon oxide film 104 to which fluorine is added, and the metal wiring film 103 covered with the silicon oxide film 104 is corroded. For example, there is a problem that the performance is not stable as compared with a silicon oxide film using SiO ₂ or the like which has been widely used conventionally.

[0006] Japanese Patent Application Laid-Open No. 3-21026 discloses a "semiconductor device having a low wiring parasitic capacitance and a method of manufacturing the same", in which a sidewall formed on a side of an upper conductor layer 115 laminated on a lower conductor layer 114 is disclosed. As a material for 116,
Since a normal dielectric material is used, the relative permittivity of the sidewall makes it possible to use the same dielectric layer on the same wiring layer.
There was a problem that the capacitance between the wirings could not be reduced too much. In view of the above circumstances, the present invention reduces the capacitance between wiring layers formed in the same layer or different layers while preventing the wiring from being corroded by external moisture or the like. It is another object of the present invention to provide a semiconductor device capable of preventing problems such as wiring delay and crosstalk from occurring. Also,
According to the second, fifth and sixth aspects, the capacitance between the wiring layers formed in the same layer or different layers is increased while preventing the wiring from being corroded by external moisture or the like, so that the power supply voltage or the ground voltage is reduced. It is an object to provide a semiconductor device which can be stabilized.

[0007]

In order to achieve the above object, according to the present invention, there is provided a wiring base substrate on which a plurality of semiconductor elements are formed, and a multilayer formed on the wiring base substrate. In a semiconductor device having a wiring layer for electrically connecting the semiconductor element, a relative dielectric constant of an insulating film disposed in another portion between wiring layers whose capacitance is to be reduced among the wiring layers. It is characterized in that an insulating film having a low dielectric constant is arranged. In order to achieve the above object, according to a second aspect of the present invention, a wiring base substrate on which a plurality of semiconductor elements are formed, and a multi-layer formed on the wiring base substrate to electrically connect the semiconductor elements In a semiconductor device having a wiring layer, an insulating film having a relative dielectric constant higher than the relative dielectric constant of an insulating film disposed in another portion is provided between wiring layers of which capacitance is to be increased among respective wiring layers. It is characterized by being arranged. In claim 3, claim 1
In the semiconductor device described in (1), an insulating film having a low relative dielectric constant is arranged only between the wirings arranged in the same layer among the respective wiring layers. Claim 4
The semiconductor device according to claim 1 is characterized in that an insulating film having a low relative dielectric constant is disposed only between wirings arranged in different layers among the wiring layers. According to a fifth aspect of the present invention, in the semiconductor device according to the second aspect, an insulating film having a high relative dielectric constant is disposed only between the respective wirings arranged in the same layer among the respective wiring layers. I have. According to a sixth aspect of the present invention, in the semiconductor device according to the second aspect, an insulating film having a high relative dielectric constant is arranged only between the wirings arranged in different layers among the wiring layers. . According to the above configuration, in claim 1, 3, and 4, a wiring undersubstrate on which a plurality of semiconductor elements are formed, and a wiring layer formed in multiple layers on the wiring undersubstrate and electrically connecting the semiconductor elements. In the semiconductor device having the above, an insulating film having a relative permittivity lower than the relative permittivity of the insulating film disposed in another part is disposed between wiring layers of which capacitance is to be reduced among the respective wiring layers. Thus, while preventing the wiring from being corroded by external moisture and the like, the capacitance between the wiring layers formed in the same layer or different layers is reduced, so that problems such as wiring delay and crosstalk do not occur. . A semiconductor device according to claim 2, 5, or 6, further comprising: a wiring base substrate on which a plurality of semiconductor elements are formed; and a wiring layer formed in multiple layers on the wiring base substrate to electrically connect the semiconductor elements. By arranging an insulating film having a dielectric constant higher than the dielectric constant of an insulating film disposed in another portion between wiring layers of which capacitance is to be increased among each wiring layer, external moisture can be reduced. The capacitance between the wiring layers formed in the same layer or different layers is increased while preventing the wiring from being corroded by the above-described method, and the power supply voltage and the ground voltage are stabilized.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a schematic configuration diagram showing one embodiment of a semiconductor device according to the present invention. A semiconductor device 1 shown in FIG. 1 has a semiconductor substrate (wiring layer base substrate) 2 on which a plurality of semiconductor elements are formed, and a material such as aluminum or silicon (S
i), a material to which copper (Cu) or the like is added, a material such as polysilicon, or a material in which tungsten (W), titanium (Ti), or the like is laminated on this polysilicon is laminated on the wiring layer base substrate 2. Then, the first wiring layer 3 is formed by etching, a first wiring layer 3 formed by etching, a silicon oxide film to which fluorine (F) is added, a silicon oxide film to which scale (P) is added, and the like. A low-dielectric-constant layer 4 formed between wiring layers having a narrower mutual interval, and a SiO ₂ film formed so as to cover the low-dielectric-constant layer 4 and the first wiring layer 3. And a material such as aluminum, a material obtained by adding Si, Cu, or the like to aluminum, a material such as polysilicon, or a material such as W or Ti on the polysilicon. The first protective coating and the like materials 5
A second wiring layer 6 formed by stacking and etching the second wiring layer 6 and SiO 2 formed to cover the second wiring layer 6.
_{A second} protective film 7 composed of _two films or the like;
N, Ta ₂ O _5, etc., the first and second
The protective film includes a high dielectric constant layer formed between the first wiring layer and the second wiring layer for which the capacitance is to be increased. The first wiring layer 3 electrically connects the semiconductor elements formed on the wiring layer base substrate 2 to each other, and the first wiring layer 3 and the second wiring layer 6 connect the semiconductor elements to external devices. And the semiconductor device 1 is operated.

Next, a procedure for forming the low dielectric constant layer 4 and the high dielectric constant layer 8 constituting the semiconductor device 1 will be described. First, when the low dielectric constant layer 4 is formed, as shown in FIG. 2A, a material such as aluminum, a material obtained by adding Si, Cu, or the like to aluminum, a material such as polysilicon, or W on the polysilicon is used. , Ti, etc. are laminated on the wiring base substrate 2,
This is etched to form the first wiring layer 3. Thereafter, as shown in FIG. 2B, a silicon oxide film 9 to which fluorine is added is formed so as to cover the first wiring layer 3 by a method such as plasma CVD or the like, and then, as shown in FIG. As described above, the portion where the capacitance between the wirings needs to be reduced by utilizing the locational difference of the deposit thickness by the anisotropic etching, that is, the distance d between the first wiring layers 3 is set to “1 μm” or less. A low dielectric layer 4 is formed by leaving only a relatively narrow portion and removing other portions. When the high dielectric constant layer 8 is formed, as shown in FIG. 3A, a material such as aluminum, a material obtained by adding Si, Cu, or the like to the aluminum, a material such as polysilicon, W, T on this polysilicon
i and the like are laminated on the wiring layer base substrate 2 and are etched to form a first wiring layer 3. Then, a silicon film is formed so as to cover the first wiring layer 3. Laminate.

Next, after the silicon film is oxidized to form the first protective film 5, a material such as aluminum, a material obtained by adding Si, Cu, or the like to aluminum, a material such as polysilicon, or this polysilicon is used. A material such as W, Ti or the like is laminated on the first protective film 5 and is etched,
After forming the second wiring layer 6, a silicon film is laminated so as to cover the second wiring layer 3 and oxidized to form a second protective film 7. Then, as shown in FIG. 3B, after applying a resist 10 on the second protective film 7, CM
The first and second wiring layers 3 and 6 are planarized by P or the like.
A photolithography process is performed on a portion, such as a power supply line or a GND line, where the capacitance between wirings needs to be increased, among the relatively thin portions having a height h of 0.5 μm or less. Then, the resist 10 on the second wiring layer 6 is removed to form an opening 11. Next, an impurity for increasing the dielectric constant is implanted into the opening 11 at a high energy of 500 KeV to 1 MeV or more to form a high dielectric layer 8 between the first and second wiring layers 3 and 6. After that, the resist 10 remaining on the second protective film 7 is removed as shown in FIG.

As described above, in this semiconductor device 1, a relative dielectric constant of 3.8 when a normal silicon oxide film is used is provided between wiring layers of each first wiring layer 3 whose distance between them is narrow. Since the low dielectric constant layer 4 such as a silicon oxide film doped with fluorine (F) and having a relative dielectric constant of about 3.5 or less, for example, a dielectric substance smaller than about 4.2, is formed. The capacitance between the first wiring layers 3 can be reduced to prevent problems such as wiring delay and crosstalk from occurring (the effects of claims 1, 3, and 4). Also, the first
2. A relative dielectric constant when a normal silicon oxide film is used between the wiring layer 3 and the second wiring layer 6 and between a line where a voltage must be stabilized, such as a power supply line and a ground line. A dielectric having a higher relative dielectric constant than about 8 to 4.2, for example, having a relative dielectric constant of about 7 or more,
Since the high dielectric constant layer 8 made of SiN, Ta ₂ O ₅ or the like is formed, the capacitance of the power supply line and the ground line is increased to reduce the noise of the power supply line.
It can be stabilized (the effects of claims 2, 5, and 6).

Further, the low dielectric constant layer 4 and the high dielectric constant layer 4 are provided only between the first and second wiring layers 3 and 6 where the capacitance is to be increased or the capacitance is to be reduced. 8 is formed, and the other parts are covered with a normal silicon oxide film. Therefore, the capacitance is increased or decreased only in the critical parts, and the reliability of the other parts is increased with respect to external factors. (Common effects of claims 1 to 6). In the above-described embodiment, the high dielectric constant layer 8 is formed between the first and second wiring layers 3 and 6 so that the first and second wiring layers 3 and 6 are formed.
Although the capacitance between the wiring layers 3 and 6 is set to be high, the first and second wiring layers 3 and 6 need to prevent the occurrence of crosstalk or the like unlike signal lines. , The first and second wiring layers 3,
6, a low dielectric constant layer 4 is formed between the first and second wiring layers 3,
The capacitance between the six may be reduced.

In the above-described embodiment, the silicon oxide film doped with fluorine is used as the low dielectric constant layer 4 formed between the first wiring layers 3. An ordinary silicon oxide film to which fluorine is not added is thinly deposited so as to cover the silicon oxide film, and a silicon oxide film having a laminated structure in which a silicon oxide film to which fluorine is added is deposited on the silicon oxide film. It is necessary to reduce the capacitance between the wirings in a relatively narrow portion where the distance d between the first wiring layers 3 is “1 μm” or less by utilizing the positional difference in the deposit thickness by the isotropic etching. The low dielectric constant layer 4 may be formed by leaving only a certain portion and removing the other portion.

[0014]

As described above, according to the present invention, according to the first, third, and fourth aspects, the wiring layers formed on the same layer or different layers while preventing the wiring from being corroded by external moisture or the like. Wiring delay,
Problems such as crosstalk can be prevented from occurring. According to the second, fifth and sixth aspects, the capacitance between wiring layers formed in the same layer or different layers is increased while preventing the wiring from being corroded by external moisture or the like.
The power supply voltage and the ground voltage can be stabilized.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of a semiconductor device according to the present invention.

2 (a), 2 (b) and 2 (c) are schematic diagrams showing an example of a procedure when forming a low dielectric constant layer shown in FIG.

FIGS. 3A, 3B and 3C are schematic diagrams showing an example of a procedure when forming the high dielectric constant device shown in FIG.

FIG. 4 shows a conventional Japanese Patent Application Laid-Open No. 6-302704.
FIG. 1 is a schematic configuration diagram for describing an outline of a “semiconductor device” shown in FIG.

FIG. 5 is a schematic configuration diagram for explaining an outline of “a semiconductor device having a low wiring parasitic capacitance and a method of manufacturing the same” disclosed in Japanese Patent Application Laid-Open No. 3-21026.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Wiring layer base board, 3 ... First wiring layer, 4 ... Low dielectric constant layer (insulating film with low relative dielectric constant), 5
... first protective film, 6 ... second wiring layer, 7 ... second protective film,
8 high dielectric constant layer (insulating film having high relative dielectric constant), 9 silicon oxide film, 10 resist, 11 opening

Claims (6)

[Claims] 1. A semiconductor device comprising: a wiring base substrate on which a plurality of semiconductor elements are formed; and a wiring layer formed on the wiring base substrate in multiple layers and electrically connecting the semiconductor elements. The semiconductor device according to claim 1, wherein an insulating film having a lower relative dielectric constant than an insulating film disposed in another portion is disposed between wiring layers whose capacitance is to be reduced. 2. A semiconductor device, comprising: a wiring base substrate on which a plurality of semiconductor elements are formed; and a wiring layer formed on the wiring base substrate in a multi-layer and electrically connecting the semiconductor elements. The semiconductor device according to claim 1, wherein an insulating film having a higher relative dielectric constant than an insulating film disposed in another portion is disposed between wiring layers whose capacitance is to be increased. 3. The semiconductor device according to claim 1, wherein an insulating film having a low relative dielectric constant is disposed only between the respective wirings arranged in the same layer among the respective wiring layers. Semiconductor device. 4. The semiconductor device according to claim 1, wherein an insulating film having a low relative dielectric constant is arranged only between the wirings arranged in different layers among the wiring layers. Semiconductor device. 5. The semiconductor device according to claim 2, wherein an insulating film having a high relative dielectric constant is disposed only between the respective wirings arranged in the same layer among the respective wiring layers. Semiconductor device. 6. The semiconductor device according to claim 2, wherein an insulating film having a high relative dielectric constant is arranged only between the wirings arranged in different layers among the wiring layers. Semiconductor device.