JPH04109655A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent improper coverage or corrosion of a wiring pattern by covering a spin-on glass layer exposed in a contact hole between wirings with an insulating film when the hole is formed, and preventing discharge of gas. CONSTITUTION:An insulating film 10 is so formed as to cover the exposed part of a spin-on glass layer 5 at least on the sidewall of a contact hole 8 for electrically connecting wirings therebetween. That is, the exposed part of the sidewall of the hole 8 of the layer 5 used for an insulating film between the layers is covered with the film 10 to prevent discharge of gas containing phosphorus (P) from the layer 5. Thus, coverage and corrosion of the wiring pattern of the upper layer can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a MOS type semiconductor device having a multilayer wiring structure with a spin-on glass layer interposed therebetween, and a method for manufacturing the same.

[Conventional technology]

A spin-on-glass (SOG) layer is used to flatten the space between multilayer interconnections in a semiconductor device.

For example, as shown in FIG. 3, an SiO□ layer 2, which is an insulating layer, is formed on a semiconductor substrate 1, and a wiring pattern 3 made of At or the like is formed thereon. Then, a SiO□ layer 4 is formed on the wiring pattern 3, and a 500 layer 5 for planarization is formed thereon.

Further, a SiO□ layer 6 is formed thereon, and a second layer wiring pattern 7 made of AI or the like is formed on this SiO□ layer 6. The upper layer wiring pattern 7 and the lower layer wiring pattern 3 are electrically connected through a contact hole 8.

[Problem to be solved by the invention]

In the multilayer wiring structure as described above, the 500 layer 5 is made of phosphorus (
Contains P).

Therefore, when forming the contact hole 8, this 5
The 00 layer 5 is exposed on the side wall of the contact hole 8, and the phosphorus (
P) is released. Conventionally, this gas has caused poor coverage and corrosion of the upper layer metal wiring pattern 7.

The present invention has been made in view of the above problems, and
An object of the present invention is to provide a structure and manufacturing method of a semiconductor device that can prevent gas release even in a structure in which the 300th layer is exposed in a contact hole.

[Means to solve the problem]

In order to solve the above-mentioned problem, the invention according to claim 1 of the present invention provides a MOS type semiconductor device having a multilayer wiring structure with a spin-on glass layer interposed between the contact holes for electrically connecting the wirings. The device is characterized in that an insulating film is formed on the side wall portion so as to cover at least the exposed portion of the spin-on glass layer.

Further, the invention according to claim 2 of the present invention provides a method for manufacturing a MOS type semiconductor device having a multilayer wiring structure with a spin-on glass layer interposed therebetween, in which a first insulating layer is formed on a first wiring pattern. forming a spin-on glass layer on the first insulating layer; forming a second insulating layer on the spin-on glass layer; the second insulating layer, the spin-on glass layer and forming a contact hole in the first insulating layer; forming an insulating film at least inside the contact hole; patterning the insulating film to remove the insulating film at the bottom of the contact hole; , a step of leaving the insulating film so as to cover at least an exposed portion of the spin-on glass layer on a side wall portion of the contact hole, and a step of forming a second wiring pattern in a portion including the contact hole. .

C) In the present invention, the exposed portion of the spin-on glass layer used for the glabella insulating film at the side wall of the contact hole is covered with an insulating film to prevent gas from being released. and corrosion can be prevented.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

First, as shown in FIG. 2 (a), the semiconductor substrate 1
: Formation top 5iozNi 2, 1st layer A] distribution wA3
are formed into approximately 3,000 to 8,000 pieces using a sputtering method, and patterned using an F processing technique.

Next, the SiO□ layer 4, which is an insulating layer, is formed by plasma CVD.
By law, we will form a group of approximately 2,000 to 5,000 people, and on F.
300 layers 5 of insulating coating material are formed in approximately 2,000 to 8,000 layers using the SOG coating method.
Furthermore, about 2,000 to 6,000 5iOz layers 6 are formed thereon.

After processing, contact hole 8 is made using microfabrication technology.
is formed on the SiO□ layer 6.500 layer 5 and the Si02 layer 4.

Next, Si is deposited to cover the inside of the contact hole 8.
Next, as shown in FIG. 2(b), an insulating film 10 made of PSG or BPSG is formed in a thickness of about 2,000 to 6,000 layers by vapor phase epitaxy.Then, as shown in FIG.
In order to make ohmic contact between the contact hole 8 and the
The insulating film 10 is removed until the first layer AI wiring 3 is exposed at the bottom. At this time, on the side wall of the contact hole 8,
An insulating film 10 with a thickness of 2000 to 3000 Å or more remains, and 80
The structure is such that the exposed portion of layer 05 is covered.

Thereafter, as shown in FIG. 1, approximately 5 to 10,000 second layer AI wirings 7 are formed by sputtering and patterned.

With this configuration, as shown in Figure 1,
Since the exposed portion of the 800 layer 5 in the contact hole 8 is covered with the insulating film 10, gas containing, for example, phosphorus (P) can be prevented from being released from the 800 layer 5, and the upper layer A
Poor coverage and corrosion of the I wiring 7 can be prevented.

[Effects of the Invention] As explained above, according to the present invention, when forming a contact hole between wirings, the spin-on glass layer exposed in the contact hole is covered with an insulating film to prevent gas release. Therefore, poor coverage and corrosion of the upper layer wiring pattern formed in the contact hole portion can be prevented.

Therefore, it is possible to easily form contact holes in a semiconductor device having a multilayer wiring structure, and to provide a semiconductor device with high reliability.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
FIGS. 2(a) and 2(b) are cross-sectional views showing the method for manufacturing the semiconductor device, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. In addition, in the symbols used in the drawings, 1... Semiconductor substrate 2.4.6... StO□ layer 3... First layer wiring 5... . . . SOC layer 7 . . . Second layer wiring 8 . . . Contact hole insulating film.

Claims (2)

[Claims] (1) In a MOS semiconductor device having a multilayer wiring structure with a spin-on glass layer interposed therebetween, the side wall of a contact hole for electrically connecting the wiring is insulated so as to cover at least the exposed portion of the spin-on glass layer. A semiconductor device characterized in that a film is formed. (2) A method for manufacturing a MOS semiconductor device having a multilayer wiring structure with a spin-on glass layer interposed therebetween, comprising: forming a first insulating layer on a first wiring pattern; forming a second insulating layer on the spin-on glass layer; and forming contact holes in the second insulating layer, the spin-on glass layer, and the first insulating layer. forming an insulating film at least inside the contact hole; patterning the insulating film to remove the insulating film at the bottom of the contact hole; and forming at least the spin-on glass on the side wall of the contact hole. A method for manufacturing a semiconductor device, comprising: leaving the insulating film so as to cover the exposed portion of the layer; and forming a second wiring pattern in a portion including the contact hole.