JPH11251433A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH11251433A
JPH11251433A JP5492298A JP5492298A JPH11251433A JP H11251433 A JPH11251433 A JP H11251433A JP 5492298 A JP5492298 A JP 5492298A JP 5492298 A JP5492298 A JP 5492298A JP H11251433 A JPH11251433 A JP H11251433A
Authority
JP
Japan
Prior art keywords
wiring
metal
contact hole
insulating film
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5492298A
Other languages
Japanese (ja)
Inventor
Muneyuki Matsumoto
宗之 松本
Original Assignee
Rohm Co Ltd
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd, ローム株式会社 filed Critical Rohm Co Ltd
Priority to JP5492298A priority Critical patent/JPH11251433A/en
Publication of JPH11251433A publication Critical patent/JPH11251433A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide an interconnecting structure for electrically connecting an upper-layer wiring and a lower-layer wiring securely, even if the connection metal that connects upper-layer wiring and lower-layer wiring becomes thin along with miniaturization of the wiring pattern, and a method for manufacturing semiconductor devices thereof. SOLUTION: Lower-layer wiring 3 and an interlayer insulating film 4 are formed on a semiconductor substrate 1 via an insulating film 2. A contact hole 4a is formed in the interlayer insulating film 4 and the lower-layer wiring 3, and connection metal 5a is embedded in the contact hole 4 so as to have the metal make contact with the side-wall of the lower-layer wiring 3 that is exposed by the contact hole 4a. In addition, upper-layer wiring 5 is formed on the interlayer insulating film 4 to electrically connect itself to the contact metal 5a.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置の上層配
線と下層配線との接続構造およびその半導体装置の製法
に関する。さらに詳しくは、集積度が向上して微細化
し、配線のコンタクト部も非常に微細化する場合にその
電気的接続を向上させる上層配線と下層配線との接続構
造およびその半導体装置の製法に関する。
The present invention relates to a connection structure between an upper wiring and a lower wiring of a semiconductor device and a method of manufacturing the semiconductor device. More specifically, the present invention relates to a connection structure between an upper layer wiring and a lower layer wiring for improving the electrical connection when the degree of integration is improved and the contact portion of the wiring is also very fine, and to a method of manufacturing the semiconductor device.
【0002】[0002]
【従来の技術】近年半導体装置の高集積化に伴い、その
配線パターンも微細化すると共に、層間絶縁膜を介して
何層にも配線を形成する多層配線構造になっている。こ
のような多層配線構造で、下層配線と上層配線とを接続
する構造は、たとえば図3に示されるように、半導体基
板21上の絶縁膜22上に下層配線23が設けられ、そ
の上の層間絶縁膜24に設けられるコンタクトホール2
4a内に接続用金属25aが埋まるように上層配線25
が設けられることにより形成されている。コンタクトホ
ール24a内の接続用金属25aは、上層配線25の成
膜の際に埋まる金属を利用することもできるし、上層配
線25を設ける前に上層配線とは別の金属によりコンタ
クトホール内のみに接続用金属(プラグ)を設けること
もできる。すなわち、下層配線23上に直接接続用金属
25aがスパッタリングにより堆積されることにより、
下層配線23と接続用金属25aすなわち上層配線25
との電気的接続がなされている。
2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated, their wiring patterns have become finer, and a multilayer wiring structure has been formed in which wiring is formed in multiple layers via interlayer insulating films. In such a multilayer wiring structure, the lower wiring and the upper wiring are connected to each other by, for example, as shown in FIG. 3, a lower wiring 23 is provided on an insulating film 22 on a semiconductor substrate 21 and an upper interlayer wiring is provided. Contact hole 2 provided in insulating film 24
4a so that the connection metal 25a is buried in the upper wiring 25.
Is formed. As the connection metal 25a in the contact hole 24a, a metal buried at the time of forming the upper wiring 25 can be used, or a metal different from the upper wiring before the upper wiring 25 is provided. A connecting metal (plug) may be provided. That is, the direct connection metal 25a is deposited on the lower wiring 23 by sputtering,
Lower wiring 23 and connection metal 25a, that is, upper wiring 25
Electrical connection with the
【0003】[0003]
【発明が解決しようとする課題】前述のように、従来の
多層配線構造を有する半導体装置は、その上層配線と下
層配線との間の電気的接続が下層配線の表面に堆積され
る接続用金属と下層配線との接触のみで電気的に接続さ
れている。しかし、近年の高集積化に伴いパターンの微
細化が図られ、配線パターンも非常に微細化されると共
に、下層配線と上層配線とを電気的に接続する接続用金
属の太さ(コンタクトホールの大きさ)も非常に細くな
ってきており、たとえば細い場合は直径が0.18μm
程度となる。そのため、接続用金属と下層配線との接触
面積が非常に小さくなり、接触による電気的接続が充分
に得られず、接触抵抗が大きくなったり、接続不良にな
ることが生ずるという問題がある。とくにコンタクトホ
ールを形成するためのエッチングを行う際に、そのエッ
チングに伴う汚れがコンタクトホール内の下層配線の表
面に付着すると、完全な接触不良となりやすい。
As described above, in a conventional semiconductor device having a multilayer wiring structure, an electrical connection between an upper wiring and a lower wiring is formed by a connection metal deposited on the surface of the lower wiring. Are electrically connected only by contact with the lower wiring. However, with the recent increase in the degree of integration, patterns have been miniaturized, wiring patterns have become extremely finer, and the thickness of the connecting metal for electrically connecting the lower wiring and the upper wiring (the thickness of the contact hole) has been reduced. Size) is also becoming very thin. For example, when it is thin, the diameter is 0.18 μm.
About. For this reason, the contact area between the connecting metal and the lower-layer wiring becomes extremely small, so that electrical connection by contact cannot be sufficiently obtained, and there is a problem that a contact resistance increases or a connection failure occurs. In particular, when etching for forming a contact hole is performed, if contamination due to the etching adheres to the surface of the lower wiring in the contact hole, complete contact failure is likely to occur.
【0004】本発明はこのような状況に鑑みてなされた
もので、配線パターンが微小化されて上層配線と下層配
線との接続用金属の太さが細くなっても、確実に電気的
に接続することができる上層配線と下層配線との接続構
造およびその半導体装置の製法を提供することを目的と
する。
The present invention has been made in view of such a situation, and even if the wiring pattern is miniaturized and the thickness of the metal for connection between the upper layer wiring and the lower layer wiring is reduced, the electrical connection is surely achieved. It is an object of the present invention to provide a connection structure between an upper-layer wiring and a lower-layer wiring, and a method for manufacturing the semiconductor device.
【0005】[0005]
【課題を解決するための手段】本発明による半導体装置
は、半導体基板上に絶縁膜を介して設けられる下層配線
と、該下層配線上に設けられる層間絶縁膜と、該層間絶
縁膜および前記下層配線に設けられるコンタクトホール
と、該コンタクトホール内に埋め込まれ、前記下層配線
のコンタクトホールにより露出する側壁に接触して設け
られる接続用金属と、該接続用金属と電気的に接続して
前記層間絶縁膜上に設けられる上層配線とからなる上層
配線と下層配線との接続構造を有している。
A semiconductor device according to the present invention comprises a lower wiring provided on a semiconductor substrate via an insulating film, an interlayer insulating film provided on the lower wiring, the interlayer insulating film and the lower layer. A contact hole provided in the wiring, a connection metal buried in the contact hole and provided in contact with a side wall exposed by the contact hole of the lower wiring, and the connection metal electrically connected to the connection metal; It has a connection structure between an upper wiring and an lower wiring composed of an upper wiring provided on an insulating film.
【0006】この構造にすることにより、下層配線と接
続用金属との接触部は、接続用金属の太さである断面積
だけではなく、下層配線に設けられたコンタクトホール
の高さの周囲全体でも接触するため、確実に電気的接続
を得ることができる。
According to this structure, the contact portion between the lower wiring and the connection metal has not only the cross-sectional area which is the thickness of the connection metal but also the entire periphery of the height of the contact hole provided in the lower wiring. However, since they make contact, an electrical connection can be reliably obtained.
【0007】本発明の半導体装置の製法は、半導体基板
上に絶縁膜を介して下層配線を形成し、該下層配線上に
層間絶縁膜を形成し、該層間絶縁膜にコンタクトホール
を形成して該コンタクトホール内に前記下層配線と電気
的に接続されるように接続用金属を埋め込み、該接続用
金属と電気的に接続されるように前記層間絶縁膜上に上
層配線を形成する半導体装置の製法であって、前記層間
絶縁膜にコンタクトホールを形成する際に、前記下層配
線にもコンタクトホールを形成して該下層配線のコンタ
クトホール内に前記接続用金属を埋め込むことを特徴と
する。
According to a method of manufacturing a semiconductor device of the present invention, a lower wiring is formed on a semiconductor substrate via an insulating film, an interlayer insulating film is formed on the lower wiring, and a contact hole is formed in the interlayer insulating film. In a semiconductor device, a connection metal is buried in the contact hole so as to be electrically connected to the lower wiring, and an upper wiring is formed on the interlayer insulating film so as to be electrically connected to the connection metal. The method is characterized in that, when forming a contact hole in the interlayer insulating film, a contact hole is also formed in the lower wiring and the connection metal is buried in the contact hole of the lower wiring.
【0008】前記接続用金属をメタルCVD法により形
成することにより、スパッタ法などに比べて狭いコンタ
クトホール内でもしっかりと金属を埋め込むことができ
るため好ましい。ここにメタルCVD法とは、金属をア
ルキル基と化合させた有機金属とし、反応させて金属を
堆積する方法を意味する。
It is preferable to form the connection metal by a metal CVD method because the metal can be buried firmly even in a narrow contact hole as compared with a sputtering method or the like. Here, the metal CVD method means a method in which a metal is converted to an organic metal in which an alkyl group is combined and reacted to deposit a metal.
【0009】[0009]
【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体装置およびその製法について説明をする。
Next, a semiconductor device of the present invention and a method of manufacturing the same will be described with reference to the drawings.
【0010】本発明の半導体装置は、図1にその一実施
形態の接続構造部の断面説明図が示されるように、半導
体基板1上に絶縁膜2を介して下層配線3が設けられて
いる。そして、下層配線3上に層間絶縁膜4が設けら
れ、その層間絶縁膜4および前記下層配線3にコンタク
トホール4aが設けられている。そして、コンタクトホ
ール4a内に接続用金属5aが埋め込まれ、下層配線3
のコンタクトホール4aにより露出する側壁に接続用金
属5aが接触して設けられている。そして、その接続用
金属5aと連続的に、または別の金属膜により接続用金
属5aと電気的に接続されるように上層配線5が設けら
れている。その結果、接続用金属5aを介して上層配線
5と下層配線3とが電気的に接続された構造の多層配線
の半導体装置となる。
In a semiconductor device according to the present invention, a lower wiring 3 is provided on a semiconductor substrate 1 via an insulating film 2 as shown in FIG. . An interlayer insulating film 4 is provided on the lower wiring 3, and a contact hole 4 a is provided in the interlayer insulating film 4 and the lower wiring 3. The connection metal 5a is buried in the contact hole 4a, and the lower wiring 3
The connection metal 5a is provided in contact with the side wall exposed by the contact hole 4a. The upper wiring 5 is provided so as to be continuously connected to the connection metal 5a or electrically connected to the connection metal 5a by another metal film. As a result, a multi-layer wiring semiconductor device having a structure in which the upper wiring 5 and the lower wiring 3 are electrically connected via the connecting metal 5a is obtained.
【0011】下層配線3は、たとえばAl-Si-Cu、
Al-CuなどのAl系、W、Al、Cuなどの金属が
その用途に応じて用いられ、厚さはたとえば0.4〜2
μm程度、幅が0.3〜100μm程度で設けられる。
また、接続用金属5aおよび上層配線5は、前述の下層
配線3の材料に応じて、それぞれW、Cu、Al、Cu
などが用いられ、その厚さや幅は下層配線3と同程度に
設けられる。なお、下層配線にWやCuが用いられる場
合、その金属の半導体層への拡散を防止するため、その
金属を成膜する前にバリア金属としてWN、Ta、Ta
Nなどの金属が設けられることが好ましい。この下層配
線3は、従来と同様にスパッタリング法により成膜して
パターニングすることにより形成され、接続用金属5a
(上層配線5を含む)は、スパッタリング法によっても
成膜することができるが、コンタクトホールが細くて深
くなるため、後述するように、メタルCVD法または無
電解メッキなどの方法により成膜することにより、コン
タクトホール内に完全に接続用金属5aを埋め込むこと
ができて好ましい。
The lower wiring 3 is made of, for example, Al-Si-Cu,
An Al-based material such as Al-Cu, or a metal such as W, Al, or Cu is used according to its use, and the thickness is, for example, 0.4 to 2 mm.
The width is about 0.3 μm and the width is about 0.3 to 100 μm.
Further, the connection metal 5a and the upper layer wiring 5 are respectively made of W, Cu, Al, Cu depending on the material of the lower layer wiring 3 described above.
And the like, and the thickness and the width thereof are provided to be substantially the same as those of the lower wiring 3. When W or Cu is used for the lower wiring, in order to prevent the metal from diffusing into the semiconductor layer, WN, Ta, Ta is used as a barrier metal before forming the metal.
Preferably, a metal such as N is provided. The lower wiring 3 is formed by forming a film by a sputtering method and patterning it in the same manner as in the related art.
Although the film (including the upper wiring 5) can be formed by a sputtering method, since the contact hole becomes thin and deep, the film is formed by a method such as a metal CVD method or electroless plating as described later. This is preferable because the connection metal 5a can be completely buried in the contact hole.
【0012】層間絶縁膜4は、通常のSiO2 などの絶
縁膜が用いられ、その厚さは通常と同じであるが、たと
えば0.7〜1μm程度に形成される。この層間絶縁膜
4は通常のCVD法により成膜される。
As the interlayer insulating film 4, an ordinary insulating film such as SiO 2 is used, and its thickness is the same as usual, but is formed, for example, to about 0.7 to 1 μm. This interlayer insulating film 4 is formed by a normal CVD method.
【0013】本発明の上層配線と下層配線との接続構造
を有する半導体装置によれば、その両者を接続する接続
用金属が下層配線に設けられたコンタクトホール内に堆
積して設けられている。そのため、下層配線と接続用金
属との接触面積が大幅に上昇する。すなわち、従来の下
層配線の上に堆積されるだけで接触させる方法では、接
続用金属の太さ(断面積)のみで接触していたため、そ
の接触面積は、たとえばその太さの半径をrとすると、
πr2 となる。一方、本発明によりたとえば下層配線の
全厚さに対してコンタクトホールが形成されておれば、
その接触面積は、下層配線の厚さをtとすると、2πr
tとなり、その面積比は、2πrt/πr2 =2t/r
となる。そのため、接続用金属(コンタクトホールの
径)が細くなればなるほどその効果が大きく、前述の接
続用金属の太さが2r=0.18μmで、下層配線の厚
さがたとえば1μmであれば、接触面積は22倍と非常
に大きくなる。なお、下層配線へのコンタクトホールを
下層配線が若干残るように行うことにより、接続用金属
の下面でも接触し、コンタクトホールの側面積の分だけ
接触面積が増えることになる。しかも、コンタクトホー
ルの側面には不純物も付着しにくく、一層接触不良が生
じにくくなり、微細化が進んでも接触部での抵抗の増大
や密着不良が生じる虞れがなくなる。。
According to the semiconductor device having the connection structure of the upper wiring and the lower wiring according to the present invention, the connecting metal for connecting the two is deposited and provided in the contact hole provided in the lower wiring. Therefore, the contact area between the lower wiring and the connecting metal is significantly increased. That is, in the conventional method in which the contact is made only by being deposited on the lower wiring, the contact is made only with the thickness (cross-sectional area) of the connecting metal. Then
πr 2 . On the other hand, according to the present invention, for example, if a contact hole is formed for the entire thickness of the lower wiring,
The contact area is 2πr, where t is the thickness of the lower wiring.
t, and the area ratio is 2πrt / πr 2 = 2t / r
Becomes Therefore, as the connection metal (diameter of the contact hole) becomes thinner, the effect becomes larger. If the thickness of the connection metal is 2r = 0.18 μm and the thickness of the lower wiring is 1 μm, for example, the contact The area is as large as 22 times. By making a contact hole to the lower layer wiring so that the lower layer wiring remains slightly, the lower surface of the connection metal is also contacted, and the contact area is increased by the side area of the contact hole. In addition, impurities do not easily adhere to the side surfaces of the contact holes, so that poor contact is less likely to occur. Even if the miniaturization is advanced, there is no possibility that the resistance at the contact portion or poor adhesion will occur. .
【0014】つぎに、図1に示される半導体装置の製法
について、図2の工程説明図を参照しながら説明をす
る。まず、図2(a)に示されるように、半導体基板1
上の絶縁膜2の上に下層配線用のたとえばAl金属をス
パッタリングにより1μm程度成膜する。そして、図示
しないレジスト膜を用いてパターニングすることによ
り、下層配線3のパターンを形成する。
Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to the process explanatory diagram of FIG. First, as shown in FIG.
On the upper insulating film 2, for example, Al metal for lower wiring is formed to a thickness of about 1 μm by sputtering. Then, a pattern of the lower wiring 3 is formed by patterning using a resist film (not shown).
【0015】つぎに、図2(b)に示されるように、C
VD法によりSiO2 を1μm程度堆積して層間絶縁膜
4を形成する。そしてその上にレジスト膜11を設け、
写真食刻法によりコンタクトホール形成場所に目抜き孔
11aを設ける。そして、図2(c)に示されるよう
に、この目抜き孔11aにより露出した層間絶縁膜4を
CF4 ガスなどの下でドライエッチングし、コンタクト
ホール4aを形成する。さらに、その層間絶縁膜4をマ
スクとして、コンタクトホール4aにより露出した下層
配線3をBCl3 ガスなどの下でドライエッチングをす
る。その結果、図2(d)に示されるように、下層配線
3もエッチングされてコンタクトホール4aが下層配線
3に達する程度にまで形成される。
Next, as shown in FIG.
SiO 2 is deposited to a thickness of about 1 μm by a VD method to form an interlayer insulating film 4. Then, a resist film 11 is provided thereon,
A perforation hole 11a is provided at a contact hole formation location by a photolithography method. Then, as shown in FIG. 2C, the interlayer insulating film 4 exposed by the hole 11a is dry-etched under a CF 4 gas or the like to form a contact hole 4a. Further, using the interlayer insulating film 4 as a mask, the lower wiring 3 exposed through the contact hole 4a is dry-etched under BCl 3 gas or the like. As a result, as shown in FIG. 2D, the lower wiring 3 is also etched, and the contact hole 4a is formed to such an extent as to reach the lower wiring 3.
【0016】ついで、Alを有機金属化したトリメチル
アルミニウムとして、反応炉内に入れ、熱CVDやプラ
ズマCVDなどのメタルCVD法により、Alを堆積す
る。このメタルCVD法によれば、スパッタリング法の
ようにコンタクトホール内に斜めから付着するのではな
く、コンタクトホールの真上から金属が堆積されるた
め、細くて深いコンタクトホールでもその中に充分に堆
積し、隙間なく埋め込まれる。そして、層間絶縁膜4上
にも堆積され、Al膜が全面に形成される。その後、前
述と同様に、その表面にレジスト膜を形成してパターニ
ングすることにより、図1に示されるような上層配線と
下層配線との接続構造を有する半導体装置が得られる。
Next, the aluminum is put into a reaction furnace as trimethylaluminum obtained by converting Al to an organic metal, and Al is deposited by a metal CVD method such as thermal CVD or plasma CVD. According to this metal CVD method, the metal is deposited directly above the contact hole instead of obliquely adhering to the inside of the contact hole unlike the sputtering method, so that even a thin and deep contact hole can be sufficiently deposited therein. And embedded without gaps. Then, it is also deposited on the interlayer insulating film 4, and an Al film is formed on the entire surface. Thereafter, a resist film is formed on the surface and patterned in the same manner as described above to obtain a semiconductor device having a connection structure between the upper wiring and the lower wiring as shown in FIG.
【0017】前述の例では、接続用金属5aおよび上層
配線5の堆積をメタルCVD法により行ったが、メタル
CVD法によればドライで隙間なく細いコンタクトホー
ル内に金属を埋め込むことができるため好ましいが、C
uなどの無電解メッキや電解メッキなどにより行って
も、同様に細くて深いコンタクトホール内に、充分に接
続用金属を埋め込むことができる。
In the above-described example, the connection metal 5a and the upper wiring 5 are deposited by the metal CVD method. However, the metal CVD method is preferable because the metal can be buried in a narrow contact hole with no dry space. But C
Even if it is performed by electroless plating or electrolytic plating of u or the like, the connection metal can be sufficiently buried in the narrow and deep contact hole.
【0018】さらに、前述の例では、接続用金属5aと
上層配線5とを同じ金属により一度に形成したが、異な
る金属で接続用金属5aをコンタクトホール4a内に形
成し、その後で所望の金属により上層配線5を形成する
こともできる。また、図1〜2に示される例では、下層
配線3へのコンタクトホール4aの形成が下層配線3の
厚さ全体に亘って貫通させているが、下側に下層配線が
僅かに残るようにコンタクトホール4aを形成してもよ
い。
Further, in the above-described example, the connection metal 5a and the upper wiring 5 are formed at the same time by the same metal. However, the connection metal 5a is formed in the contact hole 4a by a different metal, and then the desired metal is formed. Thereby, the upper layer wiring 5 can be formed. In the example shown in FIGS. 1 and 2, the formation of the contact hole 4 a in the lower wiring 3 is made to penetrate the entire thickness of the lower wiring 3, but the lower wiring is slightly left on the lower side. A contact hole 4a may be formed.
【0019】[0019]
【発明の効果】本発明によれば、一段と微細化が進む半
導体装置において、コンタクト部における接触面積を充
分に確保することができ、良好な密着力および低抵抗の
コンタクト特性が得られる。その結果、高密度で多層配
線化される半導体装置の信頼性を充分に向上させること
ができる。
According to the present invention, in a semiconductor device which is further miniaturized, a contact area at a contact portion can be sufficiently ensured, and good contact force and low-resistance contact characteristics can be obtained. As a result, it is possible to sufficiently improve the reliability of a semiconductor device having a high-density multilayer wiring.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明の半導体装置の一実施形態の上層配線と
下層配線との接続構造を示す断面説明図である。
FIG. 1 is an explanatory cross-sectional view showing a connection structure between an upper wiring and a lower wiring according to an embodiment of the semiconductor device of the present invention;
【図2】図1の構造の製造工程を示す断面説明図であ
る。
FIG. 2 is an explanatory sectional view showing a manufacturing process of the structure of FIG. 1;
【図3】従来の半導体装置の上層配線と下層配線との接
続構造を示す図である。
FIG. 3 is a diagram showing a connection structure between an upper wiring and a lower wiring of a conventional semiconductor device.
【符号の説明】[Explanation of symbols]
3 下層配線 4 層間絶縁膜 4a コンタクトホール 5 上層配線 5a 接続用金属 Reference Signs List 3 lower wiring 4 interlayer insulating film 4a contact hole 5 upper wiring 5a connection metal

Claims (3)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 半導体基板上に絶縁膜を介して設けられ
    る下層配線と、該下層配線上に設けられる層間絶縁膜
    と、該層間絶縁膜および前記下層配線に設けられるコン
    タクトホールと、該コンタクトホール内に埋め込まれ、
    前記下層配線のコンタクトホールにより露出する側壁に
    接触して設けられる接続用金属と、該接続用金属と電気
    的に接続して前記層間絶縁膜上に設けられる上層配線と
    からなる上層配線と下層配線との接続構造を有する半導
    体装置。
    A lower wiring provided on the semiconductor substrate via an insulating film; an interlayer insulating film provided on the lower wiring; a contact hole provided in the interlayer insulating film and the lower wiring; Embedded inside
    An upper wiring and a lower wiring composed of a connecting metal provided in contact with a side wall exposed by a contact hole of the lower wiring, and an upper wiring electrically connected to the connecting metal and provided on the interlayer insulating film. Semiconductor device having a connection structure with a semiconductor device
  2. 【請求項2】 半導体基板上に絶縁膜を介して下層配線
    を形成し、該下層配線上に層間絶縁膜を形成し、該層間
    絶縁膜にコンタクトホールを形成して該コンタクトホー
    ル内に前記下層配線と電気的に接続されるように接続用
    金属を埋め込み、該接続用金属と電気的に接続されるよ
    うに前記層間絶縁膜上に上層配線を形成する半導体装置
    の製法であって、前記層間絶縁膜にコンタクトホールを
    形成する際に、前記下層配線にもコンタクトホールを形
    成して該下層配線のコンタクトホール内に前記接続用金
    属を埋め込むことを特徴とする半導体装置の製法。
    2. A lower wiring is formed on a semiconductor substrate via an insulating film, an interlayer insulating film is formed on the lower wiring, a contact hole is formed in the interlayer insulating film, and the lower layer is formed in the contact hole. A method of manufacturing a semiconductor device, comprising: embedding a connection metal so as to be electrically connected to a wiring, and forming an upper wiring on the interlayer insulating film so as to be electrically connected to the connection metal, When forming a contact hole in an insulating film, a contact hole is also formed in the lower wiring, and the connection metal is buried in the contact hole of the lower wiring.
  3. 【請求項3】 前記接続用金属をメタルCVD法により
    形成する請求項2記載の半導体装置の製法。
    3. The method according to claim 2, wherein the connecting metal is formed by a metal CVD method.
JP5492298A 1998-03-06 1998-03-06 Semiconductor device and manufacture thereof Pending JPH11251433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5492298A JPH11251433A (en) 1998-03-06 1998-03-06 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5492298A JPH11251433A (en) 1998-03-06 1998-03-06 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH11251433A true JPH11251433A (en) 1999-09-17

Family

ID=12984121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5492298A Pending JPH11251433A (en) 1998-03-06 1998-03-06 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH11251433A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354637A (en) * 1998-06-11 1999-12-24 Oki Electric Ind Co Ltd Connection structure for wiring and formation of connection part of the wiring
JP2008053700A (en) * 2006-07-28 2008-03-06 Semiconductor Energy Lab Co Ltd Method of manufacturing display device
JP2009049078A (en) * 2007-08-15 2009-03-05 Elpida Memory Inc Method for manufacturing semiconductor device
JP2009520367A (en) * 2005-12-16 2009-05-21 フリースケール セミコンダクター インコーポレイテッド Transistor having buried contact and method for forming the same
WO2017072871A1 (en) * 2015-10-28 2017-05-04 オリンパス株式会社 Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354637A (en) * 1998-06-11 1999-12-24 Oki Electric Ind Co Ltd Connection structure for wiring and formation of connection part of the wiring
US7777337B2 (en) 1998-06-11 2010-08-17 Oki Semiconductor Co., Ltd. Semiconductor device having damascene interconnection structure that prevents void formation between interconnections
US8786087B2 (en) 1998-06-11 2014-07-22 Oki Semiconductor Co., Ltd. Semiconductor device having damascene interconnection structure that prevents void formation between interconnections having transparent dielectric substrate
JP2009520367A (en) * 2005-12-16 2009-05-21 フリースケール セミコンダクター インコーポレイテッド Transistor having buried contact and method for forming the same
US8633515B2 (en) 2005-12-16 2014-01-21 Freescale Semiconductor, Inc. Transistors with immersed contacts
JP2008053700A (en) * 2006-07-28 2008-03-06 Semiconductor Energy Lab Co Ltd Method of manufacturing display device
JP2009049078A (en) * 2007-08-15 2009-03-05 Elpida Memory Inc Method for manufacturing semiconductor device
WO2017072871A1 (en) * 2015-10-28 2017-05-04 オリンパス株式会社 Semiconductor device
US10665538B2 (en) 2015-10-28 2020-05-26 Olympus Corporation Semiconductor device

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