JPH0458185B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure.

In order to increase the degree of integration of semiconductor devices, it is necessary to perform multilayer wiring. In multilayer wiring, when connecting lower layer wiring to upper layer wiring through interlayer communication holes, it is necessary to form a thin metal layer as a barrier in order to increase the connection yield, or when the metals of the lower layer wiring and upper layer wiring are different. .

FIG. 1 is a cross-sectional view of an example of a conventional multilayer wiring semiconductor device.

An insulating film 2 is provided on a semiconductor substrate 1, and Si
A lower layer wiring 3 of Al containing is provided. An interlayer insulating film 4 is provided on the surface of the lower wiring 3, and an interlayer communication hole is formed in the interlayer insulating film 4, and then a barrier metal layer 5 of Ti or W and a wiring metal layer 6 of Al are sequentially deposited. The barrier metal layer 5 and the wiring metal layer 6 are photoetched to selectively remove the upper layer wiring 6 and the barrier metal layer 5 at the same time. In this way, the barrier metal layer 5 is always provided under the upper layer wiring 6.
In a semiconductor device having a certain structure, there was a problem in that the components of the barrier metal layer 5 and the upper wiring layer 6 were combined, leading to an increase in wiring resistance.

FIG. 2 is a sectional view of another example of a conventional semiconductor device.

This semiconductor device was devised to solve the problem of the increase in wiring resistance, and after depositing the barrier metal layer 5, the barrier metal layer 5 is left only in the interlayer communication hole and its vicinity, and then the upper layer wiring 6 was formed. In a semiconductor device having this structure, the only portion where the wiring resistance increases is the interlayer communication hole and its vicinity, so the problem of increased wiring resistance is solved.

However, a semiconductor device is manufactured in advance up to the step of forming the interlayer insulating film mentioned above, and only the steps from the step of forming the next interlayer communication hole to the step of forming the wiring pattern for the upper layer wiring system are changed to create a different circuit. When manufacturing a semiconductor device having this structure, the step of forming a pattern for the barrier metal layer is a step after the step of forming the interlayer insulating film, so the step of forming the barrier metal layer takes extra manufacturing time.
There was a drawback that it was difficult to complete the manufacturing steps after the step of forming interlayer communication holes in a short period of time (short delivery time).

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that simultaneously eliminates the above two drawbacks, solves the problem of increased wiring resistance in a multilayer wiring structure, and allows different circuit configurations to be created in a short period of time.

The present invention is characterized by a step of forming a lower layer wiring on an insulating film on a semiconductor substrate, and a step of depositing a plurality of barrier metal layer patterns on the upper surface of the lower layer wiring at predetermined intervals. , forming an interlayer insulating film on the entire surface to cover the entire top surfaces of all of the plurality of barrier metal layer patterns, and a central portion of only one barrier metal layer pattern selected from the plurality of barrier metal layer patterns. forming an opening in the interlayer insulating film to expose the selected barrier metal layer pattern; The method of manufacturing a semiconductor device includes the step of forming an upper layer wiring extending over the layer pattern via the interlayer insulating film.

Next, embodiments of the present invention will be described using the drawings.

FIGS. 3a to 3c are cross-sectional views showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 3a, an insulating film 2 is provided on a semiconductor substrate 1, and a lower layer wiring 3 is formed thereon. Next, a barrier metal is deposited on the entire surface and selectively etched to selectively form barrier metal layers 5a, 5b, and 5c. Barrier metal layers 5a, 5b, 5c
are provided only in areas where there is a possibility of forming interlayer communication holes in a later process. Next, an interlayer insulating film 4 is deposited on the entire surface. The interlayer insulating film 4 is formed by, for example, plasma CVD.
It is formed by depositing an oxide film using a method.

Next, as shown in FIG. 3b, when creating a specified circuit (this will be named circuit A), the interlayer insulating film 4 on the barrier metal layer 5a is selectively removed to form an opening. .

Next, as shown in FIG. 3c, a barrier metal layer 5a is formed on the interlayer insulating film 4 and through the interlayer communication hole.
Upper layer wiring 6 is formed so as to be connected to. In this way, one embodiment of the semiconductor device of the present invention is manufactured.

In this example, as a certain specified circuit, A
Although the case of configuring a circuit has been described, there are cases where it is possible to create another circuit (this will be named circuit B) using the intermediate step shown in FIG. 3a. In such a case, as shown in FIG. 4a, the interlayer insulating film 4 on the barrier metal layer 5b is selectively removed to form an interlayer communication hole, and then the upper layer wiring 6 is removed as shown in FIG. 4b. form.

In this way, by selectively forming a barrier metal layer on the lower layer wiring in a region where there is a possibility of forming an interlayer communication hole, not only the problem of increased wiring resistance but also the problem of increased wiring resistance can be solved in a short period of time. However, the effect can be obtained that it can be configured even with a B circuit.

As explained in detail above, according to the present invention,
This is highly effective because it prevents an increase in wiring resistance and allows semiconductor devices with different circuit configurations to be manufactured in a short period of time.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an example of a conventional semiconductor device, FIG. 2 is a sectional view of another example of a conventional semiconductor device, and FIG. 3 is a sectional view of another example of a conventional semiconductor device.
Figures a to c are cross-sectional views shown in the order of steps for explaining the manufacturing method of one embodiment of the present invention, and Figures 4a and b are sectional views shown in the order of steps for explaining the manufacturing method of another embodiment of the present invention. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Lower layer wiring, 4... Interlayer insulating film, 5, 5a, 5b, 5c
... Barrier metal layer, 6 ... Upper layer wiring.

Claims (1)

[Claims] 1. A step of forming a lower layer wiring on an insulating film on a semiconductor substrate, a step of depositing a plurality of barrier metal layer patterns on the upper surface of the lower layer wiring at predetermined intervals, and a step of forming interlayer insulation on the entire surface. forming a film to cover the entire upper surfaces of all of the plurality of barrier metal layer patterns, and exposing only a central portion of one barrier metal layer pattern selected from the plurality of barrier metal layer patterns; forming an opening in the interlayer insulating film, depositing the film onto the center of the selected barrier metal layer pattern through the opening, and depositing the film onto the other barrier metal layer pattern among the plurality of barrier metal layer patterns; 1. A method of manufacturing a semiconductor device, comprising the step of forming an upper layer wiring extending through an interlayer insulating film.