JPS6025252A - Semiconductor device - Google Patents

Abstract

PURPOSE:To solve the problem of the increase, etc. of wiring resistance in multilayer wiring structure, and to form different circuit constitution in a short period by selectively forming a barrier metal layer on a lower layer wiring in a region in which there is possibility forming an inter-layer communicating hole. CONSTITUTION:An insulating film 2 is formed on a semiconductor substrate 1, and a lower layer wiring 3 is shaped on the insulating film. The whole surface is coated with a barrier metal, and barrier metal layers 5a, 5b, 5c are formed selectively through selective etching. The whole surface is coated with an inter- layer insulating film 4. For prepare some designated circuit, an opening is formed on the barrier metal layer 5a by selectively removing the inter-layer insulating film 4. An upper layer wiring 6 is shaped so as to be connected to the barrier metal layer 5a through an inter-layer communicating hole.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having multiple interconnects.

In order to integrate semiconductor devices, it is necessary to perform multilayer wiring. In multilayer wiring, lower layer wiring? Interlayer communication hole? When connecting to upper layer wiring through
Or if the metals of the lower and upper wiring are different, a thin metal layer as a barrier? need to be formed.

FIG. 1 is a cross-sectional view of an example of a conventional multilayer wiring semiconductor device.

An insulating film 27 is provided on a semiconductor substrate l, and a lower layer wiring 3 is provided on it.
Fully provided. After the interlayer insulating film 4 is completely formed on the bottom surface and the interlayer communication hole is opened, a barrier metal layer 5. A wiring metal layer 6t is deposited and photoetching is performed to selectively remove the upper wiring 6 and the barrier metal layer 5 at the same time.

In this way, in a semiconductor device with a structure in which there is always a barrier metal layer under the upper layer wiring, the barrier metal layer and the upper layer wiring combine, resulting in an increase in wiring resistance. There was the problem of inviting.

FIG. 2 is a cross-sectional view of another example of a conventional multi-no wiring semiconductor device.

This semiconductor device was devised to solve all of the above problems, so the barina metal layer 5? After deposition, the barrier metal layer 5 is left only in the interlayer communication hole and its vicinity.1. Thereafter, lower layer wiring 6 was formed.

In a semiconductor device with this structure, the problem of increased wiring resistance is solved, but in a semiconductor device in which only the pattern of the upper layer wiring system is changed from the step of forming interlayer communication holes to the gold, and a different circuit configuration is implemented, Barrier metal layer pattern? Since the process of drawing the form involves a circuit borrowing process, does it take extra time to configure the circuit, which is a hindrance to completing the complete circuit configuration in a short period of time? There was a drawback that it was too late.

An object of the present invention is to provide an entire semiconductor device that eliminates all of the above-mentioned drawbacks, solves all problems such as increased wiring resistance in a multilayer wiring structure, and allows different circuit configurations to be made in a short period of time.

In the semiconductor device of the present invention, a lower layer wiring provided on an insulating film formed on a semiconductor substrate, and a plurality of lower layer wirings made of different metals from different metals are selectively provided on the lower layer wiring. 'fc metal layer, an interlayer insulating film that covers the metal layer and the lower halo wiring, and a portion of the interlayer insulating layer on at least one metal layer of the plurality of metal layers is selectively removed and provided. an interlayer communication hole provided on the interlayer insulating layer; and an interlayer communication hole provided on the interlayer insulating layer. Of course, it also includes an upper layer wiring that connects to the metal layer through the metal layer.

Next, embodiments of the present invention will be described using the drawings.

FIGS. 3(a) to 3(C) are cross-sectional views shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 3 (aJ), the insulating film 2 is entirely provided on the semiconductor substrate 1, and the lower layer wiring 3 is formed thereon.Next,
Barrier metal is fully deposited on the entire surface and selectively etched to selectively form all four barrier layers 5a, 5b, and 5ck. Barrier metal layers 5a, 5b, and 5c are provided only in regions where interlayer communication holes may be formed in a subsequent process. Next, the interlayer insulating film 4 is deposited on the entire surface. The interlayer insulating film 4 is formed by, for example, plasma CV.
Oxide film using D method? Polymers are formed by adhesion.

Next, as shown in FIG. 3(b), when creating a certain designated companion circuit (named iA circuit), the glabella insulating film 4 on the barrier metal layer 5a? Selectively remove and open? establish.

Next, as shown in FIG. 3C, an upper layer wiring 6 tray is formed on the interlayer insulating layer 4 and connected to the barrier metal layer 5a through the interlayer communication hole. In this way, one embodiment of the semiconductor device of the present invention is manufactured.

In this embodiment, a case where the whole circuit is configured as a certain specified circuit has been explained, but a separate circuit (this is named Gold B circuit) is created by using all the intermediate steps shown in Fig. 3(a). ) may be able to make all. In such a case, as shown in FIG. 4(a), the interlayer insulating film 4 on the barrier metal layer 5b is selectively removed to open the interlayer communication hole, and then as shown in FIG. 4(b), the interlayer insulating film 4 is selectively removed. Then, six upper layer wirings are formed.

In this way, by selectively forming the barrier metal layer on all the lower layer wiring in areas where there is a possibility of forming all the interlayer communication holes, not only the problem of increased wiring resistance but also the problem of increasing circuit resistance in a short period of time can be solved. The advantage is that it can also be configured with a circuit.

As described in detail above, the present invention has great effects because it is possible to completely prevent an increase in wiring resistance and to produce a semiconductor device with a different circuit configuration in a short period of time.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an example of a conventional semiconductor device, FIG. 2 is a sectional view of another example of a conventional semiconductor device, and FIGS.
) is a round sectional view showing the steps in order to explain the manufacturing method of one embodiment of the present invention, and FIGS. 4(a) and 4(b) are steps for explaining the manufacturing method of another embodiment of the present invention. It is sectional drawing shown in order. 1... Semiconductor substrate, 2... Insulating film, 3
...Lower wiring, 4...Interlayer insulating film, 5
．． 5a, 5b, 5c...barrier metal layer, 6...
...Upper layer wiring. /, -r dimension, ~ Agent Patent Attorney Uchihara Item 1,

Claims (1)

[Claims] A lower wiring provided on an insulating film formed on a semiconductor substrate, a metal layer of a different kind from the lower wiring material, and a plurality of metal layers selectively provided on the lower J-wiring; J-
and the lower wiring, the interlayer insulating film covering gold, and the interlayer insulating layer portion on at least one remaining layer of the compound metal layer? An interlayer communication hole provided by selective removal, and an upper layer wiring provided on the interlayer insulating layer and connected to the metal layer through the entire front interlayer communication hole? A semiconductor device having all the characteristics including: