JPH01194334A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH01194334A JPH01194334A JP1941088A JP1941088A JPH01194334A JP H01194334 A JPH01194334 A JP H01194334A JP 1941088 A JP1941088 A JP 1941088A JP 1941088 A JP1941088 A JP 1941088A JP H01194334 A JPH01194334 A JP H01194334A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- opening
- layer
- film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000010410 layer Substances 0.000 claims abstract description 54
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の製造方法に関し、特に多層配
線を有する半導体集積回路の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit having multilayer wiring.
半導体集積回路の高集積化のために多層配線技術が採用
されている。Multilayer wiring technology has been adopted to increase the degree of integration of semiconductor integrated circuits.
第３図は従来の半導体集積回路の一例を説明するための
半導体チップの断面図である。FIG. 3 is a cross-sectional view of a semiconductor chip for explaining an example of a conventional semiconductor integrated circuit.
図において、半導体基板１の上に設けた絶縁膜２の上に
第１の配線３を設ける。次に、配線３を含む表面に層間
絶縁膜４を堆積し、配線３の上の層間絶縁膜４にコンタ
クト用開口部を設ける。次に、前記開口部を含む表面に
配線材層を堆積し、これを選択的にエツチングして配線
３と接続する澗２の配線５を形成する。以下、同様にし
て、配線５を含む表面に層間絶縁膜１１を堆積し、配線
５の上の層間絶縁膜１２に選択的にコンタクト用の開口
部を設け、該開口部を含む表面に配線材層を堆積し、こ
れを選択的にエツチングし−て配線５と接続する第３の
配線１３を形成する。In the figure, a first wiring 3 is provided on an insulating film 2 provided on a semiconductor substrate 1. Next, an interlayer insulating film 4 is deposited on the surface including the wiring 3, and a contact opening is provided in the interlayer insulating film 4 above the wiring 3. Next, a wiring material layer is deposited on the surface including the opening and selectively etched to form a square 2 wiring 5 to be connected to the wiring 3. Thereafter, in the same manner, an interlayer insulating film 11 is deposited on the surface including the wiring 5, an opening for contact is selectively provided in the interlayer insulating film 12 above the wiring 5, and a wiring material is deposited on the surface including the opening. A layer is deposited and selectively etched to form a third interconnect 13 that connects to interconnect 5.
上述した従来の半導体集積回路は、コンタクト用開口部
内における上層配線の段差被覆性が悪く、断線を引き起
こしやすい、特に集積度の上昇とともに開口部が小さく
、且つ、その側壁が急峻になるため、断線を生じ易くな
るという問題点がある。In the conventional semiconductor integrated circuit described above, the step coverage of the upper layer wiring within the contact opening is poor, and wire breakage is likely to occur.In particular, as the degree of integration increases, the opening becomes smaller and its sidewalls become steeper, so wire breakage occurs. There is a problem in that it is more likely to occur.
また、下層配線に対して層間絶縁膜のコンタクト用開口
部の形成と上層配線のバターニングを異なるリソグラフ
ィ工程で行なうため、位置合わせの余裕を大きくとる必
要があり、配線ピッチの縮小が難しいという問題点があ
る。In addition, since the formation of contact openings in the interlayer insulating film for the lower layer wiring and the patterning of the upper layer wiring are performed in different lithography processes, it is necessary to have a large margin for alignment, making it difficult to reduce the wiring pitch. There is a point.
〔問題点を解決するための手段〕
本発明の半導体集積回路の製造方法は、半導体基板上に
設けた絶縁膜上に第１の配線を設け該第１の配線を含む
表面に層間絶縁膜を形成する工程と、前記層間絶縁膜上
に配線材層を堆積し該配線材層上に第１のホトレジスト
膜を設けてバターニングする工程と、前記第１のホトレ
ジスト膜をマスクとして前記配線材層をエツチングして
除去し前記第１の配線とのコンタクト用開口部を有する
第２の配線を設ける工程と、前記開口部近傍以外の表面
を被覆する第２のホトレジスト膜を選択的に設け前記第
１及び第２のホトレジスト膜をマスクとして前記層間絶
縁膜をエツチングしてコンタクト用開口部を設ける工程
と、前記開口部を含む表面に導電体層を堆積して前記開
口部内の前記第２の配線の上面まで充填する工程と、リ
フトオフ法により前記第１及び第２のホトレジスト膜と
前記開口部内以外の前記導電体層を除去して前記第１の
配線と第２の配線とを前記開口部内で接続する工程とを
含んで構成される。[Means for Solving the Problems] The method for manufacturing a semiconductor integrated circuit of the present invention includes providing a first wiring on an insulating film provided on a semiconductor substrate and forming an interlayer insulating film on the surface including the first wiring. a step of depositing a wiring material layer on the interlayer insulating film, providing a first photoresist film on the wiring material layer and patterning the wiring material layer, and using the first photoresist film as a mask to deposit the wiring material layer. a step of etching and removing the first wiring to provide a second wiring having an opening for contact with the first wiring, and selectively providing a second photoresist film covering the surface other than the vicinity of the opening. etching the interlayer insulating film using the first and second photoresist films as masks to form a contact opening, and depositing a conductor layer on the surface including the opening to form the second wiring in the opening. filling up to the upper surface, and removing the first and second photoresist films and the conductive layer except in the opening by a lift-off method to connect the first wiring and the second wiring within the opening. and a connecting step.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
まず、第１図（ａ）に示すように、半導体基板１の上に
設けた絶縁膜２の上に第１の配線３（紙面に垂直方向に
延在している）を設け、配線３を含む表面にプラズマＣ
ＶＤ法により層間絶縁膜４を堆積する０次に、層間絶縁
膜４の上にスパッタリング法により配線材層を堆積し、
前記配線材層の上に第１のホトレジスト膜６を塗布して
バターニングする０次に、ホトレジスト膜６をマスクと
して前記配線材層をエツチングして除去し、配線３と整
合するコンタクト用開口部７を有する配線５を形成する
０次に、１５０℃１時間の熱処理によりホトレジスト膜
６を硬化させる。First, as shown in FIG. 1(a), a first wiring 3 (extending in a direction perpendicular to the plane of the paper) is provided on an insulating film 2 provided on a semiconductor substrate 1. Plasma C on surfaces containing
Depositing the interlayer insulating film 4 by the VD method Next, depositing a wiring material layer on the interlayer insulating film 4 by the sputtering method,
A first photoresist film 6 is applied on the wiring material layer and patterned.Next, the wiring material layer is etched and removed using the photoresist film 6 as a mask to form a contact opening aligned with the wiring 3. Next, the photoresist film 6 is hardened by heat treatment at 150° C. for 1 hour.
次に、第１図（ｂ）に示すように、ホトレジスト膜６の
上に第２のホトレジスト膜８を塗布してバターニングし
、開口部７の近傍のみを開口し、他の部分を被覆する。Next, as shown in FIG. 1(b), a second photoresist film 8 is coated on the photoresist film 6 and buttered to open only the vicinity of the opening 7 and cover the other parts. .
ここで、ホトレジスト膜８のバターニングを行うための
現像処理では、熱処理で硬化されたホトレジスト膜６は
除去されることはなく、ホトレジスト１１Ａ８の開口部
の位置合わせ精度もいくらか低くできる利点がある。次
に、ホトレジスト６．８をマスクとして層間絶縁膜４を
反応性イオンエツチング等の異方性エツチング法により
除去し、コンタクト用開口部を設ける。Here, in the development treatment for patterning the photoresist film 8, the photoresist film 6 hardened by heat treatment is not removed, and there is an advantage that the positioning accuracy of the opening of the photoresist 11A8 can be somewhat lowered. Next, using the photoresist 6.8 as a mask, the interlayer insulating film 4 is removed by an anisotropic etching method such as reactive ion etching to provide a contact opening.
次に、第１図（ｃ）に示すように、開口部７を含む表面
にアルミニウム等の導電体層９を真空蒸着法等の方向性
の強い被着法で堆積し、開口部７の配線５の上面まで導
電体層９を充填する。Next, as shown in FIG. 1(c), a conductive layer 9 of aluminum or the like is deposited on the surface including the opening 7 by a highly directional deposition method such as vacuum evaporation, and the wiring of the opening 7 is deposited. The conductor layer 9 is filled up to the upper surface of the conductor layer 5.
次に、第１図（ｄ）に示すように、リフトオフ法により
ホトレジスト！１１６，８及びホトレジスト膜６．８の
上の導電体層９を同時に除去し、配線３と接続された配
線５を形成する。Next, as shown in FIG. 1(d), photoresist is applied using the lift-off method. 116, 8 and the conductor layer 9 on the photoresist film 6.8 are removed at the same time to form a wiring 5 connected to the wiring 3.
第２図は本発明の第２の実施例を説明するための半導体
チップの断面図である。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
図に示すように、第１の実施例の第１図（ａ）（ｂ）の
工程の後、開口部７を含む表面にＰｄ層１０を薄く堆積
し、リフトオフ法によりホトレジスト膜６，８及びＰｄ
層１０を除去する０次に開口部７の底部に残したＰｄ層
１０の上に無電解めっき法によりＮｉ層１１を堆積し、
開口部７に埋込む。第２の実施例では、開口面積に対す
る深さの比の大きい開口部にも導電体層を容易に埋込む
ことができるめ、配線の高密度化がより実現し易いとい
う利点がある。As shown in the figure, after the steps shown in FIGS. 1(a) and 1(b) of the first embodiment, a thin Pd layer 10 is deposited on the surface including the opening 7, and the photoresist films 6, 8 and Pd
After removing the layer 10, a Ni layer 11 is deposited by electroless plating on the Pd layer 10 left at the bottom of the opening 7.
Embed in the opening 7. The second embodiment has the advantage that the conductor layer can be easily embedded even in an opening having a large ratio of depth to opening area, so that it is easier to realize higher wiring density.
以上説明したように本発明は、下層配線上に層間絶縁膜
と配線材層を順次堆積し、配線材層をパターニングして
上層配線を形成すると同時に下層配線とのコンタクト用
開口部を上層配線の一部に設け、この開口部をマスクと
して層間絶縁膜に開口部を設け、この開口部内に導電体
層を充填して下層配線と上層配線を接続することにより
、開口部の形成と上層配線のパターニングを１回のリン
グラフィ工程で処理でき、位置合せの余裕を縮減できる
という効果を有する。As explained above, in the present invention, an interlayer insulating film and a wiring material layer are sequentially deposited on a lower layer wiring, the wiring material layer is patterned to form an upper layer wiring, and at the same time, an opening for contact with the lower layer wiring is formed in the upper layer wiring. By forming an opening in the interlayer insulating film using this opening as a mask, and filling this opening with a conductive layer to connect the lower layer wiring and the upper layer wiring, the opening can be formed and the upper layer wiring can be connected. This has the effect that patterning can be performed in one phosphorography process and that margins for alignment can be reduced.
また、開口部内に導電体層を埋込むことにより、上層配
線のコンタクト用開口部での段差被覆性を改善し、断線
事故を低減できるという効果を有する。Further, by embedding the conductor layer in the opening, it is possible to improve the step coverage of the contact opening of the upper layer wiring and reduce disconnection accidents.
第１図（ａ）〜（ｄ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図、第２図
は本発明の第２の実施例を説明するための半導体チップ
の断面図、第３図は従来の半導体集積回路の一例を説明
するための半導体チップの断面図である。
１・・・半導体基板、２・・・絶縁膜、３・・・配線、
４・・・層間絶縁膜、５・・・配線、６・・・ホトレジ
スト膜、７・・・開口部、８・・・ホトレジスト膜、９
・・・導電体層、１０・・・Ｐｄ層、１１・・・Ｎｉ層
、１２・・・層間絶縁膜、１３・・・配線。FIGS. 1(a) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a second embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor chip for explaining an example of a conventional semiconductor integrated circuit. 1... Semiconductor substrate, 2... Insulating film, 3... Wiring,
4... Interlayer insulating film, 5... Wiring, 6... Photoresist film, 7... Opening, 8... Photoresist film, 9
... Conductor layer, 10... Pd layer, 11... Ni layer, 12... Interlayer insulating film, 13... Wiring.
Claims (1)
第１の配線を含む表面に層間絶縁膜を形成する工程と、
前記層間絶縁膜上に配線材層を堆積し該配線材層上に第
１のホトレジスト膜を設けてパターニングする工程と、
前記第１のホトレジスト膜をマスクとして前記配線材層
をエッチングして除去し前記第１の配線とのコンタクト
用開口部を有する第２の配線を設ける工程と、前記開口
部近傍以外の表面を被覆する第２のホトレジスト膜を選
択的に設け前記第１及び第２のホトレジスト膜をマスク
として前記層間絶縁膜をエッチングしてコンタクト用開
口部を設ける工程と、前記開口部を含む表面に導電体層
を堆積して前記開口部内の前記第２の配線の上面まで充
填する工程と、リフトオフ法により前記第１及び第２の
ホトレジスト膜と前記開口部内以外の前記導電体層を除
去して前記第１の配線と第２の配線とを前記開口部内で
接続する工程とを含むことを特徴とする半導体集積回路
の製造方法。a step of providing a first wiring on an insulating film provided on a semiconductor substrate and forming an interlayer insulating film on a surface including the first wiring;
depositing a wiring material layer on the interlayer insulating film, and providing and patterning a first photoresist film on the wiring material layer;
etching and removing the wiring material layer using the first photoresist film as a mask to provide a second wiring having an opening for contact with the first wiring; and covering the surface other than the vicinity of the opening. selectively forming a second photoresist film to form a contact opening by etching the interlayer insulating film using the first and second photoresist films as masks; and forming a conductive layer on the surface including the opening. depositing the first and second photoresist films and the conductor layer outside the opening by a lift-off method to fill the upper surface of the second wiring in the opening; A method of manufacturing a semiconductor integrated circuit, comprising the step of connecting the wiring and the second wiring within the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1941088A JPH01194334A (en) | 1988-01-28 | 1988-01-28 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1941088A JPH01194334A (en) | 1988-01-28 | 1988-01-28 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01194334A true JPH01194334A (en) | 1989-08-04 |
Family
ID=11998483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1941088A Pending JPH01194334A (en) | 1988-01-28 | 1988-01-28 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01194334A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5798299A (en) * | 1994-05-09 | 1998-08-25 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694353A (en) * | 1979-12-28 | 1981-07-30 | Fujitsu Ltd | Micropattern forming method |
| JPS58158947A (en) * | 1982-03-16 | 1983-09-21 | Seiko Epson Corp | Manufacture of semiconductor device |
-
1988
- 1988-01-28 JP JP1941088A patent/JPH01194334A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694353A (en) * | 1979-12-28 | 1981-07-30 | Fujitsu Ltd | Micropattern forming method |
| JPS58158947A (en) * | 1982-03-16 | 1983-09-21 | Seiko Epson Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5798299A (en) * | 1994-05-09 | 1998-08-25 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
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