CN114823774A - Superconducting circuit, qubit device and method of making the same - Google Patents
Superconducting circuit, qubit device and method of making the same Download PDFInfo
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Abstract
The application discloses a superconducting circuit, a quantum bit device and a preparation method thereof, and belongs to the technical field of quantum chip preparation. The superconducting circuit includes: a structure to be connected; an extraction structure electrically connected to the superconducting layer of the Josephson junction; and the transition structure covers part of the structure to be connected and part of the lead-out structure so as to realize electric connection. A method of making the superconducting circuit is also disclosed. The superconducting circuit and the method for manufacturing the same enable good electrical contact between the Josephson junction and the structure to be connected (e.g., capacitance to ground, ground plane (GND)). Therefore, the problem that the performance parameters of the superconducting quantum chip are influenced due to poor electrical contact between the Josephson junction prepared by the relevant process and the connection structure of the capacitance to ground and the ground layer (GND) waiting is solved.
Description
Technical Field
The application belongs to the technical field of quantum chip preparation, and particularly relates to a superconducting circuit, a quantum bit device and a preparation method thereof.
Background
Quantum computation is an important field which has been widely paid attention to in China, and a superconducting qubit system based on a josephson junction is considered to be one of the most promising systems for realizing quantum computation due to the advantages of good expandability, high fidelity of door operation and the like. As a key element of a superconducting quantum chip, a josephson junction is a structure composed of three thin films, i.e., S (superconductor) -I (semiconductor or insulator) -S (superconductor), including two layers of superconducting metal, such as niobium film or aluminum film, with a barrier layer (usually a very thin oxide film) sandwiched therebetween. In a superconducting qubit system, a qubit device includes a capacitance to ground, a closed loop device connected in parallel with the capacitance, and a control signal line, the closed loop device being formed by connecting josephson junctions in parallel, e.g., two josephson junctions in parallel.
A process for preparing the superconductive quantum chip includes such steps as forming a superconductive metal layer on substrate, patterning it to obtain the pattern structure of grounding layer (GND) and capacitance to ground, exposing the preparing region for preparing the Josephson junction, coating photoresist on substrate, exposing and developing to form a mask pattern with window, and evaporating, oxidizing and evaporating the exposed region to obtain the Josephson junction. However, the josephson junction prepared by the related process is in poor electrical contact with a ground capacitor and a ground plane (GND) waiting connection structure, thereby affecting the performance parameters of the superconducting quantum chip, such as coherence time.
Disclosure of Invention
An object of the present application is to provide a superconducting circuit, a quantum bit device and a method of manufacturing the same, which can achieve a good electrical contact between a josephson junction and a structure to be connected (e.g., a capacitance to ground, a ground plane (GND)) to solve the disadvantages of the prior art.
An aspect of the present application provides a superconducting circuit including: a structure to be connected; an extraction structure electrically connected to the superconducting layer of the Josephson junction; and the transition structure covers part of the structure to be connected and part of the lead-out structure so as to realize electric connection.
Another aspect of the present application provides a qubit device comprising a ground layer, a capacitance-to-ground plate, and at least one josephson junction, the qubit device further comprising: a bottom layer lead-out structure electrically connected with the bottom super conducting layer of the Josephson junction, and a top layer lead-out structure electrically connected with the top super conducting layer of the Josephson junction; and the first transition structure covers part of the bottom layer lead-out structure and part of the ground capacitor plate, and the second transition structure covers part of the top layer lead-out structure and part of the ground layer so as to respectively realize electrical connection.
A third aspect of the present application provides a method of manufacturing a superconducting circuit, including: forming a photoresist layer to cover the structure to be connected and a first region where a lead-out structure electrically connected with the superconducting layer of the Josephson junction is to be located; patterning the photoresist layer to obtain a deposition window, wherein the deposition window comprises a first window exposing the first area and a second window exposing the second area, and the second area comprises a part of the first area and a third area positioned on the surface of the structure to be connected; sequentially utilizing the first window and the second window for directional deposition to respectively form the leading-out structure positioned in the first area and a transition structure covering the second area and part of the leading-out structure; and removing the photoresist layer to obtain the superconducting circuit.
A fourth aspect of the present application provides a method of manufacturing a qubit device comprising a ground layer, a capacitance-to-ground plate, and at least one josephson junction, the method comprising:
providing a substrate, wherein the grounding layer and the ground capacitor plate are formed on the substrate;
determining a junction preparation region on the substrate, the junction preparation region comprising a first deposition region and a second deposition region intersecting, wherein the first deposition region is used for preparing a bottom superconductive layer of the Josephson junction and a bottom layer extraction structure electrically connected with the bottom superconductive layer, and the second deposition region is used for preparing a top superconductive layer of the Josephson junction and a top layer extraction structure electrically connected with the top superconductive layer;
forming a photoresist layer to cover the junction preparation area, and the ground layer and the capacitance-to-ground plate;
patterning the photoresist layer to obtain a deposition window, the deposition window including a junction region window exposing the junction preparation region, a first transition window exposing a first transition region, and a second transition window exposing a second transition region, the first transition region including an area of a portion of the surface of the capacitor-to-ground plane and a portion of the first deposition region, the second transition region including an area of a portion of the surface of the ground plane and a portion of the second deposition region;
directionally depositing with the junction region window to form a Josephson junction, the bottom lead structure and the top lead structure; and
and utilizing the first transition window and the second transition window to perform directional deposition to form a first transition structure covering part of the bottom layer lead-out structure and part of the grounding capacitor plate and a second transition structure covering part of the top layer lead-out structure and part of the grounding layer so as to respectively realize electrical connection.
Compared with the prior art, the superconducting circuit provided by the first aspect of the application realizes the electrical connection between the superconducting layer of the Josephson junction and the structure to be connected through the lead-out structure electrically connected with the superconducting layer of the Josephson junction and the transition structure covering part of the structure to be connected and part of the lead-out structure, and has good electrical contact performance.
Compared with the prior art, the qubit device provided by the second aspect of the present application realizes the electrical connection of the bottom super-conductive layer and the ground capacitor plate of the josephson junction through the bottom layer lead-out structure electrically connected with the bottom super-conductive layer of the josephson junction and the first transition structure covering part of the bottom layer lead-out structure and part of the ground capacitor plate, and realizes the electrical connection of the top super-conductive layer and the ground layer through the top layer lead-out structure electrically connected with the top super-conductive layer of the josephson junction and the second transition structure covering part of the top layer lead-out structure and part of the ground layer, so that the josephson junction and the ground capacitor plate and the ground layer have good electrical contact performance.
Compared with the prior art, the method for preparing the superconducting circuit provided by the third aspect of the application comprises the steps of firstly forming a photoresist layer to cover a structure to be connected and a first region where a lead-out structure electrically connected with a superconducting layer of a Josephson junction is to be located; then, patterning the photoresist layer to obtain a deposition window, wherein the deposition window comprises a first window exposing the first area and a second window exposing a second area, and the second area comprises a part of the first area and a third area positioned on the surface of the connecting structure; then, the first window and the second window are sequentially utilized for directional deposition to respectively form the leading-out structure positioned in the first area and a transition structure covering the second area and part of the leading-out structure; and finally, removing the photoresist layer to obtain the superconducting circuit, thereby realizing the electric connection of the superconducting layer of the Josephson junction and the structure to be connected, having good electric contact performance, and completing the leading-out structure of the Josephson junction and the preparation of the superconducting circuit for connecting the leading-out structure and the structure to be connected by utilizing a mask pattern formed by one-time gluing, exposure and development.
Compared with the prior art, the method for manufacturing the qubit device provided by the fourth aspect of the present application comprises the steps of determining a junction preparation area comprising a first deposition area and a second deposition area which are intersected on a substrate, and then forming a photoresist layer to cover the junction preparation area, a grounding layer and a capacitance-to-ground plate on the substrate; then patterning the photoresist layer to obtain a deposition window including a junction region window exposing the junction preparation region, a first transition window exposing a first transition region including an area of a portion of the surface of the capacitor-to-ground plane and a portion of the first deposition region, and a second transition window exposing a second transition region including an area of a portion of the surface of the ground plane and a portion of the second deposition region; then, directionally depositing by using the junction region window to form a Josephson junction, the bottom layer lead-out structure and the top layer lead-out structure; and then, utilizing the first transition window and the second transition window to perform directional deposition to form a first transition structure covering a part of the bottom layer lead-out structure and a part of the grounding capacitor plate, and a second transition structure covering a part of the top layer lead-out structure and a part of the grounding layer to respectively realize electric connection, and removing the photoresist layer to obtain the qubit device, wherein the Josephson junction, the capacitance plate to ground and the grounding layer in the qubit device have good electric contact performance, and the Josephson junction, the superconducting circuit connecting the Josephson junction and the capacitance plate to ground and the superconducting circuit connecting the Josephson junction and the grounding layer can be prepared by utilizing a mask pattern formed by one-time gluing, exposing and developing.
Drawings
Fig. 1 is a schematic structural diagram of a device for manufacturing a quantum chip according to an embodiment of the present disclosure, where fig. 1(2) is an enlarged schematic diagram of a region M in fig. 1 (1);
fig. 2 is a schematic structural diagram of a josephson junction device according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a quantum chip according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural view of the superconducting circuit 41 in fig. 3, in which fig. 4(2) is a sectional view of Aa of fig. 4 (1);
fig. 5 is a schematic structural view of the superconducting circuit 42 of fig. 3, wherein fig. 5(2) is a cross-sectional view of Bb of fig. 5 (1);
fig. 6 is a flowchart of a method for manufacturing a superconducting circuit according to an embodiment of the present disclosure;
FIG. 7 is a flowchart illustrating a method for fabricating a qubit device according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram illustrating a process for manufacturing a quantum chip according to an embodiment of the present disclosure;
fig. 9 is a schematic view of a deposition window provided in the present embodiment, wherein fig. 9(2) is a schematic view of a Dd cross section in fig. 9(1), and fig. 9(3) is a schematic view of an Ee cross section in fig. 9 (1).
Description of reference numerals: 1-substrate, 11-junction preparation region, 111-first deposition region, 112-second deposition region, 2-superconducting metal layer, 21-ground layer, 22-capacitance-to-ground plate, 3-josephson junction device, 31-bottom layer lead-out structure, 32-barrier layer, 33-top layer lead-out structure, 34-josephson junction, 4-superconducting circuit, 41-first superconducting circuit, 411-first transition structure, 42-second superconducting circuit, 421-second transition structure, 5-photoresist layer, 51-junction window, 52-first transition window, 53-second transition window, 501-first photoresist layer, 502-second photoresist layer, 61-first extension direction, 62-second extension direction, 63-third extension direction, 64-fourth direction of extension.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to without contradiction.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In addition, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on the other layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
Fig. 1 is a schematic structural diagram of a device for manufacturing a quantum chip according to an embodiment of the present disclosure, where fig. 1(2) is an enlarged schematic diagram of a region M in fig. 1 (1).
Fig. 2 is a schematic structural diagram of a josephson junction device 3 according to an embodiment of the present disclosure.
In the related superconducting quantum chip fabrication process, as shown in fig. 1, first, a superconducting metal layer 2, such as an Al layer, an Nb layer, is formed on a substrate 1, and the superconducting metal layer is patterned to obtain a ground layer (GND)21, a capacitance-to-ground plate 22, a control signal line, and the like and expose a fabrication region M for fabricating a josephson junction, so as to obtain a device for fabricating a quantum chip. Then, a related process of manufacturing the josephson junction device 3 is performed on the manufacturing region M of the device, and exemplarily, the structure of the josephson junction device 3 is shown with reference to fig. 2.
It should be noted that fig. 1 schematically shows the position and shape configurations of components or structures located within the dashed boxes on the device for manufacturing the quantum chip, such as the ground layer 21, the capacitance-to-ground plate 22 and the manufacturing region M for manufacturing the josephson junction device 3, other components or structures are not or only partially shown, and components or structures other than the dashed boxes are omitted from fig. 1.
As an important component of the qubit device, the josephson junction 34 includes three layers stacked in sequence, and in order to complete the fabrication of the quantum chip, the josephson junction 34 needs to be connected with other components or structures to form a complete qubit device. Illustratively, to form a kind of Xmon Qubit based Qubit device, for example, josephson junction devices 3 are formed on the substrate 1 of the preparation region M, and it is necessary to connect the top and bottom superconductive layers of the josephson junction 34 with the ground layer 21, respectively the capacitive-to-ground plate 22. Those skilled in the art will appreciate that the arrangement of the josephson junction device 3 is not limited to that shown in fig. 1 and 2, and will not be described in detail here.
The scheme of the application is a technical improvement aiming at the problems of complex preparation process and poor electrical contact when the interconnection between the josephson junction 3 and other circuit structures (such as a ground capacitor, a ground plane (GND) and the like) on the quantum chip is realized in the related quantum chip preparation technology. Embodiments of the present application will be explained in detail below with reference to the drawings, and in the following description, other circuit structures (e.g., capacitance to ground, ground plane (GND), etc.) connected to a josephson junction on a quantum chip are generically referred to as structures to be connected.
Example 1
Fig. 3 is a schematic structural diagram of a quantum chip according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a superconducting circuit 41 according to an embodiment of the present application, where fig. 4(2) is a cross-sectional view of Aa of fig. 4 (1).
Fig. 5 is a schematic structural diagram of a superconducting circuit 42 according to an embodiment of the present application, wherein fig. 5(2) is a cross-sectional view of Bb of fig. 5 (1).
A superconducting circuit provided in embodiment 1 of the present application includes:
a structure to be connected;
an extraction structure electrically connected to the superconducting layer of the josephson junction 34; and
a transition structure covering a portion of the structure to be connected and a portion of the lead-out structure to enable electrical connection.
In the superconducting circuit in embodiment 1 of the present application, the superconducting layer of the josephson junction 34 and the structure to be connected are electrically connected through the lead-out structure electrically connected to the superconducting layer of the josephson junction 34 and the transition structure covering part of the structure to be connected and part of the lead-out structure, and the superconducting circuit has good electrical contact performance.
In some embodiments of the present application, in order to form a structure with good electrical contact and facilitate the sequential preparation of a lead-out structure and a transition structure, the extension direction of the transition structure with respect to the structure to be connected is different from the extension direction of the lead-out structure with respect to the structure to be connected.
Illustratively, two specific examples of the superconducting circuit provided in embodiment 1 of the present application are described below, respectively.
Referring to fig. 4, in some embodiments of the present application, as shown in fig. 1, 2 and 3 in combination, the superconducting circuit includes a first superconducting circuit 41, the first superconducting circuit 41 includes a capacitance-to-ground plate 22, a bottom layer lead-out structure 31 electrically connected to a bottom superconducting layer of a josephson junction 34, and a first transition structure 411, and the first transition structure 411 covers a portion of the capacitance-to-ground plate 22 and a portion of the bottom layer lead-out structure 31 to electrically connect the capacitance-to-ground plate 22 and the bottom layer lead-out structure 31. In specific implementation, in order to form a good electrical contact structure and facilitate the sequential preparation of the bottom layer lead-out structure 31 and the first transition structure 411, the extending direction of the first transition structure 411 relative to the ground capacitor plate 22 is different from the extending direction of the bottom layer lead-out structure 31 relative to the ground capacitor plate 22, that is, the first transition structure 411 and the bottom layer lead-out structure 31 form a certain included angle.
Referring to fig. 5, in some embodiments of the present application, as shown in fig. 1, fig. 2 and fig. 3 in combination, a superconducting circuit 4 provided in example 1 of the present application includes a second superconducting circuit 42, where the second superconducting circuit 42 includes a ground layer 21, a top layer lead-out structure 33 electrically connected to a top superconducting layer of a josephson junction 34, and a second transition structure 421, and the second transition structure 421 covers a part of the ground layer 21 and a part of the top layer lead-out structure 33 to electrically connect the ground layer 21 and the top layer lead-out structure 33. In specific implementation, in order to form a good electrical contact structure and facilitate the sequential preparation of the top lead-out structure 33 and the second transition structure 421, the extending direction of the second transition structure 421 relative to the ground layer 21 is different from the extending direction of the top lead-out structure 33 relative to the ground layer 21, that is, the extending directions of the second transition structure 421 and the top lead-out structure 33 are not parallel.
In one embodiment of the present invention, an angle formed by the extending direction of the second transition structure 421 and the extending direction of the top layer lead-out structure 33, an angle formed by the extending direction of the first transition structure 411 and the extending direction of the bottom layer lead-out structure 31 are in a range from 30 ° to 60 °, for example, the angle is any one of 30 °, 35 °, 45 °, 55 °, and 60 °.
In an embodiment where a superconducting circuit provided in example 1 of the present application includes a first superconducting circuit 41 and a second superconducting circuit 42, the first transition structure 411 and the second transition structure 421 can be formed in a single deposition process, and in some embodiments of the present application, the extending directions of the first transition structure 411 and the second transition structure 421 are parallel to each other.
In some embodiments of the present application, the bottom superconductive layer of the josephson junction 34 is integrally formed with the bottom layer lead-out structure 31, and the top superconductive layer of the josephson junction 34 is integrally formed with the top layer lead-out structure 33.
In other embodiments of the present application, the ground layer 21, the capacitance-to-ground board 22, the bottom lead-out structure 31, the top lead-out structure 33, the first transition structure 411, and the second transition structure 421 all include a superconducting material layer. The superconducting material layer includes at least one of aluminum, niobium nitride, titanium nitride, and the like.
Example 2
Fig. 3 is a schematic structural diagram of a quantum chip according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a superconducting circuit 41 according to an embodiment of the present application, where fig. 4(2) is a cross-sectional view of Aa of fig. 4 (1).
Fig. 5 is a schematic structural diagram of a superconducting circuit 42 according to an embodiment of the present application, where fig. 5(2) is a cross-sectional view of Bb in fig. 5 (1).
Referring to fig. 3, 4 and 5, in combination with fig. 1 and 2, embodiment 2 of the present application provides a qubit device including a ground layer 21, a capacitance-to-ground plate 22, and at least one josephson junction 34, the qubit device further including:
a bottom layer lead-out structure 31 electrically connected with the bottom super conductive layer of the Josephson junction 34, and a top layer lead-out structure 33 electrically connected with the top super conductive layer of the Josephson junction 34; and
a first transition structure 411 covering a part of the bottom layer lead-out structure 31 and a part of the ground capacitor plate 22, and a second transition structure 421 covering a part of the top layer lead-out structure 33 and a part of the ground layer 21, so as to realize the electrical connection between the bottom layer lead-out structure 31 and the ground capacitor plate 22, and the electrical connection between the top layer lead-out structure 33 and the ground layer 21.
In some embodiments of the present application, in order to form a structure with good electrical contact and facilitate the sequential preparation of the bottom layer lead-out structure 31 and the first transition structure 411, the extending direction of the first transition structure 411 with respect to the ground capacitor plate 22 is different from the extending direction of the bottom layer lead-out structure 31 with respect to the ground capacitor plate 22.
In other embodiments of the present application, in order to form a structure with good electrical contact and facilitate the sequential preparation of the top lead-out structure 33 and the second transition structure 421, the extending direction of the second transition structure 421 relative to the ground layer 21 is different from the extending direction of the top lead-out structure 33 relative to the ground layer 21.
Preferably, the extending direction of the second transition structure 421 forms an included angle with the extending direction of the top layer leading-out structure 23, the extending direction of the first transition structure 411 forms an included angle with the extending direction of the bottom layer leading-out structure 31, and the included angle is in a range of 30 ° to 60 °, for example, the included angle is any one of 30 °, 35 ° 45 °, 55 ° and 60 °.
In order to facilitate a single deposition process, i.e., to form the first transition structure 411 and the second transition structure 421, in some embodiments of the present application, the first transition structure 411 and the second transition structure 421 extend in parallel.
In an embodiment of the present application, the bottom superconducting layer of the josephson junction 34 is integrally formed with the bottom lead-out structure 31, and the top superconducting layer of the josephson junction 34 is integrally formed with the top lead-out structure 33.
In other embodiments of the present application, the ground layer 21, the capacitance-to-ground board 22, the bottom lead-out structure 31, the top lead-out structure 33, the first transition structure 411, and the second transition structure 421 all include a superconducting material layer. The superconducting material layer includes at least one of aluminum, niobium nitride, titanium nitride, and the like.
In the qubit device in embodiment 2 of the present application, the bottom layer lead-out structure 31 electrically connected to the bottom super-conductive layer of the josephson junction 34 and the first transition structure 411 covering part of the bottom layer lead-out structure 31 and part of the capacitance-to-ground plate 22 are used to electrically connect the bottom super-conductive layer of the josephson junction 34 and the capacitance-to-ground plate 22, and the top layer lead-out structure 33 electrically connected to the top super-conductive layer of the josephson junction 34 and the second transition structure 421 covering part of the top layer lead-out structure 33 and part of the ground layer 21 are used to electrically connect the top super-conductive layer and the ground layer 21, so that the josephson junction 34 and the capacitance-to-ground plate 22 and the ground layer 21 have good electrical contact performance.
Example 3
Fig. 6 is a flowchart of a method for manufacturing a superconducting circuit according to an embodiment of the present application.
Fig. 8 is a schematic view of a process for manufacturing a quantum chip according to an embodiment of the present disclosure (only an M region is shown).
Referring to fig. 6 and 8 in combination with fig. 1 to 5, a method for manufacturing a superconducting circuit according to embodiment 3 of the present application includes steps S301 to S304, where:
s301, a photoresist layer 5 is formed to cover the structure to be connected and the first region where the lead-out structure electrically connected to the superconducting layer of the josephson junction 34 is to be located.
The superconducting circuit preparation method provided by the embodiment of the application is used for preparing the structure to be connected and the lead-out structure which are connected in an electrical contact mode. Illustratively, the structure to be connected may be at least one of a ground layer 21 and a capacitance-to-ground board 22. The extraction structure electrically connected to the superconducting layer of the josephson junction 34 may be at least one of a bottom layer extraction structure 31 and a top layer extraction structure 33, wherein the bottom layer extraction structure 31 is electrically connected to the bottom super-conductive layer of the josephson junction 34, and the top layer extraction structure 33 is electrically connected to the top super-conductive layer of the josephson junction 34. According to the preparation method of the embodiment 3, the leading-out structure and the corresponding structure to be connected can be electrically connected in a contact manner according to the functional requirements of the constructed superconducting circuit.
S302, patterning the photoresist layer to obtain a deposition window, wherein the deposition window comprises a first window exposing the first area and a second window exposing the second area, and the second area comprises a part of the first area and a third area located on the surface of the structure to be connected, namely the second area is intersected with the first area.
As shown in fig. 3, 4, 5 and 8, exemplarily: in fabricating the first superconducting circuit 41, the first deposition region 111, and the second region including the third region on the surface of the capacitive-ground plate 22 and a portion of the first deposition region 111, it is understood that the second region intersects the first region, and in one embodiment, the second region intersects the first region away from the josephson junction 34. In fabricating the second superconducting circuit 42, the first region is the second deposition region 112, the second region includes a third region on the surface of the ground layer 21, and a portion of the second deposition region 112, it being understood that the second region intersects the first region, which in one embodiment is remote from the josephson junction 34.
In some embodiments of the present application, in order to facilitate deposition in the first region and the second region, respectively, the second region extends in a direction different from the direction in which the first region extends with respect to the structure to be connected.
Illustratively, the extension direction of the second region and the extension direction of the first region form an angle having a value in the range of 30 ° to 60 °, for example, the angle is any one of 30 °, 35 °, 45 °, 55 °, 60 °.
And S303, sequentially utilizing the first window and the second window to perform directional deposition so as to respectively form the leading-out structure positioned in the first area and a transition structure covering the second area and part of the leading-out structure.
As shown in connection with fig. 3 and 6, exemplarily: in the preparation of the first superconducting circuit 41, the first window directional deposition is used to form the bottom layer lead-out structure 31 located in the first deposition region 111, and the second window directional deposition is used to form the first transition structure 411 covering the second region and a part of the bottom layer lead-out structure 31. In the preparation of the second superconducting circuit 42, the first window is used for directional deposition to form the top layer leading-out structure 33 located in the second deposition region 112, and the second window is used for directional deposition to form the second transition structure 421 covering the second region and part of the top layer leading-out structure 33.
S304, removing the photoresist layer to obtain a superconducting circuit, for example, removing the photoresist layer in a peeling manner to obtain a superconducting circuit 4, and the superconducting circuit 4 includes a structure to be connected, an extraction structure electrically connected with the superconducting layer of the josephson junction, and a transition structure covering a part of the structure to be connected and a part of the extraction structure to achieve electrical connection.
In some preferred embodiments of the present application, in order to avoid an oxide layer on a surface of a structure to be connected from affecting electrical connection performance, before the step of directionally depositing by sequentially using the first window and the second window, the method further includes:
and removing the oxide layer of the third region, for example, removing the oxide film on the surface of the third region by using a directional etching method, i.e., etching and removing the oxide film of the third region by using directional high-energy ion bombardment.
Illustratively, as a specific embodiment, the step of removing the oxide layer of the third region includes:
determining an inclination angle according to the first window and the second window so that the extraction structure is shielded when the oxide layer of the third area is etched according to the inclination angle ion beam;
and etching the oxide layer of the third area according to the angle ion beam.
In the embodiment of the present application, after the deposition window is formed on the photoresist layer 5, the ion beam with a certain inclination angle is used to bombard the third area to etch the oxide layer, for example, to etch the oxide film formed on the surfaces of the ground capacitor plate 22 and the ground layer 21, and in the process of ion beam etching, because the directional high-energy ions have an inclination angle, the surface of the extraction structure far away from the intersection of the second area and the first area, especially the josephson junction 34 far away from the intersection of the second area and the first area, can be shielded and not affected by the ion beam etching.
In some embodiments of the present application, the extraction structure is integrally formed with the superconducting layer of the josephson junction 34.
In the method for manufacturing a superconducting circuit provided in embodiment 3 of the present application, the structure to be connected, the lead-out structure, and the transition structure each include a superconducting material layer. The superconducting material layer includes at least one of aluminum, niobium nitride, titanium nitride, and the like.
Example 4
Fig. 7 is a flowchart of a method for manufacturing a qubit device according to an embodiment of the present disclosure.
Fig. 8 is a schematic view of a process for manufacturing a quantum chip according to an embodiment of the present disclosure (only an M region is shown).
Referring to fig. 7 and 8 in combination with fig. 1 to 5, embodiment 4 of the present application provides a method for manufacturing a qubit device including a ground layer (GND)21, a capacitance-to-ground plate 22, and a josephson junction device 3, wherein the josephson junction device 3 includes at least one josephson junction 34, the method for manufacturing the qubit device including steps S401 to S406, wherein:
s401, as shown in fig. 8(1), providing a substrate 1, where the ground layer (GND)21 and the capacitance-to-ground board 22 are formed on the substrate 1;
s402, as shown in fig. 8(1), determining a junction preparation region 11 on the substrate 1, where the junction preparation region 11 includes a first deposition region 111 and a second deposition region 112 intersecting with each other, where the first deposition region 111 is used for preparing a bottom super-conductive layer of the josephson junction 34 and a bottom extraction structure 31 electrically connected to the bottom super-conductive layer, and the second deposition region 112 is used for preparing a top super-conductive layer of the josephson junction 34 and a top extraction structure 33 electrically connected to the top super-conductive layer, and it can be understood that if two josephson junctions 34 are to be prepared, there are two second deposition regions 112, for example, two second deposition regions 112 parallel to each other;
s403, forming a photoresist layer 5 covering the junction preparation area 11, and the ground layer (GND)21 and the capacitance-to-ground plate 22;
s404, as shown in fig. 8(1) and 8(2), patterning the photoresist layer 5 to obtain a deposition window, the deposition window including a junction region window 51 exposing the junction preparation region 11, a first transition window 52 exposing a first transition region including a region of a surface of a portion of the capacitance-to-ground board 22 and a portion of the first deposition region 111, and a second transition window 53 exposing a second transition region including a region of a surface of a portion of the ground plane (GND)21 and a portion of the second deposition region 112;
s405, as shown in fig. 8(3), directionally depositing by using the junction region window 51 to form a josephson junction 34, the bottom lead-out structure 31 and the top lead-out structure 33; and
s406, as shown in fig. 8(4), directionally depositing by using the first transition window 52 and the second transition window 53 to form a first transition structure 411 covering a portion of the bottom layer lead-out structure 31 and a portion of the grounded capacitor board 22, and a second transition structure 421 covering a portion of the top layer lead-out structure 33 and a portion of the ground layer (GND)2, so as to respectively realize electrical connection.
The manufacturing method of embodiment 4 may further include, after step S406, a step of removing the photoresist layer, for example, removing the photoresist layer in a lift-off manner, so as to obtain a qubit device.
In order to facilitate the deposition at different tilt angles, respectively.
In some embodiments of the present application, the extending direction of the first transition region with respect to the capacitance-to-ground plate 22 is different from the extending direction of the first deposition region 111 with respect to the capacitance-to-ground plate 22.
In other embodiments of the present application, the extending direction of the second transition area with respect to the ground layer (GND)21 is different from the extending direction of the second deposition area 112 with respect to the ground layer (GND) 21.
In some preferred embodiments of the present application, the extension directions of the first transition region and the second transition region are parallel to each other so that the first transition structure 411 and the second transition structure 421 can be formed by one deposition process.
In other preferred embodiments of the present application, before the step of utilizing the first transition window 52 and the second transition window 53 to directionally deposit, the method further includes:
and removing part of the oxide layer on the surface of the capacitance-to-ground board 22 and part of the oxide layer on the surface of the ground layer (GND)21, for example, removing the oxide films formed on the surface of the capacitance-to-ground board 22 and the surface of the ground layer (GND)21 by using a directional etching method.
Wherein, for example, the step of removing part of the oxide layer on the surface of the capacitive-to-ground plate 22 and part of the oxide layer on the surface of the ground layer (GND)21 comprises:
determining inclination angles according to the junction window 51, the first transition window 52 and the second transition window 53 so that the josephson junction 34 is shielded when the ion beam is directed according to the inclination angles to etch the oxide layers on the surfaces of the grounded capacitive plate 22 and the ground layer (GND)21, i.e. the structure (SIS) formed by overlapping the bottom superconducting layer, the barrier layer and the top superconducting layer is shielded; for example, the tilt angle during the directional etching is determined according to the shape structure parameters of the junction region window 51, the first transition window 52 and the second transition window 53, the window width, the photoresist thickness, and the relative positional relationship of the junction region window 51, the first transition window 52 and the second transition window 53.
And etching part of the oxide layer on the surface of the capacitance-to-ground plate 22 and part of the oxide layer on the surface of the grounding layer (GND)21 according to the inclined angle directional ion beams so as to avoid the defect of poor electrical contact caused by the oxide layers.
Similarly, the tilt angle may also be adjusted as needed to etch the oxide layer on the areas where the surfaces of the top layer extraction structure and the bottom layer extraction structure are to be covered, for example, the surface of the bottom layer extraction structure 31 at the intersection of the first transition region and the first deposition region 111 is subjected to ion beam etching.
In some embodiments of the present application, in order to avoid the effect of etching on the josephson junction 34 during directional etching, the second transition region is not parallel to the first deposition region 111 and the second transition region is not parallel to the second deposition region 112, illustratively, the first deposition region 111 and the second deposition region 112 are perpendicular to each other, and the second transition region forms an angle of 30 ° to 60 ° with respect to the first deposition region 111.
Fig. 9 is a schematic view of a deposition window provided in the present embodiment, wherein fig. 9(2) is a schematic view of a Dd cross section in fig. 9(1), and fig. 9(3) is a schematic view of an Ee cross section in fig. 9 (1).
In this embodiment, the photoresist layer 5 may be one of the photoresists such as PMMA and S1810, but is not limited thereto.
In some embodiments of the present application, in order to facilitate deposition of each region and directional ion beam etching of an oxide film formed on the surface of the ground capacitor plate 22 and the ground layer (GND)21, the junction region window 51, the first transition window 52 (see the schematic cross-sectional view of the second transition window 53), and the second transition window 53 formed on the photoresist layer 5 have a shape configuration with a bottom cut angle (an UnderCut structure, which may be referred to as an UnderCut structure) or the like such that the deposition window is formed to have an upper opening width smaller than a lower opening width, and the window width W of the first transition window 52 and the second transition window 53 is greater than the window width W of the junction region window 51, and exemplarily, 5W ≦ 10W. Illustratively, the junction region window 51 exposes a first deposition region 111 having a first extension direction 61, a second deposition region 112 having a second extension direction 62, a first transition region having a third extension direction 63, a second transition region having a fourth extension direction 64, the first extension direction 61 and the second extension direction 62 being perpendicular to each other, the third extension direction 63 and the fourth extension direction 64 being parallel to each other, the fourth extension direction 64 forming an angle of 30 ° to 60 ° with the first extension direction 61.
In other preferred embodiments of the present application, two photoresist layers may be coated to form the photoresist layer 5, for example, the photoresist layer 5 includes a first photoresist layer 501 and a second photoresist layer 502 on the first photoresist layer 501, illustratively, the first photoresist layer 501 adopts MMA, the second photoresist layer 502 adopts PMMA, the junction region window 51, the first transition window 52 and the second transition window 53 formed after exposure and development have better undercut angles, so that when the first deposition region 111 is deposited, the second deposition region 112, the first transition region and the second transition region are blocked, similarly, when the second deposition region 112 is deposited, the first deposition region 111, the first transition region and the second transition region are blocked, when the ion beam is oriented at a certain tilt angle to etch the oxide layers on the surfaces of the ground capacitor plate 22 and the ground layer (GND)21, the josephson junction 34 is shielded so that the ion beam etching does not damage the josephson junction 34.
It should be appreciated that reference throughout this specification to "some embodiments," "an embodiment," or "an implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in various embodiments, including the detailed description and the specific examples.
The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.
Claims (21)
1. A superconducting circuit, comprising:
a structure to be connected;
an extraction structure electrically connected to the superconducting layer of the Josephson junction; and
a transition structure covering a portion of the structure to be connected and a portion of the lead-out structure to enable electrical connection.
2. The superconducting circuit of claim 1, wherein a direction of extension of the transition structure with respect to the structure to be connected is different from a direction of extension of the lead-out structure with respect to the structure to be connected.
3. The superconducting circuit of claim 1, wherein the extraction structure is integrally formed with a superconducting layer of the josephson junction.
4. A superconducting circuit according to any one of claims 1-3, characterized in that the lead-out structure comprises:
a top layer extraction structure electrically connected with the top super-conducting layer of the Josephson junction;
and/or the presence of a gas in the atmosphere,
a bottom layer extraction structure electrically connected with the bottom super conducting layer of the Josephson junction.
5. A superconducting circuit according to any one of claims 1-3, characterized in that the structures to be connected, the lead-out structure and the transition structure each comprise a layer of superconducting material.
6. The superconducting circuit of claim 5, wherein the layer of superconducting material includes at least one of aluminum, niobium nitride, and titanium nitride.
7. A qubit device comprising a ground layer, a capacitive-to-ground plate, and at least one josephson junction, the qubit device further comprising:
a bottom layer lead-out structure electrically connected with the bottom super conducting layer of the Josephson junction, and a top layer lead-out structure electrically connected with the top super conducting layer of the Josephson junction; and
the first transition structure covers part of the bottom layer leading-out structure and part of the ground capacitor plate, and the second transition structure covers part of the top layer leading-out structure and part of the ground layer, so that electric connection is realized respectively.
8. The qubit device of claim 7 wherein the first transition structure extends in a direction different from a direction in which the bottom extraction structure extends with respect to the capacitive-to-ground plate;
and/or the presence of a gas in the gas,
the extending direction of the second transition structure relative to the ground layer is different from the extending direction of the top layer lead-out structure relative to the ground layer.
9. The qubit device of claim 7 or 8, wherein the directions of extension of the first transition structure and the second transition structure are parallel to each other.
10. A method of making a superconducting circuit, comprising:
forming a photoresist layer to cover the structure to be connected and a first region where a lead-out structure electrically connected with the superconducting layer of the Josephson junction is to be located;
patterning the photoresist layer to obtain a deposition window, wherein the deposition window comprises a first window exposing the first area and a second window exposing the second area, and the second area comprises a part of the first area and a third area positioned on the surface of the structure to be connected;
sequentially utilizing the first window and the second window for directional deposition to respectively form the leading-out structure positioned in the first area and a transition structure covering the second area and part of the leading-out structure;
and removing the photoresist layer to obtain the superconducting circuit.
11. The production method according to claim 10, wherein an extending direction of the second region with respect to the structure to be connected is different from an extending direction of the first region with respect to the structure to be connected.
12. The method of claim 10, wherein the extraction structure is integrally formed with a superconducting layer of the josephson junction.
13. The method of claim 10, further comprising, prior to the step of sequentially utilizing the first window and the second window for directional deposition:
and removing the oxide layer of the third area.
14. The method according to claim 13, wherein the step of removing the oxide layer of the third region comprises:
determining an inclination angle according to the first window and the second window so that the extraction structure is shielded when the oxide layer of the third area is etched according to the inclination angle ion beam;
and etching the oxide layer of the third area according to the inclined ion beam.
15. The production method according to claim 10, wherein the structure to be connected, the lead-out structure, and the transition structure each include a superconducting material layer.
16. The method according to claim 15, wherein the superconducting material layer includes at least one of aluminum, niobium nitride, and titanium nitride.
17. A method of fabricating a qubit device comprising a ground layer, a capacitive-to-ground plate, and at least one josephson junction, the method comprising:
providing a substrate, wherein the grounding layer and the ground capacitor plate are formed on the substrate;
determining a junction preparation region on the substrate, the junction preparation region comprising a first deposition region and a second deposition region intersecting, wherein the first deposition region is used for preparing a bottom superconductive layer of the Josephson junction and a bottom layer extraction structure electrically connected with the bottom superconductive layer, and the second deposition region is used for preparing a top superconductive layer of the Josephson junction and a top layer extraction structure electrically connected with the top superconductive layer;
forming a photoresist layer to cover the junction preparation area, and the ground layer and the capacitance-to-ground plate;
patterning the photoresist layer to obtain a deposition window, the deposition window including a junction region window exposing the junction preparation region, a first transition window exposing a first transition region, and a second transition window exposing a second transition region, the first transition region including an area of a portion of the surface of the capacitor-to-ground plane and a portion of the first deposition region, the second transition region including an area of a portion of the surface of the ground plane and a portion of the second deposition region;
directionally depositing with the junction region window to form a Josephson junction, the bottom layer extraction structure and the top layer extraction structure; and
and utilizing the first transition window and the second transition window to perform directional deposition to form a first transition structure covering part of the bottom layer lead-out structure and part of the grounding capacitor plate and a second transition structure covering part of the top layer lead-out structure and part of the grounding layer so as to respectively realize electrical connection.
18. The production method according to claim 17, wherein the extending direction of the first transition region with respect to the capacitance-to-ground plate is different from the extending direction of the first deposition region with respect to the capacitance-to-ground plate;
and/or the presence of a gas in the gas,
the extending direction of the second transition area relative to the ground layer is different from the extending direction of the second deposition area relative to the ground layer.
19. The production method according to claim 17 or 18, wherein the first transition zone and the second transition zone extend in parallel to each other.
20. The method of claim 17, further comprising, prior to the step of using the first and second transition windows to direct deposition:
and removing part of the oxide layer on the surface of the capacitor-to-ground plane and part of the oxide layer on the surface of the grounding layer.
21. The method according to claim 20, wherein the step of removing a portion of the oxide layer on the surface of the capacitor-to-ground layer and a portion of the oxide layer on the surface of the ground layer comprises:
determining an inclination angle according to the junction window, the first transition window and the second transition window such that the josephson junction is blocked by the ion beam directed at the inclination angle to etch a portion of the oxide layer of the surface of the capacitance-to-ground plane and a portion of the oxide layer of the surface of the ground plane;
and etching part of the oxide layer on the surface of the capacitor-to-ground plane and part of the oxide layer on the surface of the grounding layer by the directional ion beams according to the inclined angle.
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