KR100265990B1 - Method for fabricating metal interconnector of semiconductor device - Google Patents

Abstract

PURPOSE: A metal wire formation method is provided to improve a step coverage by vertically interconnecting a first and a second wires using etching selectivity between an interlayer dielectric and a photoresist. CONSTITUTION: An etch stopper and an auxiliary metal(7) are sequentially deposited on a semiconductor substrate having a first metal wire. By sequentially etching the auxiliary metal(7), the etch stopper and the first metal wire using a first photoresist pattern, a pillar shaped via is formed. After forming an interlayer dielectric(3) on the resultant structure, the interlayer dielectric(3) is etched to expose the auxiliary metal(7) by using a second photoresist pattern as a mask. A second metal wire(5) is then formed on the auxiliary metal(7).

Description

Metal wiring formation method of semiconductor device

1 is a process diagram for forming metal wirings in a conventional semiconductor device.

2 is a process diagram for forming metal wirings in a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 first metal wiring

3: interlayer insulating film 5: second metal wiring

6: etch stop layer 7: auxiliary metal

PR1, PR2: first and second photoresist

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device. In particular, the first metal wiring and the second metal wiring may be formed by using an etch stop layer of Ti / W and considering selectivity of an insulating film OXIDE and a photoresist PR. The present invention relates to a method for forming metal wirings in a semiconductor device in which step coverage is improved by vertically wiring layers.

In general, a method of forming metal wirings of a semiconductor device, which is widely used, is sputtered according to an aspect ratio of a via hole (VIA HOLE) connecting the first metal wiring and the second metal wiring, as shown in FIG. 1. Poor step coverage of the aluminum, the second metal wire, may affect short circuit or reliability.

That is, as shown in (a), the first metal wiring 2 is deposited and photo-etched on the semiconductor substrate 1 to be left only in a predetermined portion, and then the interlayer insulating film 3 is deposited over the entire surface of (b) and the ground.

After the process, as shown in (c), the via insulating film 3 is formed by etching the interlayer insulating film 3 of the portion where the second metal wiring is to be formed, and then the second metal wiring is deposited on the entire surface by sputtering and etched (d). As shown in FIG. 2, the second metal wire 5 is formed only around the via hole 4.

The metal interconnection forming method of the vertical semiconductor device as described above includes a contact (semiconductor substrate and metal junction) and a high aspect ratio of the via hole for forming the first metal interconnection and the second metal interconnection, and the step coverage of the sputtered second metal interconnection. (STEP COVERAGE) As a result, many problems occur in short circuit or reliability of the second metal wiring.

In order to solve the above problems, an etch stop layer of Ti / W is formed on a semiconductor substrate and a first metal wiring, and the first selectable layer is formed by considering the etch selectivity of the interlayer insulating layer OXIDE and the photoresist PR. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring in a semiconductor device to improve step coverage by vertically wiring a metal wiring and a second metal wiring.

The present invention provides a method of forming a metal wiring in a semiconductor device, in which a first metal wiring (2) is formed on a semiconductor substrate (1), and an etch stop layer (6) and an auxiliary metal (7) are sequentially deposited on the front surface. (Double) A pillar-type via layer having a structure of the first metal wiring 2, the etch stop layer 6, and the auxiliary metal 7 by applying and photoetching the first photoresist PR1 to the metal wiring region. Forming a layer, depositing the interlayer insulating film 3 and the second photoresist PR2 to a predetermined thickness on the entire surface after the step, and using the second photoresist PR2 as a mask to form the interlayer insulating film 3. Etching the auxiliary metal 7 until it is revealed, and after the step, the second metal wiring 5 is deposited and photo etched to form a metal structure having a double structure.

Hereinafter, described in detail by the accompanying drawings as follows.

FIG. 2 is a process diagram of forming a metal wiring in a semiconductor device according to the present invention. First, as shown in (a), the first metal wiring 2 is deposited and photo-etched on the semiconductor substrate 1 to retain only a predetermined portion. The etch stop layer 6 of Ti / W is sequentially deposited by a predetermined thickness over the entire surface of the tile and the ground. At this time, by using an etching solution of the etch stop layer 6 and the first metal wiring 2 of Ti / W differently, the oxide layer on the semiconductor substrate 1 is over etched. To protect them.

Thereafter, as shown in (c), an auxiliary metal 7 of aluminum is deposited, and as shown in (d), a first photoresist PR1 is applied to a predetermined portion to form a via layer of a pillar, and then the first photoresist is formed. Etching (PR1) as a mask forms a columnar via layer having a structure of the first metal wiring 2, the etch stop layer 6, and the auxiliary metal 7 as shown in (e).

That is, when the auxiliary metal 7 is etched, only the auxiliary metal 7 in which the first photoresist PR1 is present remains, and the etch stop layer 6 of Ti / W remains, and then the etch stop layer of the Ti / W layer. When (6) is etched, the via vias in columnar form are wired vertically.

Then, the interlayer insulating film 3 is deposited thicker than the auxiliary metal 7 on (f) and the entire surface of the ground, and then the second photoresist PR2 is coated and flattened as shown in (g). At this time, the etch selectivity of the interlayer insulating film 3 and the second photoresist PR2 are the same, and (h) degree and the second interlayer insulating film 3 are made of the auxiliary metal (the second photoresist PR2 as a mask). Perform plasma etch until 7) is revealed.

When the auxiliary metal 7 of the via layer is exposed as shown in (i) after the above process, the second metal wiring 5 is deposited and photo etched to complete the metal structure of the double structure.

As described above, in the method of forming the metal wiring of the semiconductor device according to the present invention, an etch stop layer of Ti / W is formed on the first metal wiring and the semiconductor substrate, and the interlayer insulating film OXIDE and the second photoresist PR2 are formed. ), The first metal wiring and the second metal wiring are vertically wired to the via layer with the same etching selectivity, thereby improving the step coverage and contributing to improving the reliability of the semiconductor device.

Claims (3)

A method of forming a double metal interconnection perpendicular to a semiconductor substrate, the method comprising: forming a via layer having a pillar shape having a structure of a first metal interconnection, an etch stop layer, and an auxiliary metal on the semiconductor substrate; Sequentially forming an interlayer insulating film and a photoresist so as to cover the via layer, and etching the photoresist and the interlayer insulating film so as to be planarized by exposing an auxiliary metal of the via layer on the interlayer insulating film; And forming a second metal wiring in contact with the exposed auxiliary metal and vertically connected to the via layer. The method of claim 1, wherein the etch stop layer comprises Ti / W. The method of claim 1, wherein the auxiliary metal is aluminum (Al).