KR19990000069A - Metal contact manufacturing method of semiconductor device - Google Patents
Metal contact manufacturing method of semiconductor device Download PDFInfo
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- KR19990000069A KR19990000069A KR1019970022712A KR19970022712A KR19990000069A KR 19990000069 A KR19990000069 A KR 19990000069A KR 1019970022712 A KR1019970022712 A KR 1019970022712A KR 19970022712 A KR19970022712 A KR 19970022712A KR 19990000069 A KR19990000069 A KR 19990000069A
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Abstract
본 발명은 반도체 소자의 금속콘택 제조방법에 관한 것으로, 소정의 하부구조에 적층구조로된 Pt 저장전극 및 TiN 확산방지막을 구비하는 절연막을 형성하고 반도체 기판이 노출될 때까지 식각하여 제1콘택홀을 형성한 다음, 전표면에 Ti/TiN막과 W막을 순차적으로 형성하고 SF6플라즈마로 에치백한 후, 재차 Cl2/BCl3플라즈마로 에치백한 다음 상기 Pt막이 노출될때 까지 식각하여 제2콘택홀을 형성하고 전표면에 유기용매(예컨대 ACT)를 이용하여 세정공정을 실시한 다음 Ti/TiN막과 금속배선을 형성하고 패터닝함으로서 반도체 소자의 전기적 특성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal contact of a semiconductor device, wherein an insulating film including a Pt storage electrode and a TiN diffusion barrier layer having a laminated structure is formed on a predetermined substructure, and the first contact hole is etched until the semiconductor substrate is exposed. Next, the Ti / TiN film and the W film were sequentially formed on the entire surface, etched back with SF 6 plasma, etched back with Cl 2 / BCl 3 plasma, and then etched until the Pt film was exposed. The present invention relates to a technique for improving the electrical characteristics of a semiconductor device by forming a contact hole, performing a cleaning process using an organic solvent (for example, ACT) on the entire surface, and then forming and patterning a Ti / TiN film and a metal wiring.
Description
본 발명은 반도체 소자의 금속콘택 제조방법에 관한 것으로, 특히 중속 콘택홀 형성 후 텅스텐 금속플러그를 형성하여 금속 이온의 확산방지막으로 이용함으로써 습식 세정공정시에 수반되는 오염을 원천적으로 방지할 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal contact of a semiconductor device. In particular, a technique capable of fundamentally preventing contamination in a wet cleaning process by forming a tungsten metal plug after forming a medium speed contact hole and using it as a diffusion preventing film of metal ions. It is about.
반도체 소자에서 상하의 도전배선을 연결하는 콘택홀 자체으 크기와 주변배선과의 간격을 감소됨에 따라 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)는 증가한다.As the contact hole itself connecting the upper and lower conductive wirings in the semiconductor device is reduced in size and the distance between the peripheral wirings, an aspect ratio, which is a ratio of the diameter and the depth of the contact hole, increases.
따라서, 다층의 도전배선을 구비하는 고집적 반도체 소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정 여유도가 감소된다.Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
도 1은 종래 기술에 따른 반도체 소자의 금속콘택 공정단면도이다.1 is a cross-sectional view of a metal contact process of a semiconductor device according to the prior art.
먼저, 반도체 기판(1)에 적층구조로 이루어진 저장전극인 Pt막(2)과 확산방지막인 TiN막(3)을 구비하는 절연막(4)을 형성한다.First, an insulating film 4 having a Pt film 2 as a storage electrode having a laminated structure and a TiN film 3 as a diffusion barrier film is formed on the semiconductor substrate 1.
다음, 콘택마스크를 이용하여 반도체기판(1)이 노출될때 까지 식각하여 콘택홀(5)을 형성한다.Next, using the contact mask, the semiconductor substrate 1 is etched until the semiconductor substrate 1 is exposed to form the contact hole 5.
이때, 상기 콘택홀(5)을 형성시 상기 확산방지막인 TiN막(3)이 식각되어 저장전극인 Pt막(2)이 동시에 노출되게 된다.At this time, when the contact hole 5 is formed, the TiN film 3 as the diffusion barrier layer is etched to expose the Pt film 2 as the storage electrode at the same time.
상기와 같은 종래 기술에 따르면, FeRAM 및 1기가 디램 이상에서 Pt막을 저장전극으로 사용시 후속 금속콘택을 형성할때에는 하부물질이 실리콘과 TiN/Pt의 금속막이 동시에 노출됨으로써 습식 세정공정을 진행할때 금속막의 하부로부터금속이온이 세정 용액을 통하여 이동함으로써 실리콘 접합에 심각한 오염을 유발하여 소자의 전기적 특성을 저하시키는 문제점이 있다.According to the prior art as described above, when forming a subsequent metal contact when using a Pt film as a storage electrode in FeRAM and 1 giga DRAM or more, the lower material is exposed to the metal film of silicon and TiN / Pt at the same time during the wet cleaning process of the metal film Metal ions move from the bottom through the cleaning solution, causing serious contamination of the silicon junction, thereby deteriorating the electrical characteristics of the device.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 적층구조로된 Pt 저장전극 및 TiN 확산방지막을 구비하는 절연막을 형성하고 반도체 기판의 노출될때까지 식각하여 제1콘택홀을 형성한 다음, 전표면에 Ti/TiN막과 W막을 순차적으로 형성하고 SF6플라즈마로 에치백한 후, 재차 Cl2/BCl3플라즈마로 에치백한 다음 상기 Pt막이 노출될때 까지 식각하여 제2콘택홀을 형성하고 전표면에 유기용매를 이용하여 후처리를 실시한 다음 Ti/TiN막과 금속배선을 형성하고 패터닝함으로써 습식 후처리를 실시할때 Pt/TiN막으로 부터 금속 이온이 후처리 용액을 통해 이동하여 실리콘 기판에 접합되어 오염되는 현상을 방지하는 반도체 소자의 전기적 특성을 향상시키는 반도체 소자의 금속콘택 제조방법을 제공하는데 그목적이 있다.Accordingly, the present invention is to solve the above problems to form an insulating film having a Pt storage electrode and a TiN diffusion barrier layer of a laminated structure and to form a first contact hole by etching until the semiconductor substrate is exposed, then the entire surface Ti / TiN and W films were sequentially formed on the substrate, etched back with SF 6 plasma, etched back with Cl 2 / BCl 3 plasma, and then etched until the Pt film was exposed to form a second contact hole. After the post-treatment using an organic solvent, the metal ion is transferred from the Pt / TiN film through the post-treatment solution and bonded to the silicon substrate when the wet post-treatment is performed by forming and patterning the Ti / TiN film and the metal wiring. It is an object of the present invention to provide a method for manufacturing a metal contact of a semiconductor device to improve the electrical properties of the semiconductor device to prevent the phenomenon of contamination.
도 1은 종래 기술에 따른 반도체 소자의 금속콘택 공정단면도.1 is a cross-sectional view of a metal contact process of a semiconductor device according to the prior art.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 금속콘택 제조공정도.2a to 2e is a metal contact manufacturing process of the semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1,11:반도체 기판 2,13:Pt막1,11: semiconductor substrate 2,13: Pt film
3,15:TiN막 4,17:절연막3,15: TiN film 4,17: insulating film
5,19:콘택홀 21,27:Ti/TiN막5, 19: contact hole 21, 27: Ti / TiN film
23:W막 25:제2콘택홀23: W film 25: 2nd contact hole
29:금속배선29: metal wiring
상기 목적을 달성하기 위해 본 발명에 반도체 소자의 금속콘택 제조방법은Metal contact manufacturing method of a semiconductor device in the present invention to achieve the above object
소정의 하부구조에 적층구조로된 Pt막 및 TiN막을 형성하는 공정과;Forming a Pt film and a TiN film having a laminated structure in a predetermined substructure;
상기 구조의 전표면에 절연막을 형성하는 공정과;Forming an insulating film on the entire surface of the structure;
상기 절연막의 일측에 제1콘택마스크를 이용하여 콘택으로 예정된 부분의 반도체 기판이 노출될때 까지 식각하여 제1콘택홀을 형성하는 공정과;Forming a first contact hole by using a first contact mask on one side of the insulating layer until the semiconductor substrate of a predetermined portion of the insulating film is exposed;
상기 구조의 전표면에 Ti/TiN막과 W막을 순차적으로 형성하는 공정과;Sequentially forming a Ti / TiN film and a W film on the entire surface of the structure;
상기 W막/Ti/TiN막을 SF6플라즈마로 에치백한 다음, 재차 Cl2/BCl3플라즈마로 에치백하는 공정과;Etching the W film / Ti / TiN film with SF 6 plasma and then again back to Cl 2 / BCl 3 plasma;
상기 절연막의 타측에 제2콘택마스크를 이용하여 상기 Pt막이 노출될때 까지 식각하여 제2콘택홀을 형성하는 공정과;Forming a second contact hole by etching a second contact mask on the other side of the insulating layer until the Pt film is exposed;
상기 구조의 전표면에 유기용매를 이용한 세정공정을 실시하여 금속이온을 제거하는 공정과;Performing a cleaning step using an organic solvent on the entire surface of the structure to remove metal ions;
상기 구조의 전표면에 Ti/TiN막과 금속배선을 형성한 다음, 패터닝하는 공정을 포함하는 것을 특징으로 한다.And forming a Ti / TiN film and a metal wiring on the entire surface of the structure, followed by patterning.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 금속콘택 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method for manufacturing a metal contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 금속콘택 제조공정도이다.2A to 2E are diagrams illustrating a metal contact manufacturing process of a semiconductor device according to the present invention.
먼저, 반도체 기판(11)상부에 하부구조막(도시 않됨)을 형성하고 적층구조로된 저장전극인 Pt막(13) 및 확산방지막 TiN막(15)을 형성한 다음, 전표면에 일정 두께의 절연막(17)을 형성한다.First, a lower structure film (not shown) is formed on the semiconductor substrate 11, and a Pt film 13 and a diffusion barrier TiN film 15, which are storage electrodes having a stacked structure, are formed, and then a predetermined thickness is formed on the entire surface. The insulating film 17 is formed.
다음, 상기 절연막(17)의 일측에 제1콘택마스크를 이용하여 콘택으로 예정된 부분의 반도체 기판(11)이 노출될때 까지 식각하여 제1콘택홀(19)을 형성한다(도 2a 참조).Next, the first contact hole 19 is formed on one side of the insulating layer 17 by using the first contact mask until the semiconductor substrate 11 of the predetermined portion is exposed as a contact (see FIG. 2A).
그 다음, 상기 구조의 전표면에 글루(glue)층으로 Ti/TiN막(21)과 도전층인 W막(23)을 순차적으로 형성하여 콘택플러그를 형성한다.Next, a contact plug is formed by sequentially forming a Ti / TiN film 21 and a W film 23 serving as a conductive layer on the entire surface of the structure.
이때, 상기 Ti/TiN막(21)은 스퍼터링(sputtering)법으로 500~600Å 두께로 형성하며, 상기 W막(23)은 화학적기상증착법(chemical vapor deposition)으로 4000~8000Å 두께로 형성한다(도 2b 참조).In this case, the Ti / TiN film 21 is formed to a thickness of 500 ~ 600Å by the sputtering method, the W film 23 is formed to a thickness of 4000 ~ 8000Å by chemical vapor deposition (chemical vapor deposition) (Fig. 2b).
다음, 상기 W막/Ti/TiN막(23,21)을 SF6, SF6/N2, SF6/O2, SF6/Ar 플라즈마로 에치백(etch-back)한 다음, 다시 Cl2/BCl2플라즈마로 에치백하여 상기 절연막(17) 상부에 남아있는 잔존하는 플리머를 제거한다.Next, the W film / Ti / TiN films 23 and 21 are etched back with SF 6 , SF 6 / N 2 , SF 6 / O 2 , SF 6 / Ar plasma, and then Cl 2 again. The remaining pimmers remaining on the insulating layer 17 are removed by etching back into / BCl 2 plasma.
이때, 상기 에치백을 실시하되 상기 콘택플러그의 W막/Ti/TiN막(23,21)을 1000~2000Å 두께로 식각하게 된다(도 2c 참조).At this time, the etch back is performed, but the W film / Ti / TiN films 23 and 21 of the contact plug are etched to a thickness of 1000 to 2000 Å (see FIG. 2C).
그 다음, 제2콘택마스크를 이용하여 상기 절연막(17)의 타측에 형성되어 있는 상기 Pt막(13)이 노출될때 까지 식각하여 제2콘택홀(25)을 형성한다.Next, the second contact hole 25 is etched using the second contact mask until the Pt layer 13 formed on the other side of the insulating layer 17 is exposed.
다음, 상기 구조의 전표면에 유기용매 예를들어 ACT 용매를 이용하여 습식세정공정을 실시한다.Next, a wet cleaning process is performed on the entire surface of the structure using an organic solvent such as an ACT solvent.
이때, 상기 제1콘택홀(19)에는 W막(23)의 콘택플러그로 인하여 금속이온 확산에 의한 집합누설 전류로 인해 반도체 기판이 손상되는 것을 원칙적으로 방지하게 된다(도 2d 참조).At this time, the first contact hole 19 prevents the semiconductor substrate from being damaged due to the collective leakage current due to the diffusion of metal ions due to the contact plug of the W film 23 (see FIG. 2D).
다음, 상기 구조의 전표면에 Ti/TiN막(27)을 형성한 다음, Al으로 구성된 금속배선(29)을 형성한 다음, 패터닝하여 본 발명의 제조공정을 완료한다(도 2e 참조).Next, a Ti / TiN film 27 is formed on the entire surface of the structure, a metal wiring 29 made of Al is formed, and then patterned to complete the manufacturing process of the present invention (see FIG. 2E).
상기한 바와 같이 본 발명에 따르면, 종속 콘택홀 형성후 텡스텐 금속플러그를 형성하여 금속 이온의 확산방지막을 이용함으로써 습식 공정의 후처리시에 수반되는 오염을 원천적으로 방지하는 반도체 소자의 전기적 특성을 향상시키는 이점이 있다.As described above, according to the present invention, by forming a tungsten metal plug after forming a dependent contact hole and using a diffusion barrier of metal ions, it is possible to fundamentally prevent electrical characteristics of a semiconductor device which prevents contamination accompanying post-wet processing. There is an advantage to improve.
Claims (8)
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Cited By (2)
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KR100806868B1 (en) * | 2006-09-14 | 2008-02-22 | 재단법인서울대학교산학협력재단 | Multiplex primer set specific for PRV PCMV and PCV and method and kit of detecting virus using the same |
US7733312B2 (en) * | 2002-11-19 | 2010-06-08 | Samsung Electronics Co., Ltd | Liquid crystal display with a structure for reducing corrosion of display signal lines |
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1997
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US7733312B2 (en) * | 2002-11-19 | 2010-06-08 | Samsung Electronics Co., Ltd | Liquid crystal display with a structure for reducing corrosion of display signal lines |
KR100806868B1 (en) * | 2006-09-14 | 2008-02-22 | 재단법인서울대학교산학협력재단 | Multiplex primer set specific for PRV PCMV and PCV and method and kit of detecting virus using the same |
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