KR100625388B1 - A method for fabricating metal line of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a metal wiring of a semiconductor device, and forming a contact hole by an etching process using a metal wiring contact mask to form a lower insulating layer with a unit device on the semiconductor substrate and expose the unit device. In order to form a contact plug by sequentially forming an adhesive layer, a diffusion barrier layer, and a contact plug metal layer on the entire surface, and etching the contact plug metal layer on the entire surface, and then forming a metal wiring metal layer on the entire surface of the metal wiring mask. By etching the metal layer for the metal wiring as an etching mask, using the adhesive layer and the diffusion barrier layer as an etch stop layer, and then etching the adhesive layer and the diffusion barrier layer to minimize the damage and loss of the lower insulating layer.

Description

A method for fabricating metal line of semiconductor device

1 is a cross-sectional view showing an etching method of a semiconductor device according to the prior art.

2A and 2B are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to a first embodiment of the prior art;

3A to 3D are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to a third embodiment of the prior art.

4A to 4E are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to a fourth embodiment of the prior art.

5A to 5F are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

11, 21, 31, 41, 51: semiconductor substrate 13: etched layer

23, 32, 42, 52: word line 25, 33, 43, 53: lower insulating layer

27, 37, 45, 57a: Metal layer for metal wiring 29, 38, 46, 59: Photosensitive film pattern

35, 56: contact plug 39, 47, 57b: metal wiring

34, 44, 55: metal layer for contact plug 36: adhesive layer and diffusion barrier layer                 

58a: insulating film for hard mask 58b: insulating film for hard mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method of a semiconductor device, and more particularly, to a method of preventing loss of a lower insulating layer by using a diffusion barrier layer and an adhesive layer as an etch stop layer in a metal wiring forming process of a double structure of lines and contact plugs.

Conventional dry etching technology for semiconductor manufacturing process is composed of the etching process for the etching layer and the transient etching process starting from the time when the lower layer begins to enter.

The transient etching process aims at eliminating the etching target layer partially remaining due to the loading effect due to the process nonuniformity and the pattern density difference, the lower step, and the non-uniformity of the composition to be etched.

The transient etching process time is usually performed in the form of an additional etching process in the range of 30 to 100% based on the process time of the etching target layer.

Increasing the thickness of the etching target layer also increases the thickness of the residues remaining after the etching process, thereby increasing the overetch time. The transient etching process is excessively overburdened with some lower layer loss for the purpose of ensuring a clear residue.

However, in the etching process, since the etching of the etching target layer is completed and the lower layer is exposed, additional etching proceeds from the beginning of the excessive etching, thereby increasing the loss of the lower layer. In order to minimize the loss of the lower layer by reducing the loss of the lower layer, most of the transient etching process is set up separately from the etching process at a high selectivity to the lower layer.

1 is a cross-sectional view illustrating an etching method according to the related art, in which an etching target layer 13 is formed on a semiconductor substrate on which a lower insulating layer is formed, and a photoresist pattern is formed by an exposure and development process using an exposure mask thereon. By using this, the etching target layer 13 is etched, but it is accompanied by excessive etching in order to solve the problem caused by the residue or the micro loading effect.

At this time, during the over-etching process, the portion where the pattern is dense is etched as shallow as ⓐ, and the portion where the pattern is not dense is etched as deep as ⓑ.

2A and 2B are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to a first embodiment of the prior art.

First, the word line 23 is formed on the semiconductor substrate 21 and the unit device is formed on the upper side of the semiconductor substrate 21. Then, the lower insulating layer 25 is formed to planarize the entire upper surface.

In addition, a metal wiring contact hole exposing the word line 23 is formed in the lower insulating layer 25, and a metal layer 27 for metal wiring 27 is embedded.

The photoresist pattern 29 is formed by an exposure and development process using a metal wiring mask (not shown) on the metal layer 27 for metal wiring, and the metal layer 27 for metal wiring 27 is plasma-etched using the mask as the mask. The lower insulating layer 25 is used as a target. At this time, the metal wiring metal layer 27 remains on the lower insulating layer 25.                         

In the plasma etching process, charge accumulation occurs by charge particles in the plasma on an etching target surface exposed to the plasma and an etching cross-section that is exposed as the etching progresses, and the uneven charge accumulation distribution forms an electric field.

During the etching process, since the etching target layer is electrically connected, the plasma induced charge current does not affect the lower insulating material. (FIG. 2A)

Subsequently, in order to remove the residue of the metal layer 27 for metal wiring on the lower insulating layer 25 is accompanied by a transient etching.

Here, in the transient etching process in which the etching target layer starts to be divided according to the pattern during the transient etching, the plasma induced charge current is insulated from the lower electrode by a polarizer-nodheim tunneling phenomenon using the lower substrate as a common electrode due to the potential difference. It will damage the material. This plasma induced damage increases in proportion to the time of the transient etching process. (FIG. 2A, FIG. 2B)

As described above, in the method of forming the metal wiring of the semiconductor device according to the first embodiment of the prior art, the lower insulating layer is etched during the transient etching process, thereby lowering the insulation characteristics of the device and thereby reducing the characteristics and reliability of the semiconductor device. There is a problem.

3A to 3D are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device in accordance with a second embodiment of the prior art, wherein unit devices such as word lines 32, bit lines, and capacitors are disposed on a semiconductor substrate 31; The lower insulating layer 33 is formed on the entire surface.

Next, the lower insulating layer 33 is etched using the metallization contact mask as an etch mask to form the metallization contact hole exposing the word line 32.                         

Next, a metal wiring contact plug metal layer 34 is formed on the entire surface, and is formed using a tungsten layer having excellent embedding characteristics.

Next, the contact plug metal layer 34 is entirely etched to form a contact plug 35 filling the contact hole. In this case, the front etching process is performed by a transient etching process so that the upper portion of the contact hole is exposed to a predetermined thickness.

Next, the adhesive layer and the diffusion barrier layer 36 are sequentially formed on the entire surface, and the metal layer 37 for metal wiring is formed thereon. In this case, the metal layer 37 for metal wiring is formed of an aluminum layer with a small resistance.

Next, a photosensitive film pattern 38 is formed on the metal layer 37 for metal wiring to protect a predetermined portion of the metal wiring.

Subsequently, the metal layer 39, the adhesive layer, and the diffusion barrier layer 36 are etched using the photoresist pattern 38 as an etch mask to form the metal line 39.

As described above, in the method of forming a metal wiring of a semiconductor device according to the second embodiment of the prior art, the electrical wiring of the metal wiring is formed by the adhesive layer and the diffusion barrier layer 36 provided between the metal wiring 39 and the contact plug 35. There is a problem of lowering the resistance characteristics, and there is a problem in that the characteristics of the semiconductor device are deteriorated due to loss of the lower insulating layer 33 and plasma induced damage during the etching process using the metallization mask.

4A to 4E are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to a third embodiment of the prior art.

First, as in the second embodiment, unit devices such as a word line 42, a bit line (not shown), and a capacitor are formed on the semiconductor substrate 41, and a lower insulating layer 43 is formed on the entire surface. do.

Next, the lower insulating layer 43 is etched using the metallization contact mask as an etch mask to form the metallization contact hole exposing the word line 42.

Then, the contact plug metal layer 44 is formed on the entire surface.

Next, the contact plug metal layer 44 is partially etched by the entire surface etching process so that the contact plug metal layer 44 remains on the lower insulating layer 43.

Next, a metal layer 45 for metal wiring is formed on the entire surface, and a photosensitive film pattern 46 is formed on the metal layer 45 for metal wiring to protect a portion intended for metal wiring.

Next, the metal layer 45 is formed by etching the metal layer 45 for metal wiring and the contact plug metal layer 44 having the remaining thickness using the photoresist pattern 46 as an etching mask.

As described above, in the method of forming the metal wiring of the semiconductor device according to the third embodiment of the prior art, since the overetch process is performed on the contact plug metal layer having a predetermined thickness on the lower insulating layer, the loss of the semiconductor substrate and the plasma induction Damage can be minimized, but the over-etching process cannot be performed during the entire surface etching process for leaving the contact plug metal layer on the lower insulating layer, and the remaining contact is caused by the topology of the lower layer and the uniformity of the deposition and etching process. The thickness of the metal layer for the plug and the plasma induced damage and lower insulating layer loss occurring during the subsequent etching stop layer etching process are proportional to each other.

 The present invention, in order to solve the above problems of the prior art, using the adhesive layer and the diffusion barrier layer as an etch stop layer, after completing the excessive etching of the target layer in the etching target layer electrically connected, the etch stop layer It is an object of the present invention to provide an etching method of a semiconductor device by minimizing damage and loss of a lower insulating layer caused by a polar-nodeheim tunneling phenomenon by performing excessive etching with a relatively short process time.

In order to achieve the above object, the etching method of a semiconductor device according to the present invention,

Forming a lower insulating layer having unit devices formed on the semiconductor substrate;

Forming a metal wiring contact hole exposing a word line in the unit device;

Forming an adhesive layer and a diffusion barrier layer as an etch stop layer on the entire surface;

Forming a contact plug on the entire surface, and then forming a contact plug to bury the metal wiring contact hole by performing a front etching process;

Forming a metal layer for metal wiring on the entire surface, and forming a photosensitive film pattern on the metal layer for metal wiring to protect a portion intended for metal wiring;

Forming a metal wiring by etching the metal layer for the metal wiring using the photoresist pattern as an etch mask, and using the adhesive layer and the diffusion barrier layer as an etch stop layer;

Etching the adhesive layer and the diffusion barrier layer by using the photoresist pattern as an etching mask;                     

And including a step of removing the photoresist pattern.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5A to 5F are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

First, unit devices such as a word line 52, a bit line, and a capacitor are formed on the semiconductor substrate 51, and a lower insulating layer 53 is formed on the entire surface.

Next, a metal wiring contact hole for exposing the word line 52 is formed by an etching process using a metal wiring contact mask.

Next, the adhesive layer and the diffusion barrier layer 54 are sequentially formed on the entire surface. At this time, the adhesive layer and the diffusion barrier layer 54 is formed to each 10 ~ 10000Å thickness using a Ti film and a TiN film, and is used as an etch stop layer in a subsequent process.

Next, a contact plug metal layer 55 is formed on the entire surface. The contact plug metal layer 55 is formed of a tungsten layer having excellent embedding characteristics.

Then, the contact plug 36 is formed by removing the contact plug metal layer 55 by the front etching process, and the etching process is performed by using the adhesive layer and the diffusion barrier layer 54 as an etch stop layer. In this case, the etching process is performed by the stock etching process and the transient etching process for the contact plug metal layer 55.

Since the contact plug 56 is electrically connected because the adhesive layer and the diffusion barrier layer 54 exist as the etch stop layer after the etching process, the plasma induced damage and the loss of the lower insulation layer 53 do not occur. By the transient etching process for the metal layer 55, the thickness of the adhesive layer and the diffusion barrier layer 54 can be secured stably. (See FIG. 5A, FIG. 5B)

Next, the metal layer 57a for hard wiring and the insulating layer 58a for hard mask are sequentially formed on the entire surface, and the photoresist pattern 59 for protecting a portion of the hard mask insulating layer 58a, which is intended for metal wiring, is formed on the entire surface. To form. At this time, the hard mask insulating film 58a is formed to have a thickness of 1 to 10000 GPa using an oxide film or a nitride film. The deposition process of the hard mask insulating layer 58a may be omitted. (See Figure 5c)

Next, the hard mask insulating layer 58a is etched using the photoresist pattern 59 as an etch mask to form a hard mask insulating layer pattern 58b. (See FIG. 5D)

Next, the metallization layer 57a is etched using the photoresist layer pattern 59 and the hard mask insulation layer pattern 58b as an etch mask to form the metallization 57b, but the transient etching process is performed in a range of 1 to 300%. Is carried out. At this time, the predetermined thickness of the photoresist layer pattern 59 is lost, and the adhesive layer and the diffusion barrier layer 54 remain due to the high etching selectivity of the metallization metal layer 57a, the adhesive layer, and the diffusion barrier layer 54. Since the metal wiring 57b is electrically connected, the lower insulating layer 53 is not lost and plasma induced damage is also limited. (See Figure 5E)

Next, the adhesive layer and the diffusion barrier layer 54 are etched using the photoresist pattern 59 and the hard mask insulation layer pattern 58b as an etch barrier, and the etching process is performed in the range of 1 to 300%. At this time, the photoresist pattern 59 and the hard mask insulating layer pattern 58b of a predetermined thickness may be lost, and when the adhesive layer and the diffusion barrier layer 54 are used as an etch stop layer, the tungsten layer is etched in the related art. Since the over-etching process for a lower thickness than the stop layer is used, the loss of the lower insulating layer 53 and the plasma induced damage can be minimized. (See Figure 5f)

Next, the remaining photosensitive film pattern 59 and the hard mask insulating film pattern 58b are removed.

As described above, the etching method of the semiconductor device according to the present invention can minimize the plasma induced damage generated in the conductor wiring etching process, and the uneven charge accumulation phenomenon occurring during the etching process and the etching process for the etching target layer. Is an electric field, but since the object to be etched is electrically connected by the lower etch stop layer, it does not affect the lower insulating material, and the damage of the lower insulating layer due to charge accumulation is performed only when etching the relatively thin etch stop layer. As it occurs, the damage is relatively low. Therefore, there is an effect that can prevent the deterioration of characteristics of the semiconductor device.

Claims (9)

Forming a lower insulating layer having unit devices formed on the semiconductor substrate; Forming a metal wiring contact hole exposing a word line in the unit device; Forming an adhesive layer and a diffusion barrier layer as an etch stop layer on the entire surface; Forming a contact plug on the entire surface, and then forming a contact plug to bury the metal wiring contact hole by performing a front etching process; Forming a metal layer for metal wiring on the entire surface, and forming a photosensitive film pattern on the metal layer for metal wiring to protect a portion intended for metal wiring; Forming a metal wiring by etching the metal layer for the metal wiring using the photoresist pattern as an etch mask, and using the adhesive layer and the diffusion barrier layer as an etch stop layer; Etching the adhesive layer and the diffusion barrier layer by using the photoresist pattern as an etching mask; And removing the photosensitive film pattern. The method of claim 1, The adhesive layer is a metal film forming method of a semiconductor device, characterized in that for forming a Ti film 10 to 10000 Å thickness. The method of claim 1, The adhesive layer is a metal wiring forming method of a semiconductor device, characterized in that for forming a TiN film of 10 to 10000 Å thickness. The method of claim 1, The metal layer for forming a contact plug is formed using a tungsten layer. The method of claim 1, The photosensitive film pattern is a metal wiring forming method of a semiconductor device, characterized in that formed in a stacked structure of the insulating film pattern for the hard mask and the photosensitive film pattern. The method of claim 5, wherein The method for forming a metal wiring of a semiconductor device, wherein the insulating layer pattern for the hard mask is formed to have a thickness of 10 to 10000 GPa using a nitride film or an oxide film. The method of claim 1, The contact plug is formed by over-etching the contact plug metal layer in the range of 1 to 300%. The method of claim 1, The metal wiring is formed by over-etching the metal layer for metal wiring in the range of 1 to 300%. The method of claim 1, The adhesive layer and the diffusion barrier layer is removed by over-etching in the range of 1 to 300%.

Images