KR20000045482A - Etching method of semiconductor device - Google Patents
Etching method of semiconductor device Download PDFInfo
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- KR20000045482A KR20000045482A KR1019980062040A KR19980062040A KR20000045482A KR 20000045482 A KR20000045482 A KR 20000045482A KR 1019980062040 A KR1019980062040 A KR 1019980062040A KR 19980062040 A KR19980062040 A KR 19980062040A KR 20000045482 A KR20000045482 A KR 20000045482A
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- 238000005530 etching Methods 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000001052 transient effect Effects 0.000 claims description 12
- 238000001465 metallisation Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000005689 Fowler Nordheim tunneling Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 77
- 238000009825 accumulation Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
Description
본 발명은 반도체소자의 식각방법에 관한 것으로, 특히 플라즈마를 이용하는 전도체 식각공정에 적용하는 기술에 관한 것이다BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of etching semiconductor devices, and more particularly to a technique applied to a conductor etching process using plasma.
기존의 반도체 제조 공정용 건식식각 기술은 피식각층에 대한 식각공정과 하부층이 둘어나기 식각되는 시점부터 시작되는 과도식각공정으로 구성된다.Conventional dry etching technology for semiconductor manufacturing process is composed of the etching process for the etching layer and the transient etching process starting from the point where the lower layer is etched.
과도식각공정은 식각완료시점에서 공정의 불균일성과 패턴 밀도 차이에 의한 로딩효과 ( loading effect ), 하부단차, 식각대상층 조성의 불균일성 등에 의하여 부분적으로 잔존하는 식각대상층의 제거를 목적으로 한다.The transient etching process aims to remove the remaining etching target layer due to the loading effect due to the process nonuniformity and the pattern density difference, the lower step, and the non-uniformity of the composition of the etching target layer.
과도 식각공정 시간은 식각대상층의 공정시간을 기준으로 통상 30 ∼ 100 퍼센트 범위에서 추가 식각공정 형식으로 진행된다.Transient etching process time is usually in the form of additional etching process in the range of 30 to 100 percent based on the process time of the target layer.
식각대상층의 두께가 증가하면 식각 공정후 잔존하는 잔류물의 두께도 증가하므로 과도식각 공정 시간은 증가하게 된다. 과도식각공정은 확실한 잔류물 제거를 목적으로 어느 정도의 하부층 손실을 감수하고 과도하게 진행된다.Increasing the thickness of the etching target layer also increases the thickness of the residues remaining after the etching process, thereby increasing the overetch time. The transient etching process is excessively overburdened with some lower layer loss for the purpose of ensuring a clear residue.
그러나, 식각공정에서 식각대상층의 식각이 완료되어 하부층이 드러난 부분은 과도식각 시작부터 추가식각이 진행되므로 하부층의 손실이 증가하게 된다. 이러한, 하부층의 손실은 하부 구조와의 절연특성을 저하시킴으로써 하부층의 손실을 최소화하기 위하여 대부분의 과도식각공정은 하부층에 대한 선택비가 높은 공정 조건으로 식각공정과 별도로 셋업된다.However, in the etching process, since the etching of the etching target layer is completed and the lower layer is exposed, additional etching proceeds from the beginning of the excessive etching, thereby increasing the loss of the lower layer. In order to minimize the loss of the lower layer by reducing the loss of the lower layer, the most of the transient etching process is set up separately from the etching process with a high selectivity to the lower layer.
도 1 은 종래기술에 따른 식각공정을 도시한 단면도로서, 하부절연층이 형성된 반도체기판 상부에 피식각층(13)을 형성하고 그 상부에 노광마스크를 이용한 노광 및 현상공정으로 감광막패턴을 형성한 다음, 이를 이용하여 상기 피식각층(13)을 식각하되, 잔유물이나 마이크로 로딩 효과로 인한 문제점을 해결하기 위하여 과도식각을 수반한 것이다.1 is a cross-sectional view illustrating an etching process according to the related art, in which an etching target layer 13 is formed on a semiconductor substrate on which a lower insulating layer is formed, and a photoresist pattern is formed by an exposure and development process using an exposure mask thereon. By using this, the etching target layer 13 is etched, which is accompanied by excessive etching in order to solve the problem caused by the residue or the micro loading effect.
이때, 상기 과도식각공정시 패턴이 밀집된 부분은 ⓐ 정도로 얕게 식각되고, 패턴이 밀집되지않은 부분은 ⓑ 정도로 깊게 식각된다.At this time, during the over-etching process, the portion where the pattern is dense is etched as shallow as ⓐ, and the portion where the pattern is not dense is etched as deep as ⓑ.
도 2a 및 도 2b 는 종래기술에 따른 금속배선 식각공정을 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a metallization etching process according to the prior art.
먼저, 반도체기판(21) 상부에 워드라인(23)을 형성하고 그 상측에 단위소자를 형성한 다음, 전체표면상부를 평탄화시키는 하부절연층(25)을 형성한다.First, the word line 23 is formed on the semiconductor substrate 21, and a unit device is formed on the upper side of the semiconductor substrate 21. Then, the lower insulating layer 25 is formed to planarize the entire upper surface.
그리고, 상기 상기 워드라인(23)을 노출시키는 금속배선 콘택홀을 상기 하부절연층(25)에 형성하고 이를 매립하는 금속배선 물질층(27)을 형성한다.In addition, a metal wiring contact hole exposing the word line 23 is formed in the lower insulating layer 25 and a metal wiring material layer 27 filling the metal wiring contact hole is formed.
그리고, 상기 금속배선 물질층(27) 상부에 금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(29)을 형성하고 이를 마스크로 하여 상기 금속배선 물질층(27)을 플라즈마 식각하되, 상기 하부절연층(25)을 타겟으로 하여 실시한다. 이때, 상기 하부절연층(25) 상부에 상기 금속배선 물질층(27)이 잔류하게 된다.Then, the photoresist pattern 29 is formed on the metal wiring material layer 27 by an exposure and development process using a metal wiring mask (not shown), and the metal wiring material layer 27 is plasma-etched using the mask. The lower insulating layer 25 is used as a target. In this case, the metal wiring material layer 27 remains on the lower insulating layer 25.
여기서, 상기 플라즈마 식각공정은 플라즈마에 노출되는 식각대상 표면과 식각이 진행되면서 드러나는 식각 단면에 플라즈마 내의 전하 입자들에 의하여 전하 축적현상이 발생하게 되며, 불균일한 전하 축적 분포는 전계를 형성한다.In the plasma etching process, charge accumulation occurs by charge particles in the plasma on an etching target surface exposed to the plasma and an etching cross-section that is exposed as the etching progresses, and the uneven charge accumulation distribution forms an electric field.
식각 공정 진행 중에는 식각 대상층이 전기적으로 연결되어 있는 상태이므로 플라즈마 유도 전하 전류가 하부 절연물질에 영향을 주지 않는다. (도 2a)During the etching process, since the etching target layer is electrically connected, the plasma induced charge current does not affect the lower insulating material. (FIG. 2A)
그 다음에, 상기 하부절연층(25) 상부의 금속배선 물질층(27)의 잔유물을 제거하기 위하여 과도식각을 수반한다.Subsequently, an excessive etching is performed to remove residues of the metallization material layer 27 on the lower insulating layer 25.
여기서, 상기 과도식각을 진행시 식각 대상층이 패턴 별로 구분되기 시작하는 과도 식각 공정에서 전위차에 의한 하부기판을 공통 전극으로 하는 폴러-노드하임 터널링 ( fowler nordheim tunneling ) 현상으로 플라즈마 유도전하 전류는 하부 절연물질에 손상을 주게 된다. 이러한 플라즈마 유도손상은 과도식각 공정의 시간에 비례하여 증가한다. (도 2a, 도 2b)Here, in the transient etching process where the etching target layer starts to be divided into patterns according to the transient etching, the plasma induced charge current is lower insulated due to a fowler nordheim tunneling phenomenon using the lower substrate as a common electrode due to the potential difference. It will damage the material. This plasma induced damage increases in proportion to the time of the transient etching process. (FIG. 2A, FIG. 2B)
상기한 바와같이 종래기술에 따른 반도체소자의 식각방법은, 과도식각공정시 하부절연층이 식각되어 소자의 절연특성을 저하시키고 그에 따른 반도체소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, the etching method of the semiconductor device according to the related art has a problem in that the lower insulating layer is etched during the transient etching process, thereby lowering the insulation characteristics of the device and thereby degrading the characteristics and reliability of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여,The present invention to solve the above problems of the prior art,
식각 대상층에 대하여 높은 선택비를 갖는 물질로 식각정지층을 형성하고 식각 대상층들이 전기적으로 연결되어 있는 상태에서 식각 대상층에 대한 과도 식각을 완료한 후, 식각 정지층에 대하여 상대적으로 짧은 공정 시간의 과도식각을 진행함으로써 폴러-노드하임 터널링 현상에 의한 하부절연층의 손상 및 손실을 최소화하여 반도체소자의 식각방법을 제공하는데 그 목적이 있다.After the etch stop layer is formed of a material having a high selectivity with respect to the etch target layer and the etch stop layer is electrically connected to the etch stop layer, the etch stop layer is completed. The purpose of the present invention is to provide an etching method of a semiconductor device by minimizing damage and loss of the lower insulating layer due to the polar-nodeheim tunneling phenomenon.
도 1, 도 2a 및 도 2b 는 종래기술의 실시예에 따른 반도체소자의 식각방법을 도시한 단면도.1, 2A and 2B are cross-sectional views illustrating an etching method of a semiconductor device according to an embodiment of the prior art.
도 3a 내지 도 3c 는 본 발명의 제1실시예에 따른 반도체소자의 식각방법을 도시한 단면도.3A to 3C are cross-sectional views illustrating an etching method of a semiconductor device in accordance with a first embodiment of the present invention.
도 4 는 본 발명의 제2실시예에 따른 반도체소자의 식각방법을 도시한 단면도.4 is a cross-sectional view illustrating an etching method of a semiconductor device in accordance with a second embodiment of the present invention.
도 5 는 본 발명의 제3실시예에 따른 반도체소자의 식각방법을 도시한 단면도.5 is a cross-sectional view illustrating an etching method of a semiconductor device according to a third exemplary embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11,21,31 : 반도체기판 13 : 피식각층11, 21, 31: semiconductor substrate 13: etching layer
23,33 : 워드라인 25,35 : 하부절연층23,33 word line 25,35 lower insulating layer
27,39 : 금속배선 물질층 29,41 : 감광막패턴27,39: Metallization material layer 29,41: Photoresist pattern
37 : 반사방지막 51 : 접착층37: antireflection film 51: adhesive layer
53 : 확산방지막53: diffusion barrier
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 식각방법은,In order to achieve the above object, the etching method of a semiconductor device according to the present invention,
반도체기판 상부에 단위소자가 형성된 하부절연층을 형성하는 공정과,Forming a lower insulating layer having unit devices formed on the semiconductor substrate;
상기 단위소자 중에서 워드라인을 노출시키는 금속배선 콘택홀을 형성하는 공정과,Forming a metal wiring contact hole exposing a word line in the unit device;
상기 콘택홀을 포함하는 전체표면상부에 식각정지층을 형성하는 공정과,Forming an etch stop layer on the entire surface including the contact hole;
상기 식각정지층 상부에 금속배선 물질층을 형성하는 공정과,Forming a metallization material layer on the etch stop layer;
상기 금속배선 물질층 상부에 금속배선 마스크를 이용한 노광 및 현상공정으로 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the metal wiring material layer by exposure and development using a metal wiring mask;
상기 감광막패턴을 마스크로하여 상기 금속배선 물질층을 플라즈마식각하되, 과도식각을 수반하여 상기 식각정지층이 노출되도록 실시하는 공정과,Performing plasma etching of the metallization material layer using the photoresist pattern as a mask, and exposing the etch stop layer with transient etching;
연속적으로 상기 식각정지층을 식각하여 상기 워드라인에 접속되는 금속배선을 형성하는 공정을 포함하는 것과,Continuously etching the etch stop layer to form a metal wiring connected to the word line;
상기 식각정지층은 10 ∼ 10000 Å 두께의 텅스텐으로 형성하는 것과,The etch stop layer is formed of tungsten having a thickness of 10 to 10000 kPa,
상기 식각정지층에 대한 과도식각공정은 1 ∼ 300 퍼센트 범위에서 실시하는 것과,The transient etching process for the etch stop layer is performed in the range of 1 to 300 percent,
상기 식각정지층 대신에 식각정지층/접착증의 적층구조로 형성하는 것과,Instead of the etch stop layer to form a laminated structure of etch stop layer / adhesion,
상기 식각정지층은 10 ∼ 10000 Å 두께의 티타늄으로 형성하는 것과,The etch stop layer is formed of titanium having a thickness of 10 to 10000 Å,
상기 식각정지층 대신에 식각정지층/확산방지막/접착증의 적층구조로 형성하는 것과,Forming a laminated structure of an etch stop layer / diffusion barrier film / adhesion instead of the etch stop layer,
상기 확산방지막은 10 ∼ 10000 Å 티타늄질화막으로 형성되는 것을 특징으로 한다.The diffusion barrier is characterized in that formed of 10 to 10000 Å titanium nitride film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3c 는 본 발명의 실시예에 따른 반도체소자의 식각방법을 도시한 단면도이다.3A to 3C are cross-sectional views illustrating an etching method of a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(31) 상부에 활성영역을 정의하는 소자분리막(도시안됨)을 형성하고, 상기 반도체기판의 활성영역에 워드라인(33)을 형성한다.First, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 31, and a word line 33 is formed in the active region of the semiconductor substrate 31.
그리고, 그 상부에 비트라인, 캐패시터등의 단위소자가 구비된 하부절연층(35)을 형성하고 금속배선 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 워드라인(33)을 노출시키는 금속배선 콘택홀을 형성한 다음, 이를 포함한 전체표면상부에 식각정지층(37)을 일정두께 형성하고 상기 콘택홀을 매립하는 금속배선 물질층(39)을 형성한다.In addition, a metal wiring contact exposing the word line 33 by an etching process using a metal wiring contact mask (not shown) is formed on the lower insulating layer 35 provided with unit devices such as bit lines and capacitors thereon. After the hole is formed, an etch stop layer 37 is formed on the entire surface including the hole, and the metal wiring material layer 39 filling the contact hole is formed.
이때, 상기 식각정지층(37)은 10 ∼ 10000 Å 두께로 형성한다.At this time, the etch stop layer 37 is formed to a thickness of 10 to 10000 Å.
그 다음, 상기 금속배선 물질층(39) 상부에 금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(41)을 형성한다. (도 3a)Next, the photoresist pattern 41 is formed on the metallization material layer 39 by an exposure and development process using a metallization mask (not shown). (FIG. 3A)
그 다음, 상기 감광막패턴(41)을 마스크로하여 상기 금속배선 물질층(390을 식각한다. 이때, 상기 식각정지층(37)이 노출될때까지 실시한다.Next, the metal wiring material layer 390 is etched using the photoresist pattern 41 as a mask, and the etching process is performed until the etch stop layer 37 is exposed.
이때, 상기 금속배선 물질층(39)과 식각정지층(37)의 높은 식각선택비 차이로 인하여 식각대상층 패턴들은 전기적으로 연결되어 있으므므로 플라즈마 유도전하전류에 의한 하부절연층의 손상은 제한된다. (도 3b)At this time, the etching target layer patterns are electrically connected due to the difference in the etch selectivity between the metallization material layer 39 and the etch stop layer 37, so that the damage of the lower insulating layer due to the plasma induced charge current is limited. (FIG. 3B)
그 다음, 상기 감광막패턴(41)을 마스크로하여 상기 식각정지층(37)을 식각한다.Next, the etch stop layer 37 is etched using the photoresist pattern 41 as a mask.
이때, 상기 식각대상층인 금속배선 물질층(39) 보다 낮은 두께의 식각정지층을 식각함으로써 플라즈마 유도 전하 전류에 의한 하부절연층(35)의 특성 저하와 하부절연층(35)의 손실을 최소화할 수 있다. (도 3c)At this time, by etching the etch stop layer having a lower thickness than the metal wiring material layer 39, which is the etch target layer, the characteristics of the lower insulating layer 35 due to the plasma induced charge current and the loss of the lower insulating layer 35 can be minimized. Can be. (FIG. 3C)
도 4 와 도 5 는 본 발명의 제2,3 실시예에 따른 반도체소자의 식각방법을 도시한 단면도로서, 식각정지층으로 하부에 접착층(51)을 형성하거나 Ti/TiN의 적층구조로 확산방지막/접착층(53,51)을 형성하여 반도체소자의 특성을 보다 향상시킬 수 있도록 한 것이다.4 and 5 are cross-sectional views illustrating an etching method of semiconductor devices according to embodiments 2 and 3 of the present invention, wherein an etching stop layer forms an adhesive layer 51 at a lower portion, or a diffusion barrier layer having a stacked structure of Ti / TiN. The adhesive layers 53 and 51 are formed to improve the characteristics of the semiconductor device.
이때, 상기 접착층(51)은 상기 10 ∼ 10000 Å 두께의 티타늄막으로 형성하고, 상기 확산방지막(53)은 10 ∼ 10000 Å 두께의 티타늄질화막으로 형성한다.At this time, the adhesive layer 51 is formed of a titanium film having a thickness of 10 to 10000 mm 3, and the diffusion barrier 53 is formed of a titanium nitride film of 10 to 10000 mm 3.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 식각방법은, 전도체 배선 식각공정에 발생하는 플라즈마 유도손상을 최소화할 수 있으며, 식각대상층에 대한 식각공정, 과도 식각 공정 중 발생하는 불균일한 전하축적현상은 전기장을 형성하지만 하부식각 정지층에 의하여 식각대상층이 전기적으로 연결되어 있으므로 하부절연물질에 영향을 주지 않고, 전하축적에 의한 하부절연층의 손상은 상대적으로 두께가 얇은 식각정지층의 식각시에만 발생하므로 상대적으로 손상정도가 낮다. 따라서, 반도체소자의 특성 열화를 방지할 수 있는 효과가 있다.As described above, the etching method of the semiconductor device according to the present invention can minimize the plasma induced damage generated in the conductor wiring etching process, and the uneven charge accumulation phenomenon occurring during the etching process and the etching process for the etching target layer. Is an electric field, but since the object to be etched is electrically connected by the lower etch stop layer, it does not affect the lower insulating material, and the damage of the lower insulating layer due to charge accumulation is performed only when etching the relatively thin etch stop layer. As it occurs, the damage is relatively low. Therefore, there is an effect that can prevent the deterioration of characteristics of the semiconductor device.
Claims (7)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100625388B1 (en) * | 2000-04-04 | 2006-09-18 | 주식회사 하이닉스반도체 | A method for fabricating metal line of semiconductor device |
| KR100632623B1 (en) * | 2002-07-02 | 2006-10-09 | 주식회사 하이닉스반도체 | Metal wiring formation method of semiconductor device |
| KR100915065B1 (en) * | 2002-07-18 | 2009-09-02 | 주식회사 하이닉스반도체 | A method for manufacturing of a Magnetic random access memory |
| KR101128723B1 (en) * | 2004-07-29 | 2012-03-26 | 매그나칩 반도체 유한회사 | Image sensor with removed metal organic residue and method for fabrication thereof |
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1998
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100625388B1 (en) * | 2000-04-04 | 2006-09-18 | 주식회사 하이닉스반도체 | A method for fabricating metal line of semiconductor device |
| KR100632623B1 (en) * | 2002-07-02 | 2006-10-09 | 주식회사 하이닉스반도체 | Metal wiring formation method of semiconductor device |
| KR100915065B1 (en) * | 2002-07-18 | 2009-09-02 | 주식회사 하이닉스반도체 | A method for manufacturing of a Magnetic random access memory |
| KR101128723B1 (en) * | 2004-07-29 | 2012-03-26 | 매그나칩 반도체 유한회사 | Image sensor with removed metal organic residue and method for fabrication thereof |
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