KR100314741B1 - Method for forming metal line in semiconductor device - Google Patents
Method for forming metal line in semiconductor device Download PDFInfo
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- KR100314741B1 KR100314741B1 KR1019950048762A KR19950048762A KR100314741B1 KR 100314741 B1 KR100314741 B1 KR 100314741B1 KR 1019950048762 A KR1019950048762 A KR 1019950048762A KR 19950048762 A KR19950048762 A KR 19950048762A KR 100314741 B1 KR100314741 B1 KR 100314741B1
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- film
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- contact hole
- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 37
- 239000010937 tungsten Substances 0.000 claims abstract description 37
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000010936 titanium Substances 0.000 claims abstract description 22
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 47
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 19
- 238000001020 plasma etching Methods 0.000 claims description 8
- YPSXFMHXRZAGTG-UHFFFAOYSA-N 4-methoxy-2-[2-(5-methoxy-2-nitrosophenyl)ethyl]-1-nitrosobenzene Chemical compound COC1=CC=C(N=O)C(CCC=2C(=CC=C(OC)C=2)N=O)=C1 YPSXFMHXRZAGTG-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000001465 metallisation Methods 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 3
- 239000011135 tin Substances 0.000 abstract 3
- 229910052718 tin Inorganic materials 0.000 abstract 3
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 230000001052 transient effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 하나의 웨이퍼상에 콘택홀 면적이 큰것과 작은것이 공존할 경우, 콘택홀 매립방법을 개선함에 의해 면적이 큰 콘택홀의 저면에 식각 손상되는 것을 방지할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, when a large contact hole area and a small one coexist on one wafer, the etching hole is damaged on the bottom surface of the large contact hole by improving the contact hole filling method. The present invention relates to a method for forming metal wiring of a semiconductor device that can be prevented.
일반적으로, 반도체 소자가 고집적화되어감에 따라 콘택홀의 면적은 작아진다. 이에따라 소자간을 전기적으로 연결하는 금속배선 형성공정시 주 금속배선재료인 알루미늄 또는 알루미늄합금이 콘택홀에서 스텝커버리지가 불량해지고, 또한 콘택면적이 줄어듦에 따라 콘택저항이 증대된다. 이를 해결하기 위하여, 콘택홀을 텅스텐으로 먼저 매립한 후, 알루미늄합금층을 형성하였다. 이와같이 면적이 작은 콘택홀을 텅스텐으로 매립하여 콘택저항을 낮출수 있지만, 콘택홀의 면적이 더욱 작아질 경우 텅스텐 매립방법을 적용한다 하더라도 콘택저항값을 작게 제어할 수 없고, 따라서 콘택홀수를 늘리는 방법으로 콘택저항값을 보상시켜야하므로, 이로인하여 소자의 고집적화에 한계가 있게된다. 그런데 반도체 소자를 제조함에 있어, 하나의 웨이퍼에는 콘택홀 면적이 큰것과 작은 것이 공존하는 경우가 있다. 이와같은 경우 면적이 작은 콘택홀에서 알루미늄합금충의 스텝커버리지를 향상시키기 위하여, 콘택홀의 면적이 큰것과 작은 것을 동시에 텅스텐으로 매립하여야 하는데, 이 경우 큰 면적의 콘택홀에서 문제가 발생되는데, 이를 종래의 금속배선 형성 방법을 설명하기 위해 도시한 제 1a 및 1b 도를 참조하여 설명하기로 한다.In general, the area of the contact hole decreases as the semiconductor device becomes more integrated. Accordingly, in the metal wiring forming process of electrically connecting the elements, step coverage is poor in the contact hole of aluminum or aluminum alloy, which is the main metal wiring material, and the contact resistance is increased as the contact area is reduced. In order to solve this problem, the contact hole was first buried in tungsten, and then an aluminum alloy layer was formed. Although the contact resistance can be lowered by embedding a small contact hole with tungsten as described above, if the contact hole becomes smaller, even if the tungsten embedding method is applied, the contact resistance value cannot be controlled small, thus increasing the number of contact holes. Since the contact resistance value must be compensated, there is a limit to the high integration of the device. However, in manufacturing a semiconductor device, one contact wafer may have a large contact hole area and a small one coexist. In this case, in order to improve the step coverage of the aluminum alloy in the small contact hole, the contact hole having a large area and a small area should be buried in tungsten at the same time. In this case, a problem occurs in the large area of the contact hole. A method of forming metal wirings will be described with reference to FIGS. 1A and 1B.
제 1a 도를 참조하면, 층간 절연막(2)이 실리콘 기판(1)상에 형성되고, 콘택홀 마스크를 사용한 식각공정으로 층간 절연막(2)의 일부분을 식각하여 면적이 작은 제 1 콘택홀(10A)과 면적이 큰 제 2콘택홀(10B)이 동시에 형성된다. 제 1 및 2 콘택홀(10A 및 10B)을 포함한 층간 절연막(2)상에 티타늄막(3), 티타늄나이트라이드막(4) 및 텅스텐층(5)이 순차적으로 형성된다.Referring to FIG. 1A, an interlayer insulating film 2 is formed on a silicon substrate 1 and a portion of the first contact hole 10A having a small area is etched by etching a portion of the interlayer insulating film 2 by an etching process using a contact hole mask. ) And a large second contact hole 10B are formed at the same time. The titanium film 3, the titanium nitride film 4 and the tungsten layer 5 are sequentially formed on the interlayer insulating film 2 including the first and second contact holes 10A and 10B.
제 1b 도를 참조하면, 전면식각공정을 통해 층간 절연막(2)의 표면이 충분히 노출될 때까지 텅스텐층(5), 티타늄나이트라이드막(4) 및 티타늄막(3)이 순차적으로 식각되므로, 이로인하여 제 1 콘택홀(10A)내에는 텅스텐층(5), 티타늄나이트라이드막(4) 및 티타늄막(3)으로 완전히 매립되고, 제 2 콘택홀(10B)내에는 그 측벽에 텅스텐층(5), 티타늄나이트라이드막(4) 및 티타늄막(3)이 스페이서 형태로 남아있게된다. 따라서, 제 1 콘택홀(10A)에서는 콘택저항이 개선됨과 동시에 추후 형성되는 알루미늄합금층의 스텝커버리지를 향상시킬 수 있다. 그런데, 제 1 콘택홀(10A)내를 텅스텐층(5), 티타늄나이트라이드막(4) 및 티타늄막(3)으로 매립시키기 위해서는 과도식각공정이 이루어지는데, 과도식각공정으로 인하여 제 2 콘택홀(10B)의 저면에 식각 손상부(10C)가 생길 우려가 높으며, 식각 손상부(10C)가 생길 경우 소자 동작시 이부분에서 누설전류가 발생되어 소자의 신뢰성을 저하시키게 된다.Referring to FIG. 1B, since the tungsten layer 5, the titanium nitride film 4, and the titanium film 3 are sequentially etched until the surface of the interlayer insulating film 2 is sufficiently exposed through the entire surface etching process, This completely fills the tungsten layer 5, the titanium nitride film 4 and the titanium film 3 in the first contact hole 10A, and the tungsten layer (2) on the sidewall of the second contact hole 10B. 5), the titanium nitride film 4 and the titanium film 3 remain in the form of spacers. Therefore, in the first contact hole 10A, the contact resistance may be improved and the step coverage of the aluminum alloy layer formed later may be improved. However, a transient etching process is performed to fill the first contact hole 10A with the tungsten layer 5, the titanium nitride film 4, and the titanium film 3, but the second contact hole is caused by the transient etching process. There is a high possibility that the etching damage portion 10C may be formed on the bottom surface of 10B. If the etching damage portion 10C is generated, a leakage current is generated at this portion during operation of the device, thereby degrading the reliability of the device.
따라서, 본 발명은 하나의 웨이퍼상에 콘택홀 면적이 큰것과 작은것이 공존할 경우, 콘택홀 매립 방법을 개선함에 의해 면적이 큰 콘택홀의 저면에 식각 손상되는 것을 방지할 수 있는 반도체 소자의 금속배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, in the present invention, when a large contact hole area and a small one coexist on one wafer, the metal wiring of the semiconductor device can be prevented from being etched on the bottom surface of the large contact hole by improving the contact hole filling method. The purpose is to provide a forming method.
이러한 목적을 달성하기 위한 본 발명의 금속배선 형성 방법은 면적이 작은 제 1 콘택홀과 면적이 큰 제 2 콘택홀이 형성된 충간 절연막이 실리콘 시판상에 제공되는 단계; 상기 제 1 및 2 콘택홀을 포함한 상기 층간 절연막상에 티타늄막, 티타늄나이트라이드막 및 텅스텐층이 순차적으로 형성되는 단계; 상기 티타늄막, 상기 티타늄나이트라이드막 및 상기 텅스텐층의 두께를 합한것에 대하여 50 내지 90%범위의 석각 타겟으로 상기 텅스텐층을 식각하는 단계; 및 상기 식각된 텅스텐층상에 알루미늄합금층 및 난반사막을 순차적으로 형성한 후 패턴닝하고, 상기 알루미늄합금층 및 상기 난반사막이 패턴닝됨에 의해 노출되는 부분을 상기 층간 절연막의 표면이 충분히 노출될 때까지 상기 텅스텐층, 상기 티타늄나이트라이드막 및 상기 티타늄막을 순차적으로 식각하여 금속배선을 형성시키는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a metal interconnection forming method comprising: providing an interlayer insulating film having a first contact hole having a small area and a second contact hole having a large area on a silicon commercially available; Sequentially forming a titanium film, a titanium nitride film and a tungsten layer on the interlayer insulating film including the first and second contact holes; Etching the tungsten layer with an incidence target in the range of 50 to 90% relative to the sum of the thicknesses of the titanium film, the titanium nitride film and the tungsten layer; And sequentially patterning an aluminum alloy layer and a diffuse reflection layer on the etched tungsten layer, and patterning the portion of the aluminum alloy layer and the diffuse reflection layer until the surface of the interlayer insulating layer is sufficiently exposed. Forming a metal wiring by sequentially etching the tungsten layer, the titanium nitride film and the titanium film.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 2a 내지 2d 도는 본 발명의 실시예에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위해 도시한 소자의 단면도이다.2A through 2D are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.
제 2a 도를 참조하면, 층간 절연막(12)이 실리콘 기판(11)상에 형성되고, 콘택홀 마스크를 사용한 식각공정으로 층간 절연막(12)의 일부분을 식각하여 면적이 작은 제 1 콘택홀(20A)과 면적이 큰 제 2 콘택홀(20B)이 동시에 형성된다. 제 1 및 2 콘택홀(20A 및 20B)을 포함한 층간 절연막(12)상에 티타늄막(13), 티타늄나이트라이드막(14) 및 텅스텐층(15)이 순차적으로 형성된다.Referring to FIG. 2A, an interlayer insulating film 12 is formed on the silicon substrate 11, and a portion of the interlayer insulating film 12 is etched by an etching process using a contact hole mask to reduce the area of the first contact hole 20A. ) And a large second contact hole 20B are formed at the same time. Titanium film 13, titanium nitride film 14 and tungsten layer 15 are sequentially formed on interlayer insulating film 12 including first and second contact holes 20A and 20B.
상기에서, 티타늄막(13)은 300Å의 두께로 형성되고, 티타늄나이트 라이드막(14)은 1000Å의 두께로 형성되며, 텅스텐층(15)은 5000Å의 두께로 형성된다.In the above description, the titanium film 13 is formed to a thickness of 300 kPa, the titanium nitride film 14 is formed to a thickness of 1000 kPa, and the tungsten layer 15 is formed to a thickness of 5000 kPa.
제 2b 도를 참조하면, 제 2 콘택홀(20A) 저면이 식각손상되는 것을 방지하기위하여, 티타늄막(13), 티타늄나이트라이드막(14) 및 텅스텐층(15)을 SF6와 Ar이 1 : 2~5 의 비율로 혼합된 가스를 사용한 플라즈마 식각공정으로 식각하며, 이때 식각 타겟은 티타늄막(13), 티타늄나이트라이드막(14) 및 텅스텐층(15)의 두께를 합한것에 대하여 50 내지 90% 범위로 한다. 본 발명의 도면에서는 텅스텐층(15)이 어느정도 잔류된 상태가 도시된다.Referring to FIG. 2B, in order to prevent the bottom surface of the second contact hole 20A from being etched, the titanium film 13, the titanium nitride film 14, and the tungsten layer 15 may have SF 6 and Ar 1. : Etch by a plasma etching process using a gas mixed in a ratio of 2 to 5, wherein the etching target is 50 to the total thickness of the titanium film 13, titanium nitride film 14 and tungsten layer 15 90% range. In the drawing of the present invention, the state in which the tungsten layer 15 remains to some extent is shown.
제 2c 도를 참조하면, 1차 식각된 텅스텐층(5)상에 알루미늄합금층 (16) 및 난반사막(17)이 순차적으로 형성된다. 알루미늄합금층(16) 및 난반사막(17)은 금속배선 마스크공정과 Cl2와 BCl2이 1 : 0.1∼1 의 비율로 혼합된 가스를 사용한 플라즈마 식각공정에 의해 패턴닝된다.Referring to FIG. 2C, the aluminum alloy layer 16 and the diffuse reflection film 17 are sequentially formed on the first etched tungsten layer 5. The aluminum alloy layer 16 and the diffuse reflection film 17 are patterned by a metal wiring mask process and a plasma etching process using a gas in which Cl 2 and BCl 2 are mixed at a ratio of 1: 0.1 to 1.
제 2d 도를 참조하면, 알루미늄합금층(16) 및 난반사막(17)이 패턴닝됨에 의해 노출되는 부분을 50 내지 100SCCM의 SF6가스를 사용한 플라즈마 식각공정으로 층간 절연막(12)의 표면이 충분히 노출될 때까지 텅스텐층(15), 티타늄나이트라이드막(14) 및 티타늄막(13)을 순차적으로 식각하여 금속배선을 형성시킨다. 플라즈마 식각공정시 전력값은 50 내지 300W를 사용하며, 압력은 10 내지 100mTorr로 한다.Referring to FIG. 2D, the surface of the interlayer insulating film 12 is sufficiently formed by a plasma etching process using 50 to 100 SCCM of SF 6 gas to expose the portions exposed by the patterning of the aluminum alloy layer 16 and the diffuse reflection film 17. The tungsten layer 15, the titanium nitride film 14 and the titanium film 13 are sequentially etched until they are exposed to form metal wiring. In the plasma etching process, the power value is 50 to 300 W and the pressure is 10 to 100 mTorr.
본 발명의 실시예에 의하면, 하나의 웨이퍼상에 콘택홀 면적이 큰것과 작은것이 공존할 경우, 면적이 작은 콘택홀에서 알루미늄합금층의 스텝커버리지를 향상시키고, 콘택저항을 낮추기 위하여, 면적이 큰것과 작은 콘택홀을 포함한 웨이퍼상에 텅스텐층을 형성하고, 면적이 큰 콘택홀의 저면이 식각 손상되는 것이 방지되도록 식각 타겟을 맞추어 텅스텐층을 식각한다.According to an embodiment of the present invention, when a large contact hole area and a small one coexist on one wafer, in order to improve the step coverage of the aluminum alloy layer in the small contact hole and to lower the contact resistance, the area is large. And a tungsten layer are formed on the wafer including the small contact hole, and the tungsten layer is etched by aligning the etch target to prevent the bottom surface of the large contact hole from being etched.
따라서, 본 발명은 웨이퍼에 형성되는 콘택홀의 면적 크기에 관계없이 텅스텐 에치백공정을 실시할 수 있어, 콘택저항을 개선할 수 있고, 소자의 수율을 증대시킬 수 있다.Therefore, the present invention can perform a tungsten etch back process irrespective of the area size of the contact hole formed in the wafer, thereby improving the contact resistance and increasing the yield of the device.
제 1a 및 1b 도는 종래의 금속배선 형성방법을 설명하기 위해 도시한 소자의 단면도.1A and 1B are cross-sectional views of a device shown for explaining a conventional metal wiring forming method.
제 2a 내지 2d 도는 본 발명의 실시예에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위해 도시한 소자의 단면도.2A through 2D are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1, 11: 실리콘 기판 2,12: 층간 절연충1, 11: Silicon Substrate 2,12: Interlayer Insulation
3, 13: 티타늄막 4, 14: 티타늄나이트라이드막3, 13: titanium film 4, 14: titanium nitride film
5, 15: 텅스텐층 16: 알루미늄합금층5, 15: tungsten layer 16: aluminum alloy layer
17: 난반사막 10A, 20A: 제 1 콘택홀17: diffuse reflection film 10A, 20A: 1st contact hole
10B, 20B: 제 2 콘택홀 10C: 식각 손상부10B and 20B: second contact hole 10C: etching damaged part
Claims (6)
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| KR1019950048762A KR100314741B1 (en) | 1995-12-12 | 1995-12-12 | Method for forming metal line in semiconductor device |
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| KR1019950048762A KR100314741B1 (en) | 1995-12-12 | 1995-12-12 | Method for forming metal line in semiconductor device |
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