KR100560292B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR100560292B1 KR100560292B1 KR1019980060331A KR19980060331A KR100560292B1 KR 100560292 B1 KR100560292 B1 KR 100560292B1 KR 1019980060331 A KR1019980060331 A KR 1019980060331A KR 19980060331 A KR19980060331 A KR 19980060331A KR 100560292 B1 KR100560292 B1 KR 100560292B1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 85
- 239000002184 metal Substances 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 35
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 229910052721 tungsten Inorganic materials 0.000 claims description 14
- 239000010937 tungsten Substances 0.000 claims description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- -1 tungsten nitride Chemical class 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims 2
- 239000010410 layer Substances 0.000 description 15
- 238000005530 etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002736 metal compounds Chemical class 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
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Abstract
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 콘택홀이 매립되도록 제 1 금속을 증착한 후 상기 제 1 금속층상에 확산 방지막 및 제 2 금속층을 순차적으로 형성하므로써 접합부와 금속배선 또는 금속배선간의 접촉 저항이 효과적으로 감소되어 소자의 전기적 특성이 향상될 수 있는 반도체 소자의 금속배선 형성 방법이 개시된다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and by depositing a first metal so as to fill a contact hole and then sequentially forming a diffusion barrier and a second metal layer on the first metal layer, the junction part, the metal wiring, or the metal wiring. Disclosed is a method of forming metal wirings in a semiconductor device in which contact resistance between the electrodes is effectively reduced to improve electrical characteristics of the device.
Description
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 특히 콘택홀이 매립되도록 제 1 금속을 증착한 후 상기 제 1 금속층상에 확산 방지막 및 제 2 금속층을 순차적으로 형성하므로써 소자의 전기적 특성이 향상될 수 있도록 한 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, by depositing a first metal to fill a contact hole and then sequentially forming a diffusion barrier and a second metal layer on the first metal layer, the electrical characteristics of the device are improved. The present invention relates to a method for forming metal wiring of a semiconductor device.
일반적으로 반도체 소자의 제조 공정에서 금속배선은 텅스텐(W), 알루미늄(Al) 등과 같은 금속으로 이루어지며, 알루미늄(Al)은 스퍼터링(Sputtering) 방법으로, 그리고 텅스텐(W)은 화학기상증착(CVD) 방법으로 각각 증착된다.In general, in the semiconductor device manufacturing process, the metal wiring is made of metal such as tungsten (W), aluminum (Al), aluminum (Al) by sputtering, and tungsten (W) by chemical vapor deposition (CVD). Respectively) by the method.
이러한 알루미늄(Al)은 2.7 내지 3.0 μΩCm의 비저항치를 가지며, 텅스텐(W)은 10 내지 12 μΩCm의 비저항치를 갖는다. 그러므로 소자의 신호전달 속도를 증가시키기 위해서는 배선의 자체 저항을 감소시켜야 하기 때문에 금속배선으로 비저항치가 작은 알루미늄(Al)을 주로 사용하며, 텅스텐(W)은 우수한 매립특성을 가지는 장점을 이용하여 미세한 콘택홀을 매립시키는 데 사용한다. 그러면 종래 반도체 소자의 금속배선 형성 방법을 도 1a 내지 1c를 참조하여 설명하기로 한다.Such aluminum (Al) has a resistivity of 2.7 to 3.0 μΩCm, and tungsten (W) has a resistivity of 10 to 12 μΩCm. Therefore, in order to increase the signal transmission speed of the device, it is necessary to reduce the resistance of the wiring itself. Therefore, aluminum (Al), which has a small specific resistance, is mainly used for metal wiring, and tungsten (W) has a fine contact by using the advantage of having excellent buried characteristics. Used to bury the hole. Next, a method of forming metal wirings of a conventional semiconductor device will be described with reference to FIGS. 1A to 1C.
도 1a 내지 1c는 종래 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도로서,1A to 1C are cross-sectional views of a device for explaining a method of forming metal wirings of a conventional semiconductor device.
도 1a는 접합부(2)가 형성된 반도체 기판(1)상에 절연막(3)을 형성한 후 상기 접합부(2)의 소정 부분이 노출되도록 상기 절연막(3)을 패터닝하여 콘택홀(4)을 형성하고, 전체 상부면에 확산 방지막(5)을 형성한 상태의 단면도인데, 반도체 소자의 고집적화에 따른 콘택홀의 단차 증가로 인하여 상기 확산 방지막(5)의 층덮힘이 불량해진다. 그리고 이에 따라 상기 콘택홀(4) 입구에서 상기 확산 방지막(5)이 두껍게 증착되어 상기 콘택홀(4)의 입구가 막히는 오버행(Over-hang) 현상이 발생된다.1A illustrates that after forming the insulating film 3 on the semiconductor substrate 1 on which the junction part 2 is formed, the insulating film 3 is patterned to expose a predetermined portion of the junction part 2 to form the contact hole 4. In addition, the diffusion barrier film 5 is formed on the entire upper surface, and the layer covering of the diffusion barrier film 5 is poor due to an increase in the step height of the contact hole due to the high integration of the semiconductor device. As a result, the diffusion barrier 5 is thickly deposited at the inlet of the contact hole 4, thereby causing an over-hang phenomenon in which the inlet of the contact hole 4 is blocked.
도 1b는 상기 콘택홀(4)이 매립되도록 전체 상부면에 제 1 금속(6)을 증착한 상태의 단면도로서, 상기 제 1 금속(6)으로는 매립 특성이 우수한 텅스텐(W)을 사용한다. 그런데 상기와 같이 상기 콘택홀(4) 입구에 두껍게 증착된 상기 확산 방지막(5)에 의해 상기 제 1 금속(6)이 상기 콘택홀(4)내에 완전히 매립되지 않고 콘택홀(4)의 저면부와 입구에만 증착되는 현상이 발생된다. 따라서 상기 콘택홀(4)내에는 보이드(Void; 7)가 생성된다.FIG. 1B is a cross-sectional view of a state in which the first metal 6 is deposited on the entire upper surface of the contact hole 4 so that the contact hole 4 is embedded. Tungsten (W) having excellent filling characteristics is used as the first metal 6. . However, as described above, the first metal 6 is not completely embedded in the contact hole 4 by the diffusion barrier 5 deposited at the entrance of the contact hole 4, and the bottom portion of the contact hole 4 is not included. Deposition occurs only at the inlet and the inlet. Therefore, a void 7 is generated in the contact hole 4.
도 1c는 상기 확산 방지막(5)이 노출되는 시점까지 상기 제 1 금속(6)을 식각(Etchback)하여 상기 콘택홀(4)내에 금속 플러그(6A)가 형성되도록 한 후 전체 상부면에 알루미늄(Al)과 같은 제 2 금속(8)을 증착한 상태의 단면도인데, 이후 상기 제 2 금속(8) 및 확산 방지막(5)을 패터닝하여 금속배선을 형성한다. 그런데 상기 도 1b에 도시된 바와 같이 오버행이 발생된 상태에서 식각 공정이 실시되기 때문에 상기 콘택홀(4) 입구에 증착된 상기 제 1 금속(6)이 이때 거의 식각되거나 소량만 잔류되어 상기 금속 플러그(6A)의 모양이 불량해진다.FIG. 1C shows that the metal plug 6A is formed in the contact hole 4 by etching back the first metal 6 until the diffusion barrier layer 5 is exposed. A cross-sectional view of a state in which a second metal 8, such as Al) is deposited, is then patterned to form a metal wiring by patterning the second metal 8 and the diffusion barrier film 5. However, since the etching process is performed in a state where an overhang occurs as shown in FIG. 1B, the first metal 6 deposited at the inlet of the contact hole 4 is almost etched or only a small amount of metal remains. The shape of 6A becomes poor.
그러므로 종래의 방법으로 금속배선을 형성하는 경우 상기 금속 플러그(6A)의 형상이 불량해지고, 내부에 보이드(7)가 존재하게 되어 상기 제 2 금속(8)과 접합부(2)간의 전기적 접촉 저항이 증가된다. 그리고 이에 의해 소자의 전기적 특성 및 신호의 전달 속도가 저하된다.Therefore, when the metal wiring is formed by the conventional method, the shape of the metal plug 6A is poor, and the void 7 is present therein, so that the electrical contact resistance between the second metal 8 and the junction 2 is reduced. Is increased. As a result, the electrical characteristics of the device and the transmission speed of the signal are lowered.
또한, 종래의 방법을 이용하는 경우 후속 열처리 공정시 상기 제 2 금속(8)과 금속 플러그(6A)의 계면에 금속 화합물이 생성되어 금속배선의 접촉 저항이 더욱 증가할 뿐만아니라, 금속배선의 변형이 야기된다. 이는 350 ℃ 이상의 온도가 되면 알루미늄(Al)과 텅스텐(W)의 반응에 의해 계면에 텅스텐-알루미늄 화합물이 생성되기 때문이다.In addition, in the case of using the conventional method, a metal compound is formed at the interface between the second metal 8 and the metal plug 6A during the subsequent heat treatment process, so that the contact resistance of the metal wiring is further increased, and the deformation of the metal wiring is further increased. Is caused. This is because a tungsten-aluminum compound is formed at the interface by the reaction of aluminum (Al) and tungsten (W) when the temperature is higher than 350 ° C.
따라서 본 발명은 콘택홀이 매립되도록 제 1 금속을 증착한 후 상기 제 1 금속층상에 확산 방지막 및 제 2 금속층을 순차적으로 형성하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속배선 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention provides a method for forming a metal wiring in a semiconductor device that can solve the above-mentioned disadvantages by sequentially forming a diffusion barrier and a second metal layer on the first metal layer after depositing a first metal to fill a contact hole. Its purpose is to.
상기한 목적을 달성하기 위한 본 발명은 반도체 기판에 형성된 접합부의 소정 부분이 노출되도록 절연막에 콘택홀을 형성한 후 실시하는 반도체 소자의 금속배선 형성 방법에 있어서, 상기 반도체 기판의 전체 상부면에 제 1 확산 방지막을 형성한 후 상기 콘택홀이 매립되도록 상기 제 1 확산 방지막상에 제 1 금속을 증착하되 상기 콘택홀 지름의 1/2 두께로 증착하는 단계와, 상기 단계로부터 상기 제 1 금속상에 제 2 확산 방지막을 형성하는 단계와, 상기 단계로부터 상기 확산 방지막상에 제 2 금속 및 반사 방지막을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 반사 방지막, 제 2 금속, 제 2 확산 방지막, 제 1 금속 및 제 1 확산 방지막을 순차적으로 패터닝하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a metal wiring of a semiconductor device, which is performed after forming a contact hole in an insulating film so that a predetermined portion of a junction portion formed on a semiconductor substrate is exposed. After forming a diffusion barrier layer, depositing a first metal on the first diffusion barrier layer so that the contact hole is buried, and depositing a thickness of 1/2 of the diameter of the contact hole; Forming a second diffusion barrier film, and sequentially forming a second metal and an antireflection film on the diffusion barrier film from the step; and from the step, the antireflection film, the second metal, the second diffusion barrier film, and the first And sequentially patterning the metal and the first diffusion barrier layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 2c는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도로서,2A through 2C are cross-sectional views of devices for describing a method for forming metal wirings of a semiconductor device according to the present invention.
도 2a는 접합부(12)가 형성된 반도체 기판(11)상에 절연막(13)을 형성한 후 상기 접합부(12)의 소정 부분이 노출되도록 상기 절연막(13)을 패터닝하여 콘택홀(14)을 형성하고, 전체 상부면에 제 1 확산 방지막(15)을 형성한 상태의 단면도로서, 상기 제 1 확산 방지막(15)은 접합부와 금속층간의 접촉 저항을 감소시킬 수 있는 티타늄(Ti)과 접착층(Glue Layer) 역할을 하는 티타늄 질화막(TiN)을 순차적으로 증착하여 형성한다.2A illustrates that after forming the insulating layer 13 on the semiconductor substrate 11 on which the junction 12 is formed, the insulating layer 13 is patterned to expose a predetermined portion of the junction 12 to form the contact hole 14. The first diffusion barrier 15 is a cross-sectional view of the first diffusion barrier 15 formed on the entire upper surface. The first diffusion barrier 15 is formed of titanium (Ti) and an adhesive layer (Glue), which may reduce contact resistance between the junction part and the metal layer. It is formed by sequentially depositing a titanium nitride film (TiN) serving as a layer).
도 2b는 상기 콘택홀(14)이 매립되도록 전체 상부면에 텅스텐(W)과 같은 제 1 금속(16)을 증착한 후 상기 제 1 금속(16)상에 제 2 확산 방지막(17)을 형성한 상태의 단면도로서, 이때 상기 제 1 금속(16)의 두께는 상기 콘택홀(14) 지름의 1/2, 예를들어 500 내지 3000 Å이 되도록 한다. 이는 알루미늄(Al)보다 비저항치가 큰 텅스텐(W)의 두께를 감소시켜야 금속배선 전체의 두께가 감소되고, 이에 의해 금속배선의 자체 저항이 감소될 수 있으며, 금속배선 패터닝시 식각 공정이 용이해질 수 있기 때문이다.2B illustrates depositing a first metal 16 such as tungsten (W) on the entire upper surface of the contact hole 14 to fill the second hole, and then forming a second diffusion barrier 17 on the first metal 16. In this state, the thickness of the first metal 16 is 1/2 of the diameter of the contact hole 14, for example, 500 to 3000 mm. It is necessary to reduce the thickness of tungsten (W), which has a specific resistance higher than that of aluminum (Al), thereby reducing the thickness of the entire metal wiring, thereby reducing the self resistance of the metal wiring, and facilitating the etching process when patterning the metal wiring. Because there is.
도 2c는 상기 제 1 금속(16)상에 제 2 확산 방지막(17), 제 2 금속(18) 및 반사 방지막(19)을 순차적으로 증착한 상태의 단면도로서, 상기 제 2 확산 방지막(17)은 질소 또는 암모니아 가스 분위기에서 텅스텐(W)을 타켓으로 한 스퍼터링 방법 또는 WF6, N2 및 H2 가스를 이용한 화학기상증착(CVD) 방법을 이용하거나, 질소 또는 암모니아 플라즈마 상태에서 텅스텐(W)의 표면을 질화시키는 방법 등을 이용하여 형성하며, 그 두께는 50 내지 500 Å이 되도록 한다. 또한, 상기 제 2 금속(18)은 스퍼터링 방법으로 알루미늄(Al)을 3000 내지 10000 Å의 두께로 증착하여 형성한다.FIG. 2C is a cross-sectional view of sequentially depositing a second diffusion barrier 17, a second metal 18, and an antireflection layer 19 on the first metal 16. The second diffusion barrier 17 is shown in FIG. Using a sputtering method targeting tungsten (W) in a nitrogen or ammonia gas atmosphere or a chemical vapor deposition (CVD) method using WF 6 , N 2 and H 2 gases, or tungsten (W) in a nitrogen or ammonia plasma state. It is formed using a method such as nitriding the surface of the, and the thickness is to be 50 to 500 kPa. In addition, the second metal 18 is formed by depositing aluminum (Al) to a thickness of 3000 to 10000 kPa by the sputtering method.
이후, 상기 반사 방지막(19), 제 2 금속(18), 제 2 확산 방지막(17), 제 1 금속(16) 및 제 1 확산 방지막(15)을 순차적으로 패터닝하여 금속배선을 형성한다.Thereafter, the anti-reflection film 19, the second metal 18, the second diffusion barrier 17, the first metal 16, and the first diffusion barrier 15 are sequentially patterned to form metal wiring.
상술한 바와 같이 본 발명에 의하면 첫째, 상기 제 1 금속(16)을 증착한 후 금속 플러그를 형성하기 위한 식각 공정이 실시되지 않으므로 공정이 단순해지며, 둘째, 상기 제 1 금속(16)의 증착 두께를 조절하므로써 상기 콘택홀(14)내에 제 1 금속(16)이 완전히 매립될 수 있다. 또한 세째, 상기 제 1 금속(16)과 제 2 금속(18)의 사이에 제 2 확산 방지막(17)을 형성하므로써 후속 열처리 공정시 금속 화합물의 생성이 방지된다. 따라서 본 발명을 이용하여 금속배선을 형성하면 접합부와 금속배선 또는 금속배선간의 접촉 저항이 효과적으로 감소되어 소자의 전기적 특성이 향상될 수 있다.As described above, according to the present invention, first, since the etching process for forming the metal plug is not performed after the deposition of the first metal 16, the process is simplified. Second, the deposition of the first metal 16 is performed. By adjusting the thickness, the first metal 16 may be completely embedded in the contact hole 14. Third, the formation of the second diffusion barrier layer 17 between the first metal 16 and the second metal 18 prevents the formation of the metal compound during the subsequent heat treatment process. Therefore, when the metal wiring is formed using the present invention, the contact resistance between the junction and the metal wiring or the metal wiring can be effectively reduced, thereby improving the electrical characteristics of the device.
도 1a 내지 1c는 종래 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a metal wiring formation method of a conventional semiconductor device.
도 2a 내지 2c는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of devices for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 및 11: 반도체 기판 2 및 12: 접합부1 and 11: semiconductor substrates 2 and 12 junctions
3 및 13: 절연막 4 및 14: 콘택홀3 and 13: insulating film 4 and 14: contact hole
5: 확산 방지막 6 및 16: 제 1 금속5: diffusion barrier 6 and 16: first metal
6A: 금속 플러그 7: 보이드6A: Metal Plug 7: Void
8 및 18: 제 2 금속 15 및 17: 제 1 및 제 2 확산 방지막8 and 18: second metal 15 and 17: first and second diffusion barrier films
19: 반사 방지막19: antireflection film
Claims (9)
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| KR1019980060331A KR100560292B1 (en) | 1998-12-29 | 1998-12-29 | Metal wiring formation method of semiconductor device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03180030A (en) * | 1989-12-08 | 1991-08-06 | Fujitsu Ltd | Semiconductor device |
| JPH0418760A (en) * | 1989-02-20 | 1992-01-22 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| KR970052277A (en) * | 1995-12-18 | 1997-07-29 | 문정환 | Metal wiring formation method |
| KR980005442A (en) * | 1996-06-12 | 1998-03-30 | 문정환 | Metal wiring formation method |
| KR19980048961A (en) * | 1996-12-18 | 1998-09-15 | 김영환 | Metal contact method of semiconductor device |
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1998
- 1998-12-29 KR KR1019980060331A patent/KR100560292B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0418760A (en) * | 1989-02-20 | 1992-01-22 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH03180030A (en) * | 1989-12-08 | 1991-08-06 | Fujitsu Ltd | Semiconductor device |
| KR970052277A (en) * | 1995-12-18 | 1997-07-29 | 문정환 | Metal wiring formation method |
| KR980005442A (en) * | 1996-06-12 | 1998-03-30 | 문정환 | Metal wiring formation method |
| KR19980048961A (en) * | 1996-12-18 | 1998-09-15 | 김영환 | Metal contact method of semiconductor device |
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