KR20010004728A - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR20010004728A KR20010004728A KR1019990025442A KR19990025442A KR20010004728A KR 20010004728 A KR20010004728 A KR 20010004728A KR 1019990025442 A KR1019990025442 A KR 1019990025442A KR 19990025442 A KR19990025442 A KR 19990025442A KR 20010004728 A KR20010004728 A KR 20010004728A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 텅스텐 플러그를 형성하기 위한 전면 식각 공정의 식각 정지층을 층간 절연막으로 변형하고, 금속 배선층으로 텅스텐막을 이용하여 반도체 소자의 수율을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, the etching stop layer of the front surface etching process for forming a tungsten plug can be transformed into an interlayer insulating film, and the yield of the semiconductor device can be improved by using a tungsten film as the metal wiring layer. A metal wiring formation method of a semiconductor element which exists.
현재 VLSI 반도체 소자의 금속 배선 공정에는 높은 애스펙트비(aspect ratio)를 갖는 금속 콘택을 매립하기 위해 텅스텐 플러그 공정이 적용되고 있다.Currently, a tungsten plug process is applied to a metal wiring process of a VLSI semiconductor device to fill a metal contact having a high aspect ratio.
그럼, 텅스텐 플러그를 이용한 종래의 금속 배선 형성 방법을 도 1(a) 내지 도 1(c)를 이용하여 설명하면 다음과 같다.Then, a conventional metal wiring forming method using a tungsten plug will be described with reference to FIGS. 1 (a) to 1 (c).
도 1(a)를 참조하면, 소정의 공정을 통해 하부 구조가 형성된 반도체 기판 (11) 상부에 층간 절연막(12)을 형성한다. 층간 절연막(12)의 선택된 영역을 식각하여 반도체 기판(11)의 소정 영역을 노출시키는 콘택 홀을 형성한다. 콘택 홀을 포함한 전체 구조 상부에 Ti/TiN막으로 장벽 금속층(13)을 형성한다. 콘택 홀이 매립되도록 전체 구조 상부에 텅스텐막(14)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a semiconductor substrate 11 on which a lower structure is formed through a predetermined process. The selected region of the interlayer insulating layer 12 is etched to form a contact hole exposing a predetermined region of the semiconductor substrate 11. The barrier metal layer 13 is formed of a Ti / TiN film on the entire structure including the contact hole. A tungsten film 14 is formed on the entire structure so that the contact hole is filled.
도 1(b)는 장벽 금속층(13)의 상부, 즉 TiN막이 노출되도록 텅스텐막(14)을 전면 식각하여 텅스텐 플러그를 형성한 상태의 단면도이다.FIG. 1B is a cross-sectional view of a top surface of the barrier metal layer 13, that is, a tungsten plug 14 formed by etching the entire surface of the tungsten film 14 to expose the TiN film.
도 1(c)는 전체 구조 상부에 웨팅층(15)으로 Ti막 또는 Ti/TiN막을 형성한 후 금속 배선층으로 알루미늄층(16)을 형성한 상태의 단면도이다.FIG. 1C is a cross-sectional view of a state in which an aluminum layer 16 is formed of a metal wiring layer after a Ti film or a Ti / TiN film is formed of a wetting layer 15 on the entire structure.
그런데, 상기와 같은 텅스텐 플러그를 사용하는 금속 배선 형성 방법에서 최종 금속 배선층으로 사용되는 알루미늄층의 높은 반사율 때문에 금속 배선의 선폭이 0.25㎛ 이하로 감소하면 난반사로 인하여 리소그라피 공정에서 배선 자체가 확정되기 매우 어렵다.However, in the metal wiring forming method using the tungsten plug as described above, when the line width of the metal wiring decreases to 0.25 μm or less due to the high reflectivity of the aluminum layer used as the final metal wiring layer, the wiring itself is very determined in the lithography process due to diffuse reflection. it's difficult.
상기한 문제점을 해결하기 위해 텅스텐을 증착하여 바로 금속 배선을 형성하는 방법을 생각할 수 있는데, 이를 도 2(a) 내지 도 2(c)를 이용하여 설명하면 다음과 같다.In order to solve the above problems, a method of directly forming a metal wiring by depositing tungsten can be considered. This will be described with reference to FIGS. 2 (a) to 2 (c).
도 2(a)를 참조하면, 소정의 공정을 통해 하부 구조가 형성된 반도체 기판 (21) 상부에 제 1 층간 절연막(22)을 형성한다. 제 1 층간 절연막(22)의 선택된 영역을 식각하여 반도체 기판(21)의 소정 영역을 노출시키는 콘택 홀을 형성한다. 콘택 홀을 포함한 전체 구조 상부에 Ti/TiN막으로 장벽 금속층(23)을 형성한다. 콘택 홀이 매립되도록 전체 구조 상부에 텅스텐막(24)을 형성한다.Referring to FIG. 2A, the first interlayer insulating layer 22 is formed on the semiconductor substrate 21 on which the lower structure is formed through a predetermined process. The selected region of the first interlayer insulating layer 22 is etched to form a contact hole exposing a predetermined region of the semiconductor substrate 21. The barrier metal layer 23 is formed of a Ti / TiN film on the entire structure including the contact hole. A tungsten film 24 is formed on the entire structure so that the contact hole is filled.
도 2(b)는 텅스텐막(14)을 패터닝하여 장벽 금속층(23)의 상부, 즉 TiN막을 노출시켜 금속 배선을 형성한 상태의 단면도이다.FIG. 2B is a cross-sectional view of the metal wiring formed by patterning the tungsten film 14 to expose the upper portion of the barrier metal layer 23, that is, the TiN film.
상기와 같은 공정으로 금속 배선을 형성하면 금속 배선을 형성한 후 제 2 층간 절연막 증착시 금속 배선 사이가 갭필되지 않아 금속 배선 사이에 보이드가 발생한다. 즉, 텅스텐을 이용한 금속 배선 형성 공정은 텅스텐 플러그를 이용한 금속 배선 공정에 비해 스텝커버러지가 떨어지기 때문에 콘택을 움푹 패인 곳없이 완전히 매립하여 안정적인 소자의 특성을 얻기 위해서는 적어도 3000Å 이상의 텅스텐막을 증착해야 한다. 따라서, 금속 배선이 형성되고 나면 배선 사이에 깊고 좁은 골이 생기게 되어 이를 채우기 매우 어렵게 된다.When the metal lines are formed by the above process, voids are generated between the metal lines because the metal lines are not gap-filled during the deposition of the second interlayer insulating film after the metal lines are formed. That is, in the metal wire forming process using tungsten, the step coverage is lower than the metal wiring process using the tungsten plug. Therefore, at least 3000 kW or more of tungsten film must be deposited to completely fill the contact without dents and obtain stable device characteristics. . Therefore, after the metal wiring is formed, deep and narrow valleys are formed between the wirings, which makes it very difficult to fill them.
텅스텐을 이용한 금속 배선 공정에서 텅스텐의 증착 두께를 낮출 수 없는 다른 중요한 이유는 금속 상호 연결이 스택 비아 구조를 갖기 때문이다. 즉, 도 2(c)에 도시된 바와 같이 제 2 층간 절연막(25)을 식각하여 형성하는 비아 콘택(26)이 금속 콘택 바로 위에 형성되기 때문에 금속 배선인 텅스텐이 너무 얇아 콘택 위에 텅스텐이 충분히 증착되어 있지 않거나 틈(seam)이 존재할 경우 비아 식각 공정에 적용되는 과도 식각에 의해 금속 콘택에 치명적인 손상을 입게 된다.Another important reason why tungsten deposition thickness cannot be lowered in tungsten metallization processes is that the metal interconnects have a stack via structure. That is, as shown in FIG. 2C, since the via contact 26 formed by etching the second interlayer insulating layer 25 is formed directly on the metal contact, tungsten, which is a metal wire, is too thin so that tungsten is sufficiently deposited on the contact. If not present or a gap is present, the metal contacts are critically damaged by the excessive etching applied to the via etching process.
상기한 종래의 제 1 및 제 2 실시 예의 문제점을 해결하기 위해 도 3(a) 내지 도 3(c)에 도시된 바와 같은 텅스텐 플러그와 텅스텐 금속 배선을 이용하여 금속 배선을 형성할 수 있는데, 이를 설명하면 다음과 같다.In order to solve the problems of the first and second exemplary embodiments described above, metal wires may be formed using tungsten plugs and tungsten metal wires as shown in FIGS. 3 (a) to 3 (c). The explanation is as follows.
도 3(a)를 참조하면, 소정의 공정을 통해 하부 구조가 형성된 반도체 기판 (31) 상부에 층간 절연막(32)을 형성한다. 층간 절연막(32)의 선택된 영역을 식각하여 반도체 기판(31)의 소정 영역을 노출시키는 콘택 홀을 형성한다. 콘택 홀을 포함한 전체 구조 상부에 Ti/TiN막으로 장벽 금속층(33)을 형성한다. 콘택 홀이 매립되도록 전체 구조 상부에 제 1 텅스텐막(34)을 형성한다.Referring to FIG. 3A, an interlayer insulating layer 32 is formed on a semiconductor substrate 31 on which a lower structure is formed through a predetermined process. The selected region of the interlayer insulating layer 32 is etched to form a contact hole exposing a predetermined region of the semiconductor substrate 31. The barrier metal layer 33 is formed of a Ti / TiN film on the entire structure including the contact hole. A first tungsten film 34 is formed on the entire structure so that the contact hole is filled.
도 3(b)는 장벽 금속층(33)의 상부, 즉 TiN막이 노출되도록 제 1 텅스텐막 (34)을 전면 식각하여 텅스텐 플러그를 형성한 상태의 단면도이다.FIG. 3B is a cross-sectional view of a top surface of the barrier metal layer 33, that is, a tungsten plug formed by etching the entire first tungsten film 34 so that the TiN film is exposed.
도 3(c)는 전체 구조 상부에 웨팅층(35)으로 Ti막 또는 Ti/TiN막을 형성한 후 금속 배선층으로 제 2 텅스텐막(36)을 형성한 상태의 단면도이다.3C is a cross-sectional view of a state in which a second tungsten film 36 is formed of a metal wiring layer after a Ti film or a Ti / TiN film is formed of a wetting layer 35 on the entire structure.
상기와 같은 공정으로 금속 배선을 형성할 경우 제 1 텅스텐막을 식각한 후 금속 배선이 뜨는 리프팅(lifting) 형상이 발생한다. 이는 텅스텐에 의한 스트레스 및 장벽 금속층의 일부로 사용되는 TiN막과 웨팅층으로 사용되는 Ti막 사이의 약한 접착력에 의한 것이다.When the metal wiring is formed by the above process, a lifting shape in which the metal wiring floats is generated after the first tungsten film is etched. This is due to the stress caused by tungsten and the weak adhesion between the TiN film used as part of the barrier metal layer and the Ti film used as the wetting layer.
따라서, 본 발명은 상기한 문제점을 해결할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that can solve the above problems.
상술한 목적을 달성하기 위한 본 발명은 소정의 공정을 통해 하부 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하는 단계와, 상기 층간 절연막의 소정 영역을 식각하여 상기 반도체 기판의 소정 영역을 노출시키는 콘택 홀을 형성하는 단계와, 상기 콘택홀을 포함한 전체 구조 상부에 장벽 금속층을 형성한 후 상기 콘택 홀이 매립되도록 전체 구조 상부에 제 1 텅스텐막을 형성하는 단계와, 상기 층간 절연막이 노출되도록 상기 제 1 텅스텐막 및 장벽 금속층을 전면 식각하여 텅스텐 플러그를 형성하는 단계와, 전체 구조 상부에 웨팅층을 증착하고 제 2 텅스텐막을 형성한 후 패터닝하여 금속 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming an interlayer insulating film on a semiconductor substrate on which a lower structure is formed through a predetermined process, and etching a predetermined region of the interlayer insulating film to expose a predetermined region of the semiconductor substrate. Forming a hole, forming a barrier metal layer over the entire structure including the contact hole, and then forming a first tungsten film over the entire structure to fill the contact hole, and exposing the first insulating layer to expose the interlayer insulating layer. Forming a tungsten plug by etching the tungsten film and the barrier metal layer on the entire surface, and depositing a wetting layer on the entire structure, forming a second tungsten film, and then patterning the metal wire to form a metal wiring.
도 1(a) 내지 도 1(c)는 종래의 금속 배선 형성 방법의 제 1 실시 예를 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of elements sequentially shown for explaining the first embodiment of the conventional metal wiring forming method.
도 2(a) 내지 도 2(c)는 종래의 금속 배선 형성 방법의 제 2 실시 예를 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of elements sequentially shown to explain a second embodiment of the conventional metal wiring forming method.
도 3(a) 내지 도 3(c)는 종래의 금속 배선 형성 방법의 제 3 실시 예를 설명하기 위해 순서적으로 도시한 소자의 단면도.3 (a) to 3 (c) are cross-sectional views of elements sequentially shown for explaining a third embodiment of the conventional metal wiring forming method.
도 4(a) 내지 도 4(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.4 (a) to 4 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11, 21, 31 및 41: 반도체 기판 12, 32 및 42 층간 절연막11, 21, 31, and 41: semiconductor substrate 12, 32, and 42 interlayer insulating film
13, 23, 33 및 43 : 장벽 금속층 14 : 텅스텐막13, 23, 33, and 43: barrier metal layer 14: tungsten film
15, 35 및 45 : 웨팅층 16 : 알루미늄층15, 35, and 45: wetting layer 16: aluminum layer
24 : 제 1 층간 절연막 25 : 제 2 층간 절연막24: first interlayer insulating film 25: second interlayer insulating film
26 : 비아 콘택 34 및 44 : 제 1 텅스텐막26: via contact 34 and 44: first tungsten film
36 및 46 : 제 2 텅스텐막36 and 46: second tungsten film
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 4(a) 내지 도 4(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.4 (a) to 4 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 4(a)를 참조하면, 소정의 공정을 통해 하부 구조가 형성된 반도체 기판 (41) 상부에 층간 절연막(42)을 형성한다. 층간 절연막(42)의 선택된 영역을 식각하여 반도체 기판(41)의 소정 영역을 노출시키는 콘택 홀을 형성한다. 콘택 홀을 포함한 전체 구조 상부에 Ti/TiN막으로 장벽 금속층(43)을 형성한다. 콘택 홀이 매립되도록 전체 구조 상부에 제 1 텅스텐막(44)을 형성한다.Referring to FIG. 4A, an interlayer insulating layer 42 is formed on a semiconductor substrate 41 on which a lower structure is formed through a predetermined process. The selected region of the interlayer insulating layer 42 is etched to form a contact hole exposing a predetermined region of the semiconductor substrate 41. The barrier metal layer 43 is formed of a Ti / TiN film on the entire structure including the contact hole. A first tungsten film 44 is formed on the entire structure so that the contact hole is filled.
도 4(b)는 층간 절연막(42)가 노출되도록 제 1 텅스텐막(44) 및 장벽 금속층(43)을 전면 식각하여 텅스텐 플러그를 형성한 상태의 단면도이다. 즉, 본 발명에서는 식각 정지층으로 장벽 금속층을 사용하던 종래의 방법과 달리 층간 절연막을 식각 정지층으로 사용한다.FIG. 4B is a cross-sectional view of a state in which a tungsten plug is formed by etching the first tungsten film 44 and the barrier metal layer 43 so that the interlayer insulating film 42 is exposed. That is, in the present invention, unlike the conventional method of using the barrier metal layer as the etch stop layer, the interlayer insulating film is used as the etch stop layer.
도 4(c)는 전체 구조 상부에 웨팅층(45)으로 PVD Ti/TiN막을 형성한 후 금속 배선층으로 PVD 제 2 텅스텐막(66)을 형성한 상태의 단면도이다. 웨팅층(45)과 제 2 텅스텐막(66)은 PVD 방식으로 형성되기 때문에 동일한 챔버에서 인시투로 공정을 진행할 수 있다.FIG. 4C is a cross-sectional view of a PVD Ti / TiN film formed of a wetting layer 45 on the entire structure and a PVD second tungsten film 66 formed of a metal wiring layer. Since the wetting layer 45 and the second tungsten film 66 are formed by the PVD method, the wetting layer 45 and the second tungsten film 66 may be processed in-situ in the same chamber.
상술한 바와 같이 본 발명에 의하면 다음과 같은 효과를 기대할 수 있다.As described above, according to the present invention, the following effects can be expected.
첫째, 금속 배선층으로 알루미늄보다 반사율이 낮은 텅스텐막을 사용하기 때문에 좁은 배선 패턴도 확정할 수 있다.First, since a tungsten film having a lower reflectance than aluminum is used as the metal wiring layer, a narrow wiring pattern can also be determined.
둘째, 텅스텐을 전면 식각하여 텅스텐 플러그를 형성한 후 금속 배선층을 형성하기 때문에 증착 두께를 상당히 낮출 수 있어 갭필 특성을 향상시킬 수 있다.Second, since the metal wiring layer is formed after the tungsten is entirely etched to form the tungsten plug, the deposition thickness can be considerably lowered, thereby improving the gapfill characteristics.
세째, 스택 비아를 형성할 때 금속 콘택 위에 금속 배선으로 텅스텐막이 형성되어 있으므로 과도 식각에 의한 손상을 방지할 수 있다.Third, when the stack via is formed, a tungsten film is formed on the metal contact by the metal wires, thereby preventing damage due to excessive etching.
네째, 텅스텐 플러그를 형성하기 위한 텅스텐막을 전면 식각할 때 식각 정지층으로 층간 절연막을 사용하기 때문에, 즉 장벽 금속층을 제거하기 때문에 장벽 금속층과 웨팅층의 약한 접착력에 의한 금속 배선의 리프팅을 방지할 수 있다.Fourth, since the interlayer insulating film is used as the etch stop layer when the tungsten film for forming the tungsten plug is etched in front, that is, the barrier metal layer is removed, the lifting of the metal wiring due to the weak adhesion between the barrier metal layer and the wetting layer can be prevented. have.
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| KR1019990025442A KR100568794B1 (en) | 1999-06-29 | 1999-06-29 | Method of forming a metal wiring in a semiconductor device |
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| KR1019990025442A KR100568794B1 (en) | 1999-06-29 | 1999-06-29 | Method of forming a metal wiring in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101027337B1 (en) * | 2004-06-30 | 2011-04-11 | 주식회사 하이닉스반도체 | Method for fabrication of conduction pattern of semiconductor device having tungsten layer |
| KR101037420B1 (en) * | 2009-07-24 | 2011-05-30 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101027337B1 (en) * | 2004-06-30 | 2011-04-11 | 주식회사 하이닉스반도체 | Method for fabrication of conduction pattern of semiconductor device having tungsten layer |
| KR101037420B1 (en) * | 2009-07-24 | 2011-05-30 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
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