KR100373346B1 - Method for bonding pad in semiconductor device - Google Patents
Method for bonding pad in semiconductor device Download PDFInfo
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- KR100373346B1 KR100373346B1 KR10-2000-0080887A KR20000080887A KR100373346B1 KR 100373346 B1 KR100373346 B1 KR 100373346B1 KR 20000080887 A KR20000080887 A KR 20000080887A KR 100373346 B1 KR100373346 B1 KR 100373346B1
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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Abstract
본 발명은 본딩패드와 하부 금속배선사이의 층간절연막의 크랙 및 파괴로 인한 필오프 현상을 방지하도록 한 본딩패드의 제조 방법에 관한 것으로, 소정 공정이 완료된 반도체 기판상에 블록킹막을 형성하는 단계, 상기 블록킹막상에 제 1 층간절연막을 형성하는 단계, 상기 제 1 층간절연막상에 그물망 형태의 금속배선을 형성하는 단계, 상기 금속배선상에 제 2 층간절연막을 형성하는 단계, 상기 제 2 층간절연막을 제거하여 상기 금속배선을 노출시키는 단계, 상기 노출된 금속배선 하부의 상기 제 1 층간절연막을 제거하여 상기 블록킹막을 노출시키는 함몰된 본딩패드 콘택 영역을 형성하는 단계, 상기 노출된 금속막사이의 블록킹막상에 플러그를 형성함과 동시에 상기 제 2 층간절연막 제거시 형성된 절연막측벽에 금속막측벽을 형성하는 단계, 및 상기 플러그와 금속막측벽상에 상기 금속막과 접속되는 본딩패드를 형성하는 단계를 포함하여 이루진다.The present invention relates to a method of manufacturing a bonding pad for preventing a peel-off phenomenon due to cracking and breakage of an interlayer insulating layer between the bonding pad and a lower metal wiring, the method comprising: forming a blocking film on a semiconductor substrate on which a predetermined process is completed; Forming a first interlayer insulating film on the blocking film, forming a metal wiring in the form of a mesh on the first interlayer insulating film, forming a second interlayer insulating film on the metal wiring, and removing the second interlayer insulating film. Exposing the metal interconnection, removing the first interlayer dielectric layer under the exposed metal interconnection to form a recessed bonding pad contact region exposing the blocking layer, on the blocking layer between the exposed metal layers Simultaneously forming a plug and forming a metal film side wall on the insulating film side wall formed when the second interlayer insulating film is removed; and And forming a bonding pad connected to the metal film on the plug and the metal film side wall.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 기계적 스트레스(Mechnical stress)에 의한 본딩(Bonding)시 필오프(Peel-off) 현상을 방지하도록 한 본딩 패드(Bonding pad)의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a bonding pad to prevent peel-off when bonding is caused by mechanical stress. .
도 1은 종래기술에 따라 제조된 본딩패드의 구조를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a bonding pad manufactured according to the prior art.
도 1에 도시된 바와 같이, 소정 공정이 완료된 층간절연막(11)상에 소정 간격을 두고 다수의 금속배선(12)을 형성한 후, 금속배선(12)상에 IMD(Inter Metal Dielectric)로서 TEOS/SOG/TEOS(13/14/15)을 순차적으로 형성한다. 이 때, SOG(14)는 자체 평탄화가 가능하므로 금속배선(12)간 매립되는 TEOS(13)로 인한 단차를 완화시키며 후속 TEOS(15) 형성시 평탄화가 가능하다.As shown in FIG. 1, after forming a plurality of metal wires 12 at predetermined intervals on the interlayer insulating film 11 in which a predetermined process is completed, TEOS as IMD (Inter Metal Dielectric) on the metal wires 12. / SOG / TEOS (13/14/15) are formed sequentially. At this time, since the SOG 14 is capable of self-planarization, the step difference caused by the TEOS 13 embedded between the metal lines 12 may be alleviated, and the SOG 14 may be planarized in the formation of the subsequent TEOS 15.
TEOS(15)상에 본딩패드용 금속을 증착한 후, 선택적으로 식각하여 본딩패드(16)를 형성한다.After depositing the bonding pad metal on the TEOS 15, the bonding pad 16 is selectively etched to form the bonding pad 16.
그러나, 상술한 종래기술에서는 본딩패드(16) 하부의 금속배선(12)을 막대 모양으로 한정하므로써 USG(14) 형성시 단차에 의해 두껍게 매립되는 부분과 얇게 매립되는 부분이 발생되므로서, 본딩패드(16)에 본딩시 USG(14)에 스트레스를 전달하여 전체적으로 본딩패드(16) 하부의 층간절연막에 크랙 또는 파괴가 발생된다.However, in the above-described prior art, by limiting the metal wiring 12 below the bonding pad 16 to the shape of a rod, a portion that is thickly embedded and a portion that is thinly buried due to a step occurs when the USG 14 is formed. When bonding to the (16), the stress is transmitted to the USG (14), the crack or breakage occurs in the interlayer insulating film under the bonding pad 16 as a whole.
이로 인해 층간절연막의 필오프 현상이 발생하는 문제점이 있다.As a result, a peel-off phenomenon of the interlayer insulating film occurs.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 기계적 스트레스에 의한 층간절연막의 크랙 및 파괴를 방지하고, 필오프 현상을 방지하는데 적합한 본딩패드의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, an object of the present invention is to provide a method of manufacturing a bonding pad suitable for preventing the crack and breakage of the interlayer insulating film due to mechanical stress, and to prevent the peel off phenomenon.
도 1은 종래기술에 따라 형성된 본딩패드의 구조 단면도,1 is a structural cross-sectional view of a bonding pad formed according to the prior art,
도 2a 내지 도 2e는 본 발명의 실시예에 따른 본딩패드의 제조 방법을 나타낸 공정 단면도,2A to 2E are cross-sectional views illustrating a method of manufacturing a bonding pad according to an embodiment of the present invention;
도 3은 본 발명의 실시예에 따른 본딩패드 영역의 평면도.3 is a plan view of a bonding pad area in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 하부층 22 : 블록킹층21: lower layer 22: blocking layer
23 : 제 1 층간절연막 24 : 금속배선23: first interlayer insulating film 24: metal wiring
25/26/27 : TEOS/SOG/TEOS 29a : 텅스텐플러그25/26/27: TEOS / SOG / TEOS 29a: tungsten plug
29b : 텅스텐측벽 30 : 본딩패드29b: tungsten side wall 30: bonding pad
상기의 목적을 달성하기 위한 본 발명의 본딩패드의 제조 방법은 소정 공정이 완료된 반도체 기판상에 블록킹막을 형성하는 단계, 상기 블록킹막상에 제 1 층간절연막을 형성하는 단계, 상기 제 1 층간절연막상에 그물망 형태의 금속배선을 형성하는 단계, 상기 금속배선상에 제 2 층간절연막을 형성하는 단계, 상기 제 2 층간절연막을 제거하여 상기 금속배선을 노출시키는 단계, 상기 노출된 금속배선 하부의 상기 제 1 층간절연막을 제거하여 상기 블록킹막을 노출시키는 함몰된 본딩패드 콘택 영역을 형성하는 단계, 상기 노출된 금속막사이의 블록킹막상에 플러그를 형성함과 동시에 상기 제 2 층간절연막 제거시 형성된 절연막측벽에 금속막측벽을 형성하는 단계, 및 상기 플러그와 금속막측벽상에 상기 금속막과 접속되는 본딩패드를 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a bonding pad of the present invention for achieving the above object comprises the steps of forming a blocking film on a semiconductor substrate having a predetermined process, forming a first interlayer insulating film on the blocking film, on the first interlayer insulating film Forming a metal network in the form of a net, forming a second interlayer insulating film on the metal wire, exposing the metal wire by removing the second interlayer insulating film, and exposing the metal wire under the exposed metal wire. Forming a recessed bonding pad contact region exposing the blocking film by removing the interlayer insulating film; forming a plug on the blocking film between the exposed metal films and at the same time a metal film on the insulating side wall formed when removing the second interlayer insulating film; Forming a sidewall, and forming a bonding pad connected to the metal film on the plug and the metal film side wall; Characterized in that comprises a.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2e는 본 발명의 실시예에 따른 본딩패드의 제조 방법을 나타낸 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a bonding pad according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 소정 공정이 완료된 층간절연막이나 반도체기판 등의 하부층(21)상에 블록킹층(22)을 형성한 후, 블록킹층(22)을 포함한 전면에 제1 층간절연막(23)을 형성하고, 제 1 층간절연막(23)상에 금속배선(24)을 증착하고 선택적으로 패터닝하여 그물망 창(24a)을 형성한다. 이 때, 금속배선(24)을 식각하기 위한 마스크는 후속 본딩패드 영역 하부의 층간절연막을 완전히 제거하기 위해 그물망으로 형성되며, 후속 본딩패드 오픈 영역만큼 형성된다. 그리고, 블록킹층(22)은 후속 비아콘택 식각시 다른 층이나 반도체기판에 국부배선되는 것을 방지하기 위해 하부 금속배선과 식각률이 다른 층을 이용한다.As shown in FIG. 2A, after the blocking layer 22 is formed on the lower layer 21 such as an interlayer insulating film or a semiconductor substrate having a predetermined process, the first interlayer insulating film 23 is formed on the entire surface including the blocking layer 22. ), A metal wiring 24 is deposited and selectively patterned on the first interlayer insulating film 23 to form a mesh window 24a. In this case, the mask for etching the metal wiring 24 is formed of a mesh to completely remove the interlayer insulating film under the subsequent bonding pad region, and is formed by the subsequent bonding pad open region. In addition, the blocking layer 22 may use a layer having a different etching rate from that of the lower metal wiring to prevent local wiring on another layer or a semiconductor substrate during subsequent via contact etching.
도 2b에 도시된 바와 같이, 그물망 창(24a)이 형성된 금속배선(24)상에 제 2 층간절연막으로서 TEOS/SOG/TEOS(25/26/27)을 순차적으로 형성한다.As shown in FIG. 2B, TEOS / SOG / TEOS 25/26/27 is sequentially formed as a second interlayer insulating film on the metal wiring 24 on which the mesh window 24a is formed.
도 2c에 도시된 바와 같이, 비아콘택 마스크(Via contact mask)를 이용하여 TEOS/USG/TEOS(25/26/27)을 식각하여 후속 본딩패드 하부에 TEOS/USG/TEOS (25/26/27)이 잔류하지 않도록 완전히 제거하는데, 이 때 비아콘택 마스크는 후속 본딩패드 영역(28)을 완전히 노출시키는 마스크 즉, 본딩패드의 영역과 동일한 크기를 갖는 마스크를 이용한다.As shown in FIG. 2C, the TEOS / USG / TEOS 25/26/27 is etched using a via contact mask to remove the TEOS / USG / TEOS under the subsequent bonding pads (25/26/27). The via contact mask uses a mask that completely exposes the subsequent bonding pad region 28, i.e., a mask having the same size as the region of the bonding pad.
이러한 TEOS/USG/TEOS(25/26/27) 식각후, 하부의 금속배선(24)이 식각정지막으로 작용하여 금속배선(24) 하부의 제 1 층간절연막(23)이 선택적으로 식각되어 블록킹층(22)이 노출되어 본딩패드 영역(28)이 함몰되고 또는 용기 모양으로 형성되고, 본딩패드 영역(28)을 제외한 부분에는 TEOS/USG/TEOS(25a/26a/27a)이 잔류한다.After etching the TEOS / USG / TEOS (25/26/27), the lower metal wiring 24 acts as an etch stop layer, so that the first interlayer insulating film 23 under the metal wiring 24 is selectively etched and blocked. The layer 22 is exposed and the bonding pad region 28 is recessed or formed into a container shape, and the TEOS / USG / TEOS 25a / 26a / 27a remains in the portion except the bonding pad region 28.
도 2d에 도시된 바와 같이, 노출된 비아콘택 영역을 포함한 전면에 텅스텐을 증착한 후 에치백하여 금속배선(24) 사이의 노출된 블록킹층(22)상에 매립되는 텅스텐플러그(29a)를 형성하고, 잔류하는 TEOS/USG/TEOS(25a/26a/27a)의 측벽에 접하는 텅스텐측벽(29b)을 형성한다.As shown in FIG. 2D, tungsten is deposited on the entire surface including the exposed via contact region and then etched back to form a tungsten plug 29a buried on the exposed blocking layer 22 between the metal lines 24. Then, a tungsten side wall 29b is formed in contact with the sidewalls of the remaining TEOS / USG / TEOS 25a / 26a / 27a.
도 2e에 도시된 바와 같이, 텅스텐플러그(29a) 및 텅스텐측벽(29b)을 포함한 전면에 본딩패드용 금속을 증착한 후 선택적으로 식각하여 본딩패드(30)를 형성한다.As shown in FIG. 2E, the bonding pad metal is deposited on the front surface including the tungsten plug 29a and the tungsten side wall 29b and then selectively etched to form the bonding pad 30.
상술한 바와 같이, 본 발명의 실시예에서는 본딩패드(30)와 본딩패드(30) 하부의 금속배선(24)사이에 존재하는 층간절연막을 완전히 제거하며, 본딩시 텅스텐측벽(29b)을 이용하여 콘택 영역을 증가시킨다.As described above, in the embodiment of the present invention, the interlayer insulating film existing between the bonding pad 30 and the metal wiring 24 under the bonding pad 30 is completely removed, and the tungsten side wall 29b is used during bonding. Increase the contact area.
또한, 함몰된 영역에 텅스텐 측벽(29b)을 형성하므로써 본딩패드 양끝단에 가드링(Guarding)역할을 하여 본딩패드로의 흡습을 억제할 수 있다.In addition, by forming the tungsten sidewall 29b in the recessed region, it is possible to act as a guard ring at both ends of the bonding pad to suppress moisture absorption to the bonding pad.
도 3은 본 발명의 실시예에 따른 본딩패드 영역을 노출시킨 평면도로서, 블록킹층(22)보다 작은 폭으로 금속배선(24)을 형성하되, 금속배선(24)은 그물망 창(24a)을 갖도록 패터닝되며, 본딩패드 영역(28)은 그물망 창(24a)이 형성된 금속배선(24)보다는 크다.3 is a plan view exposing a bonding pad region according to an exemplary embodiment of the present invention, wherein the metal wiring 24 is formed to have a width smaller than that of the blocking layer 22, but the metal wiring 24 has a mesh window 24a. The patterned, bonding pad region 28 is larger than the metallization 24 in which the mesh window 24a is formed.
그리고, 금속배선(24)과 블록킹층(22) 사이에 가드링으로서 즉, 본딩패드 모서리 부분에 텅스텐측벽(29b)이 형성되어 본딩패드로의 흡습을 억제한다. 이러한 텅스텐측벽(29b)은 금속배선(24) 상부에 형성된다.Then, a tungsten side wall 29b is formed between the metal wiring 24 and the blocking layer 22 as a guard ring, that is, at the corner of the bonding pad to suppress moisture absorption into the bonding pad. The tungsten side wall 29b is formed on the metal wiring 24.
상술한 것처럼, 본 발명의 실시예에서는 자기정렬 트렌치(Self-aligned Trench) 구조의 본딩패드를 구현한다.As described above, the embodiment of the present invention implements a bonding pad having a self-aligned trench structure.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 본딩패드의 제조 방법은 금속배선을 그물망처럼 형성하여 비아콘택 식각시 본딩패드와 본딩패드 하부의 금속배선 사이에 존재하는 층간절연막을 완전히 제거하여 본딩시 층간절연막의 크랙 및 파괴를 방지할 수 있으며, 본딩 패드 영역의 본딩영역을 함몰시켜 측벽에 텅스텐측벽을 형성하므로써 본딩영역을 증가시켜 콘택저항을 감소시킬 수 있는 효과가 있다.As described above, the method of manufacturing the bonding pad of the present invention forms a metal wiring like a mesh to completely remove the interlayer insulating film existing between the bonding pad and the metal wiring under the bonding pad during etching of the via contact, thereby cracking the interlayer insulating film during bonding and The breakage can be prevented, and the tungsten side wall is formed on the sidewall by recessing the bonding area of the bonding pad area, thereby increasing the bonding area and reducing the contact resistance.
Claims (5)
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| KR10-2000-0080887A KR100373346B1 (en) | 2000-12-22 | 2000-12-22 | Method for bonding pad in semiconductor device |
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| KR10-2000-0080887A KR100373346B1 (en) | 2000-12-22 | 2000-12-22 | Method for bonding pad in semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100979242B1 (en) | 2008-04-28 | 2010-08-31 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| KR20230006268A (en) * | 2021-07-02 | 2023-01-10 | 주식회사 디비하이텍 | Backside illumination image sensor and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100400047B1 (en) * | 2001-11-19 | 2003-09-29 | 삼성전자주식회사 | Bonding pad structure of semiconductor device and method for forming thereof |
| KR100933685B1 (en) * | 2007-12-18 | 2009-12-23 | 주식회사 하이닉스반도체 | Bonding pad to prevent peeling and forming method thereof |
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2000
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100979242B1 (en) | 2008-04-28 | 2010-08-31 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| KR20230006268A (en) * | 2021-07-02 | 2023-01-10 | 주식회사 디비하이텍 | Backside illumination image sensor and method of manufacturing the same |
| KR102645312B1 (en) * | 2021-07-02 | 2024-03-08 | 주식회사 디비하이텍 | Backside illumination image sensor and method of manufacturing the same |
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