KR100237743B1 - Method for forming metal interconnector in semiconductor device - Google Patents

Method for forming metal interconnector in semiconductor device Download PDF

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KR100237743B1
KR100237743B1 KR1019970014098A KR19970014098A KR100237743B1 KR 100237743 B1 KR100237743 B1 KR 100237743B1 KR 1019970014098 A KR1019970014098 A KR 1019970014098A KR 19970014098 A KR19970014098 A KR 19970014098A KR 100237743 B1 KR100237743 B1 KR 100237743B1
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forming
contact hole
semiconductor device
metal wiring
film
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KR19980077123A (en
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이해정
박현식
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 장치 제조 방법.Semiconductor device manufacturing method.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

반도체 장치의 금속 배선 형성 방법에 있어서, 집적도 증가에 따라 스텝 커버리지 불량으로 인해 금속 배선막 증착시 키홀이 발생하여 반도체 소자의 특성, 수율 및 신뢰성 저하의 원인이 되고 있다.In the method of forming a metal wiring of a semiconductor device, keyholes are generated during deposition of a metal wiring film due to poor step coverage due to an increase in the degree of integration, which causes deterioration of characteristics, yield and reliability of the semiconductor device.

종래의 금속 배선 콘택홀 형성 후 전체 구조에 대한 전면 건식 식각으로 콘택홀 입구 부분을 라운딩하여 금속막을 증착하는 방법은 키홀의 발생을 방지할 수는 있으나, 실리콘 기판 상에 형성된 접합의 소모를 유발하므로 접합 누설이 발생하는 문제점이 있다.The conventional method for depositing a metal film by rounding the contact hole inlet by dry etching the entire structure after forming the metal wiring contact hole may prevent the generation of key holes, but may cause the consumption of the junction formed on the silicon substrate. There is a problem that a junction leak occurs.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

식각 공정에서 접합의 소모를 방지하기 위하여 실리콘 기판에 형성된 접합 상에 장벽금속막 패턴을 형성하고, 키홀의 발생을 방지하기 위하여 라운딩된 콘택홀 입구 부분을 형성함으로써 키홀 발생 및 접합 누설을 동시에 방지하는 반도체 장치의 금속 배선 형성 방법을 제공하고자 함.The barrier metal film pattern is formed on the junction formed on the silicon substrate to prevent the consumption of the junction in the etching process, and the rounded contact hole inlet portion is formed to prevent the generation of the keyhole, thereby simultaneously preventing the occurrence of the keyhole and the junction leakage. To provide a method for forming metal wiring of a semiconductor device.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 장치의 금속 배선 형성 방법에 이용됨Used in the method of forming metal wiring of semiconductor device

Description

반도체 장치의 금속 배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 일반적으로, 반도체 장치의 금속 배선 형성 방법에 관한 것으로, 특히 금속 배선막 증착시 발생하는 키홀 및 접합 누설을 방지하기 위한 반도체 장치의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a method for forming metal wirings in a semiconductor device for preventing keyholes and junction leaks generated during deposition of a metal wiring film.

이하 첨부 도면 도1A 내지 도1E를 참조하여 종래 기술의 문제점을 상세히 설명한다.Hereinafter, the problems of the prior art will be described in detail with reference to FIGS. 1A to 1E.

종래의 금속 배선 형성 공정은 먼저, 첨부 도면 도1A에 도시한 바와 같이 실리콘 기판(11) 상에 P+또는 N+접합영역(12)을 형성한 다음 하부금속배선(14) 및 층간절연막(13,15)으로 이루어지는 하부구조를 형성하고, 전체 구조 상부에 금속 배선 콘택 마스크인 포토레지스트 패턴(16)을 형성한다.In the conventional metal wiring forming process, first, as shown in FIG. 1A, the P + or N + junction region 12 is formed on the silicon substrate 11, and then the lower metal wiring 14 and the interlayer insulating film 13 are formed. 15 is formed, and a photoresist pattern 16 that is a metal wiring contact mask is formed on the entire structure.

이어서, 도1B에 도시한 바와 같이, 상기 포토레지스트 패턴(16)을 식각 방지막으로 하여 층간 절연막(13,15)을 건식식각하고 금속 배선 콘택홀을 형성한 다음 포토레지스트 패턴(16)을 제거한다.Subsequently, as shown in FIG. 1B, the interlayer insulating films 13 and 15 are dry-etched using the photoresist pattern 16 as an etch stop layer, metal contact holes are formed, and then the photoresist pattern 16 is removed. .

다음으로, 도1C에 도시한 바와 같이 상기 전체 구조 상부에 Ti 또는 Ti/TiN로 장벽금속막(17)을 증착한 후, 텅스텐으로 금속 배선막(18)을 증착한다. 상기 장벽금속막(17) 중에서 Ti는 실리콘 기판에 형성된 접합(12)과 반응하여 TiS2를 형성함으로써 콘택 저항을 낮추는 역할을 하며, TiN은 Ti와 W의 접착력을 향상시키기 위해 사용되므로 상기 장벽 금속막(17)은 금속 배선 형성 공정에서 없어서는 안되는 중요한 막이다.Next, as shown in FIG. 1C, the barrier metal film 17 is deposited on the entire structure by Ti or Ti / TiN, and then the metal wiring film 18 is deposited by tungsten. Among the barrier metal films 17, Ti serves to lower the contact resistance by forming TiS 2 by reacting with the junction 12 formed on the silicon substrate, and since the TiN is used to improve the adhesion between Ti and W, the barrier metal The film 17 is an important film which is indispensable in the metal wiring forming process.

전술한 바와 같은 종래의 금속 배선 형성 방법에 있어서는 스텝 커버리지(step coverage) 불량으로 인해 금속 배선막(18) 증착시 발생되는 키홀(keyhole)(19)이라고 부르는 콘택홀 내에서의 금속막 보이드(void) 현상을 방지할 수 없어 반도체 소자의 특성, 수율 및 신뢰성 저하의 원인이 되고 있다.In the conventional metal wiring forming method as described above, a metal film void in a contact hole called a keyhole 19 generated when the metal wiring film 18 is deposited due to poor step coverage. This phenomenon cannot be prevented, which is a cause of deterioration in characteristics, yield and reliability of semiconductor devices.

또한, 첨부된 도1D는 상기 도1B에서 금속 배선의 콘택홀 형성시 콘택홀을 경사지게 형성한 후의 단면도로서 이러한 방법으로는 후속 금속막 증착시 키홀의 크기를 감소시킬 수는 있으나 상기 콘택홀의 경사에 한계가 있으므로 키홀의 발생을 근본적으로 방지할 수 없다.In addition, FIG. 1D is a cross-sectional view after the contact hole is formed to be inclined when forming the contact hole of the metal wiring in FIG. 1B. In this method, the size of the keyhole may be reduced during subsequent deposition of the metal film. Since there is a limit, it is impossible to fundamentally prevent the occurrence of keyholes.

또한, 첨부된 1E도는 상기 도1B에서 금속 배선 콘택홀 형성 후 전체 구조에 대한 전면 건식 식각으로 콘택홀 입구 부분을 라운딩한 단면도로서, 후속 금속막 증착시 키홀의 발생을 방지할 수는 있으나 통상의 건식식각 방법으로는 실리콘 기판 상에 형성된 접합(12)의 소모를 유발하므로 접합 누설이 발생하게 된다.In addition, FIG. 1E is a cross-sectional view of the contact hole inlet portion formed by dry etching the entire structure after forming the metal interconnection contact hole in FIG. 1B, and it is possible to prevent the generation of key holes during subsequent metal film deposition. In the dry etching method, the junction 12 is formed on the silicon substrate, so that the junction leakage occurs.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 반도체 장치의 제조 방법에 있어서 보이드 현상과 접합 누설을 동시에 방지하기 위한 반도체 장치의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention devised to solve the above problems has an object of the present invention to provide a method for forming a metal wiring of a semiconductor device for simultaneously preventing void phenomenon and junction leakage in a method of manufacturing a semiconductor device.

도1A 내지 도1E는 종래 기술에 따른 금속 배선 형성 공정 단면도1A to 1E are cross-sectional views of a metal wiring forming process according to the prior art.

도2A 내지 도2E는 본 발명의 일실시예에 따른 금속 배선 형성 공정 단면도2A through 2E are cross-sectional views of a metal wiring forming process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing

11,21: 실리콘 기판12,22: 접합층11,21 silicon substrate 12,22 bonding layer

13,15,24,26,29: 절연층 14,25: 하부금속배선13,15,24,26,29: insulating layer 14,25: lower metal wiring

16,27: 포토레지스트 패턴17,23: 장벽금속막16, 27: photoresist pattern 17, 23: barrier metal film

18,28: 금속배선막19: 키홀18, 28: metal wiring film 19: keyhole

상기 목적을 달성하기 위한 본 발명은 반도체 장치의 금속 배선 형성 방법에 있어서, 반도체 기판 상에 접합영역을 형성하는 단계; 상기 접합영역 상에 장벽금속막 패턴을 형성하는 단계; 제1 층간 절연막을 형성하는 단계; 하부 금속 배선 및 제2 층간 절연막을 형성하는 단계; 상기 전체 구조에 콘택홀 형성을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 방지막으로 상기 제1 및 제2 층간 절연막을 건식식각하여 콘택홀을 형성하는 단계; 포토레지스트 패턴을 제거하는 단계; 상기 전체 구조에 대해 전면 건식식각을 하여 라운딩된 콘택홀 입구 부분을 형성단계; 및 상부 금속 배선막을 형성하는 단계를 포함해서 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a metal wiring forming method of a semiconductor device, the method comprising: forming a junction region on a semiconductor substrate; Forming a barrier metal film pattern on the junction region; Forming a first interlayer insulating film; Forming a lower metal wiring and a second interlayer insulating film; Forming a photoresist pattern for forming a contact hole in the entire structure; Forming a contact hole by dry etching the first and second interlayer insulating layers using the photoresist pattern as an etch stop layer; Removing the photoresist pattern; Forming a rounded contact hole inlet by dry etching the entire structure on the entire structure; And forming an upper metal wiring film.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 살펴본다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도2A 내지 도2E는 본 발명의 일실시예에 따른 금속 배선 형성 공정 단면도이다.2A through 2E are cross-sectional views of a metal wiring forming process according to an embodiment of the present invention.

먼저, 도2A에 도시한 바와 같이 실리콘 기판(21) 상에 P+또는 N+접합(22)을 형성한 다음 Ti, Ti/TiN, Ti/TiW 중의 어느 하나로 장벽 금속막을 소정의 두께로 증착하고 사진식각하여 장벽금속막(23) 패턴을 형성한다.First, as shown in FIG. 2A, a P + or N + junction 22 is formed on the silicon substrate 21, and then a barrier metal film is deposited to a predetermined thickness using any one of Ti, Ti / TiN, and Ti / TiW. Photolithography is performed to form the barrier metal film 23 pattern.

상기 과정에서 실리콘 기판에 바로 접하여 증착된 장벽금속막의 사진식각 공정에서 실리콘과 장벽금속막의 식각 선택비가 좋지 않아서 실리콘 기판의 소모가 발생하기도 한다. 이를 방지하기 위하여 도2A´에 도시한 바와 같이 P+또는 N+의 접합(22)이 형성된 실리콘 기판(21) 상에 산화막으로 절연층(29)을 형성하고, 절연층(29)을 사진식각하여 접합 상에 콘택홀을 형성하고, 장벽금속막(23)을 소정의 두께로 증착하고 사진식각하여 장벽금속막(23) 패턴을 형성하기도 한다.In the above process, in the photolithography process of the barrier metal film deposited directly in contact with the silicon substrate, the etching selectivity between the silicon and the barrier metal film is not good, and thus the consumption of the silicon substrate may occur. In order to prevent this, as shown in FIG. 2A ′, an insulating layer 29 is formed of an oxide film on the silicon substrate 21 on which the junction 22 of P + or N + is formed, and the insulating layer 29 is photo-etched. Contact holes are formed on the junction, and the barrier metal film 23 is deposited to a predetermined thickness and etched to form the barrier metal film 23 pattern.

이어서, 도2B에 도시한 바와 같이 상기 전체 구조 상부에 하부금속배선(25) 및 주로 산화막인 층간 절연막(24,26)을 포함하는 하부구조를 형성하고 금속 배선 콘택 마스크인 포토레지스트 패턴(27)을 형성한다.Subsequently, as shown in FIG. 2B, a lower structure including a lower metal wiring 25 and interlayer insulating films 24 and 26, which are mainly oxide films, is formed on the entire structure, and a photoresist pattern 27, which is a metal wiring contact mask, is formed. To form.

다음으로, 도2C에 도시한 바와 같이 상기 포토레지스트 패턴(27)을 식각 방지막으로 상기 층간 절연막(24,26)을 건식식각하여 금속 배선 콘택홀을 형성한 다음 포토레지스트 패턴(27)의 일부 또는 전부를 제거한다. 통상의 식각 기술로도 장벽금속막과 산화막의 식각 선택비가 20:1 이상이므로 장벽 금속막(23) 패턴의 일부만이 손상된다.Next, as shown in FIG. 2C, the interlayer insulating layers 24 and 26 are dry-etched using the photoresist pattern 27 as an etch stop layer to form metal wiring contact holes, and then a portion or a portion of the photoresist pattern 27 is formed. Remove everything Even with the conventional etching technique, since the etching selectivity of the barrier metal film and the oxide film is 20: 1 or more, only a part of the barrier metal film 23 pattern is damaged.

다음으로, 도2D에 도시한 바와 같이 상기 전체 구조에 대해 C와 F를 포함한 플라즈마 또는 Ar을 포함한 플라즈마를 사용한 전면 건식 식각을 하여 라운딩된 콘택홀 입구 부분을 형성한다. 통상의 식각 기술로도 장벽금속막(23) 패턴의 소모는 존재하지만 접합(22)의 소모는 발생하지 않는다. 상기 포토레지스트 패턴(27) 제거 과정은 등방성 식각이므로 포토레지스트 패턴(27)을 전부 제거하지 않고 일부를 남기면 콘택홀 입구 부분이 다른 부분에 비해 비교적 많이 제거된 포토레지스트 패턴을 얻을 수 있어서, 전면식각 과정에서 포토레지스트 패턴 하부의 절연층의 식각없이 콘택홀 입구 부분을 집중적으로 식각하여 라운딩지게 할 수 있다.Next, as shown in FIG. 2D, the entire dry structure is subjected to full dry etching using a plasma including C and F or a plasma including Ar to form a rounded contact hole inlet portion. Even with conventional etching techniques, there is a consumption of the barrier metal film 23 pattern, but no consumption of the junction 22 occurs. Since the process of removing the photoresist pattern 27 is an isotropic etching process, if a portion of the photoresist pattern 27 is left without removing all of the photoresist pattern 27, a photoresist pattern having a relatively large number of contact hole inlet portions removed from other portions can be obtained. In the process, the contact hole inlet portion may be etched intensively without being etched from the insulating layer under the photoresist pattern to be rounded.

다음으로, 도2E에 도시한 바와 같이 상기 장벽금속막 패턴(23) 상부의 자연산화막(도시하지 않음)을 제거한 다음 전체 구조 상부에 텅스텐 또는 알루미늄으로 금속 배선막(28)을 증착한다.Next, as shown in FIG. 2E, a natural oxide film (not shown) on the barrier metal film pattern 23 is removed, and then a metal wiring film 28 is deposited on tungsten or aluminum over the entire structure.

상기와 같이 이루어지는 본 발명의 기술은 종래의 기술로는 방지할 수 없는 금속 콘택홀 내에서의 키홀을 방지할 수 있으며 또한 실리콘 기판 상에 형성된 접합의 소모를 방지할 수 있어 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있는 이점이 있다.The technique of the present invention made as described above can prevent the keyhole in the metal contact hole which cannot be prevented by the conventional technique, and can also prevent the consumption of the junction formed on the silicon substrate, thereby reducing the characteristics and reliability of the semiconductor device. There is an advantage to improve.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명의 기술은 금속 배선 콘택홀 내에서의 키홀을 방지함과 동시에 실리콘 기판 상에 형성된 접합의 소모를 방지할 수 있어서 반도체 소자의 특성과 수율 및 신뢰성을 향상시킬 수 있다.The technique of the present invention made as described above can prevent the keyhole in the metal wiring contact hole and at the same time prevent the consumption of the junction formed on the silicon substrate, thereby improving the characteristics, yield and reliability of the semiconductor device.

Claims (8)

반도체 장치의 금속 배선 형성 방법에 있어서,In the metal wiring formation method of a semiconductor device, 반도체 기판 상에 접합영역을 형성하는 단계;Forming a junction region on the semiconductor substrate; 상기 접합영역 상에 장벽금속막 패턴을 형성하는 단계;Forming a barrier metal film pattern on the junction region; 제1 층간 절연막을 형성하는 단계;Forming a first interlayer insulating film; 하부 금속 배선 및 제2 층간 절연막을 형성하는 단계;Forming a lower metal wiring and a second interlayer insulating film; 상기 전체 구조에 콘택홀 형성을 위한 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern for forming a contact hole in the entire structure; 상기 포토레지스트 패턴을 식각 방지막으로 상기 제1 및 제2 층간 절연막을 건식식각하여 콘택홀을 형성하는 단계;Forming a contact hole by dry etching the first and second interlayer insulating layers using the photoresist pattern as an etch stop layer; 포토레지스트 패턴을 제거하는 단계;Removing the photoresist pattern; 상기 전체 구조에 대해 전면 건식식각을 하여 라운딩된 콘택홀 입구 부분을 형성단계; 및Forming a rounded contact hole inlet by dry etching the entire structure on the entire structure; And 상부 금속 배선막을 형성하는 단계를 포함하여 이루어진 반도체 장치의 금속 배선 형성 방법.A metal wiring forming method for a semiconductor device comprising the step of forming an upper metal wiring film. 제1항에 있어서,The method of claim 1, 상기 반도체 기판에 접합 영역을 형성하는 단계 후After forming a junction region on the semiconductor substrate 상기 반도체 기판 상에 절연막을 형성하는 단계;Forming an insulating film on the semiconductor substrate; 상기 절연막을 사진식각하여 콘택홀을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.And forming a contact hole by photolithography the insulating film. 제1항에 있어서,The method of claim 1, 상기 전체 구조에 대한 전면 식각하여 라운딩된 콘택홀 입구 부분을 형성하는 단계 후,After etching the entire structure to form a rounded contact hole inlet portion, 장벽 금속막 패턴 상부의 자연산화막을 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.And removing the native oxide film on the barrier metal film pattern. 제1항에 있어서,The method of claim 1, 상기 장벽금속막 패턴은 Ti , Ti/TiN 및 Ti/TiW 중 어느 하나로 이루어지는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.And the barrier metal film pattern is formed of any one of Ti, Ti / TiN, and Ti / TiW. 제1항에 있어서,The method of claim 1, 상기 전체 구조에 대해 전면 건식식각을 하여 라운딩된 콘택홀 입구 부분을 형성하는 건식식각은 C 및 F를 포함한 플라즈마를 사용하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.And forming a rounded contact hole inlet by front-drying the entire structure using plasma including C and F. 19. 제1항에 있어서,The method of claim 1, 상기 전체 구조에 대해 전면 건식식각을 하여 라운딩된 콘택홀 입구 부분을 형성하는 건식식각은 Ar를 포함하는 플라즈마를 사용하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.And dry etching the entire contact structure to form a rounded contact hole inlet portion using a plasma containing Ar. 제1항에 있어서,The method of claim 1, 상기 포토레지스트를 제거하는 단계는 등방성 식각으로 상기 콘택홀의 입구가 드러날때까지 상기 포토레지스트를 소정 두께만큼 제거하는 것으로 이루어지며 상기 전면 식각으로 라운딩된 콘택홀 입구 부분을 형성하는 단계 후, 상기 포토레지스트 패턴을 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.The removing of the photoresist may include removing the photoresist by a predetermined thickness until the inlet of the contact hole is exposed by isotropic etching, and after forming the contact hole inlet portion rounded by the front side etching, the photoresist. The method of forming a metal wiring of a semiconductor device, further comprising the step of removing the pattern. 제3항에 있어서,The method of claim 3, 상기 전체 구조에 대해 전면 건식식각하여 라운딩된 콘택홀 입구 부분을 형성하는 건식식각시 장벽금속막 상부의 자연 산화막을 동시에 제거하고, 인시튜 방식으로 금속 배선막을 증착하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.A metal of a semiconductor device, characterized in that the entire oxide structure is removed simultaneously with the natural oxide film on the upper part of the barrier metal film during dry etching to form a rounded contact hole inlet. Wiring formation method.
KR1019970014098A 1997-04-16 1997-04-16 Method for forming metal interconnector in semiconductor device KR100237743B1 (en)

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