KR100477821B1 - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

Info

Publication number
KR100477821B1
KR100477821B1 KR1019970077915A KR19970077915A KR100477821B1 KR 100477821 B1 KR100477821 B1 KR 100477821B1 KR 1019970077915 A KR1019970077915 A KR 1019970077915A KR 19970077915 A KR19970077915 A KR 19970077915A KR 100477821 B1 KR100477821 B1 KR 100477821B1
Authority
KR
South Korea
Prior art keywords
undercut
forming
metal wiring
semiconductor device
metal
Prior art date
Application number
KR1019970077915A
Other languages
Korean (ko)
Other versions
KR19990057836A (en
Inventor
이정석
남기원
김광철
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019970077915A priority Critical patent/KR100477821B1/en
Publication of KR19990057836A publication Critical patent/KR19990057836A/en
Application granted granted Critical
Publication of KR100477821B1 publication Critical patent/KR100477821B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure

Abstract

본 발명은 금속배선의 언더컷에 의해 발생되는 수분 확산을 방지하여 소자 특성을 향상시키는 반도체 소자의 금속배선 형성 방법을 제공하고자 하는 것으로,이를 위하여 본 발명의 금속배선 형성 방법은, 과도식각에 의해 그 에지 하부에 언더컷을 갖는 금속배선을 패터닝하는 단계; 및 상기 언더컷을 덮도록 상기 패터닝된 금속배선의 측벽에 스페이서를 형성하는 단계를 포함하여 이루어진다. 상기 스페이서는 예컨대 질화막과 같이 언더컷의 갭필링 및 수분 확산을 방지하는 물질로 이루어진다.The present invention is to provide a method for forming a metal wiring of a semiconductor device to prevent the diffusion of moisture caused by the undercut of the metal wiring to improve the device characteristics, for this purpose, the method for forming a metal wiring of the present invention by the transient etching Patterning a metallization having an undercut under the edge; And forming spacers on sidewalls of the patterned metallization to cover the undercut. The spacer is made of a material that prevents gap peeling and moisture diffusion of the undercut, such as a nitride film.

Description

반도체 소자의 금속배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 다층 금속배선을 갖는 반도체 소자 제조 방법에 관한 것으로, 특히 금속배선의 언더컷을 통해 수분이 침투되는 것을 방지하기 위한 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device having a multi-layered metal wiring, and more particularly, to a metal wiring forming method for preventing moisture from penetrating through the undercut of the metal wiring.

잘 알려진 바와 같이, 소자가 고집적화되어 감에 따라 금속배선은 다층화되어가고 있으며, 금속층간의 평탄화를 위해 금속층간 절연막으로써 SOG(spin on glass)를 사용하고 있다. 종래의 다층 금속배선 공정과 그 문제점을 도 1a 및 도 1b를 참조하여 살펴본다. 먼저, 도 1a는 소정 공정이 완료된 웨이퍼(11) 상에 예컨대 Ti/TiN과 같은 장벽 금속막(barrier metal)(12), 예컨대 텅스텐 또는 알루미늄과 같은 배선용 금속막(13), 및 예컨대 TiN과 같은 비반사층(14)을 차례로 형성한 다음, 마스크 및 식각 공정에 의해 적층된 층을 차례로 식각함으로써 하부 금속배선을 완료한 상태이다. 그런데, 도면의 점선 "A"의 내부에 도시된 바와 같이, 배선용 금속막(13)의 에지 하부에 언더컷 현상이 발생되게 된다. 즉, 식각 공정에서 금속 잔류물에 의한 금속 브리지를 방지하기 위하여 과도식각(Over Etch)을 실시하게 되는데, 이 과도식각에 의해 배선용 금속막(13)의 하부에 배치된 장벽 금속막(12)이 과도식각되어 언더컷이 발생되게 되는 것이다. 금속 브리지는 금속배선의 페일(Fail)을 가져오는 큰 원인이 되므로 현 상태에서는 과도 식각을 하지 않을 수 없는 실정이다. 한편, 도 1b는 도 1a의 전체구조 상부에 금속층간산화막(IMO-1)(15)을 형성한 상태로서, 이 금속층간산화막(15)은 통상 1000Å 정도로 얇게 형성하고 있으며, 이 얇은 산화막은 스텝커버리지가 나쁘기 때문에 언더컷 부위(도 1a의 "A")를 충분히 덮지 못한다. As is well known, as the device is highly integrated, metal wiring is becoming multilayered, and spin on glass (SOG) is used as an intermetallic insulating film for planarization between metal layers. The conventional multilayer metallization process and its problems will be described with reference to FIGS. 1A and 1B. First, FIG. 1A shows a barrier metal 12 such as Ti / TiN, for example, a wiring metal film 13 such as tungsten or aluminum, and for example TiN, on a wafer 11 on which a predetermined process is completed. After forming the anti-reflective layer 14 in sequence, the layer laminated by the mask and the etching process is etched in order to complete the lower metal wiring. By the way, as shown inside the dotted line "A" in the figure, the undercut phenomenon occurs in the lower edge of the wiring metal film 13. That is, in order to prevent metal bridges due to metal residues in the etching process, an over etching is performed. The barrier metal film 12 disposed under the wiring metal film 13 is formed by the over etching. It is overetched and undercut occurs. Since the metal bridge is a big cause of the failing of the metal wiring, the current situation is inevitable for excessive etching. 1B is a state in which the interlayer oxide film (IMO-1) 15 is formed on the entire structure of FIG. 1A, and the interlayer oxide film 15 is generally thinned to about 1000 GPa. Because of poor coverage, the undercut portion (“A” in FIG. 1A) is not sufficiently covered.

따라서, 후속 공정으로 금속층간산화막(15) 상에 SOG막을 형성할 때, 언더컷으로 인해 스텝커버리지가 불량해진 부분(도 1b의 "B")으로 SOG막으로부터의 수분이 침투하여 하부층으로 확산되므로써, 소자 특성을 테스트하는 PCT(pressure cooker test)에서 페일(fail)이 발생하게 된다.Therefore, when the SOG film is formed on the interlayer oxide film 15 by a subsequent process, moisture from the SOG film penetrates into the portion where step coverage is poor due to undercut ("B" in FIG. 1B) and diffuses into the lower layer, A failure occurs in a pressure cooker test (PCT) that tests device characteristics.

본 발명은 상기 문제점을 해결하기 위하여 안출된 것으로써, 금속배선의 언더컷에 의해 발생되는 수분 확산을 방지하여 소자 특성을 향상시키는 반도체 소자의 금속배선 형성 방법을 제공함을 그 목적으로 한다.An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device to improve the device characteristics by preventing the diffusion of moisture caused by the undercut of the metal wiring to solve the above problems.

상기 목적을 달성하기 위한 본 발명의 금속배선 형성 방법은, 과도식각에 의해 그 에지 하부에 언더컷을 갖는 금속배선을 패터닝하는 단계; 및 상기 언더컷을 덮도록 상기 패터닝된 금속배선의 측벽에 스페이서를 형성하는 단계를 포함하여 이루어진다. 상기 스페이서는 예컨대 질화막과 같이 언더컷의 갭필링 및 수분 확산을 방지하는 물질로 이루어진다.The metallization method of the present invention for achieving the above object comprises the steps of: patterning a metallization having an undercut under the edge by the transient etching; And forming spacers on sidewalls of the patterned metallization to cover the undercut. The spacer is made of a material that prevents gap peeling and moisture diffusion of the undercut, such as a nitride film.

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 다층 금속배선 공정도로서, 이를 통해 본 발명의 일실시예를 상세히 설명한다.2A to 2C are multi-layered metallization process diagrams according to an embodiment of the present invention, and one embodiment of the present invention will be described in detail.

도 2a와 같이, 소정 공정이 완료된 웨이퍼(21) 상에 장벽금속인 Ti/TiN막(22), 배선용 금속막인 텅스텐 또는 알루미늄막(23) 및 비반사층인 TiN(24)을 차례로 적층하고, 마스크 및 식각 공정에 의해 적층된 층을 차례로 식각함으로써 하부 금속배선을 완료한 다음, 언더컷 부위를 덮기 위하여 질화막(25)을 100Å 내지 200Å 정도로 얇게 형성한다. 앞서 설명하였듯이, 하부 금속배선의 패터닝을 위한 식각시 금속 브리지 방지를 위해 과도식각을 실시하므로 금속배선의 에지 하부에는 언더컷이 발생되게 된다. 이어서, 도 2b와 같이, 상기 질화막(25)을 전면식각하여 하부 금속배선의 측벽에 질화막 스페이서(25a)를 형성하고, 도 2c에 도시된 바와 같이 도 2b의 전면에 금속층간산화막(IMO-1)(26)을 형성한다. 이후 SOG막을 형성하는 등 통상의 공정을 계속한다.2A, a Ti / TiN film 22, which is a barrier metal, a tungsten or aluminum film 23, which is a wiring metal film, and a TiN 24, which is a non-reflective layer, are sequentially stacked on the wafer 21 where a predetermined process is completed. By sequentially etching the stacked layers by a mask and an etching process, the lower metal wiring is completed, and the nitride film 25 is thinly formed to have a thickness of about 100 kPa to about 200 kPa to cover the undercut portion. As described above, since the overetch is performed to prevent the metal bridge during etching for the patterning of the lower metal wiring, an undercut is generated at the lower edge of the metal wiring. Subsequently, as shown in FIG. 2B, the nitride film 25 is etched entirely to form a nitride film spacer 25a on the sidewall of the lower metal wiring, and as shown in FIG. 2C, an interlayer oxide film IMO-1 on the entire surface of FIG. 2B. (26). After that, the usual steps such as forming an SOG film are continued.

통상적으로 질화막은 그 특성상 갭필링 능력이 매우 우수하여, 얇은 두께로 증착되는 질화막으로도 배선용 금속막의 언더컷을 충분히 채울 수 있으며, 질화막 스페이서에 의해 금속층간산화막의 스텝커버리지를 개선한다. 동시에, 언더컷 부위의 질화막은 SOG로부터 금속배선의 하부층으로 확산되는 수분을 효과적으로 막아준다.In general, the nitride film has a very good gap peeling capability, so that the undercut of the metal film for wiring can be sufficiently filled with a nitride film deposited with a thin thickness, and the step coverage of the interlayer oxide film is improved by the nitride film spacer. At the same time, the nitride film of the undercut portion effectively prevents moisture from diffusing into the lower layer of the metallization.

이상에서, 설명한 바와 같이 본 발명은 언더컷의 갭필링 및 수분 침투 방지를 위한 질화막 스페이서를 사용하는 것에 그 특징이 있는 것으로, 질화막 대신에 다른 물질을 사용할 수 있는데, 전도층이든 절연층이든 언더컷을 채우면서 공정조건 및 특성 등 기타 제반 조건을 만족하는 물질이면 될 것이다.As described above, the present invention is characterized by using a nitride film spacer for preventing gap penetration and moisture penetration of the undercut, and other materials may be used instead of the nitride film. In addition, the material may satisfy other conditions such as process conditions and characteristics.

본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위내에서 여러 가지 치환, 변형 및 변경이 가능하다.The present invention is not limited by the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the spirit of the present invention.

본 발명은 금속배선의 언더컷에 의해 발생되는 수분 확산을 방지하여 PCT(pressure cooker test)에서의 소자 페일(Fail)을 방지하는 효과가 있다.The present invention has the effect of preventing the device failure in the pressure cooker test (PCT) by preventing the diffusion of moisture caused by the undercut of the metal wiring.

도 1a 및 도 1b는 종래기술에 따른 다층 금속배선 공정도.1a and 1b is a multilayer metallization process diagram according to the prior art.

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 다층 금속배선 공정도.2a to 2c is a multilayer metallization process diagram according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

22 : Ti/TiN 23 : 텅스텐 또는 알루미늄22: Ti / TiN 23: tungsten or aluminum

24 : TiN 25 : 질화막24: TiN 25: nitride film

25a : 질화막 스페이서 26 : 금속층간산화막25a: nitride film spacer 26: metal interlayer oxide film

Claims (3)

소정공정이 완료된 기판 상에 Ti/TiN 장벽금속층을 형성하는 단계;Forming a Ti / TiN barrier metal layer on the substrate on which the predetermined process is completed; 상기 Ti/TiN 장벽금속 상에 배선용 금속층 및 TiN 비반사층을 형성하는 단계;Forming a wiring metal layer and a TiN anti-reflective layer on the Ti / TiN barrier metal; 마스크 및 식각 공정으로 상기 기판 상에 적층된 막들을 식각하여 금속배선패턴을 형성하되, 상기 식각시 과도 식각을 진행하여 상기 패턴의 그 에지 하부에 언더컷을 형성하는 단계;Forming a metallization pattern by etching the layers stacked on the substrate by a mask and an etching process, and performing an overetch during the etching to form an undercut under the edge of the pattern; 상기 언더컷을 통한 수분 확산을 방지하기 위하여 상기 언더컷을 갭필하도록상기 패터닝된 금속배선의 측벽에 수분확산방지 물질의 스페이서를 형성하는 단계;및Forming a spacer of a moisture diffusion preventing material on sidewalls of the patterned metallization to gapfill the undercut to prevent moisture diffusion through the undercut; and 전체구조 상분에 금속층간산화막과 SOG막을 적층 형성하는 단계Laminating a metal interlayer oxide film and an SOG film on the whole structure 를 포함하여 이루어진 반도체 소자의 금속배선 형성 방법.Metal wiring forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 수분확산방지 물질은 질화막인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The water diffusion preventing material is a nitride film forming method of a semiconductor device, characterized in that the nitride film. 제1항에 있어서,The method of claim 1, 상기 스페이서는 증착 및 전면식각에 의해 형성하는 반도체 소자의 금속배선 형성 방법.The spacer is a metal wiring forming method of a semiconductor device formed by deposition and full surface etching.
KR1019970077915A 1997-12-30 1997-12-30 Metal wiring formation method of semiconductor device KR100477821B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970077915A KR100477821B1 (en) 1997-12-30 1997-12-30 Metal wiring formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970077915A KR100477821B1 (en) 1997-12-30 1997-12-30 Metal wiring formation method of semiconductor device

Publications (2)

Publication Number Publication Date
KR19990057836A KR19990057836A (en) 1999-07-15
KR100477821B1 true KR100477821B1 (en) 2005-07-07

Family

ID=37303431

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970077915A KR100477821B1 (en) 1997-12-30 1997-12-30 Metal wiring formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100477821B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100979232B1 (en) * 2003-07-15 2010-08-31 매그나칩 반도체 유한회사 The method for forming capacitor in semiconductor device
DE102019131909A1 (en) * 2018-11-30 2020-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. MULTILAYER STRUCTURES AND MANUFACTURING METHODS
US11004685B2 (en) 2018-11-30 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer structures and methods of forming

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02187069A (en) * 1988-11-10 1990-07-23 Texas Instr Inc <Ti> Transistor having radiation resistance and manufacture thereof
JPH02201928A (en) * 1989-01-30 1990-08-10 Nec Corp Formation of pattern
JPH02224276A (en) * 1988-10-28 1990-09-06 Texas Instr Inc <Ti> Non-defectiveness of improved gate silicon dioxide and method of realizing it
JPH05136421A (en) * 1991-10-24 1993-06-01 Kaho Denshi Kofun Yugenkoshi Manufacture of eeprom cell and eeprom cell
JPH0730125A (en) * 1993-07-07 1995-01-31 Semiconductor Energy Lab Co Ltd Semiconductor device and its production
JPH0738092A (en) * 1991-11-29 1995-02-07 Sumitomo Metal Ind Ltd Manufacture of semiconductor device
JPH09307007A (en) * 1996-05-17 1997-11-28 Sanyo Electric Co Ltd Method of fabricating semiconductor storage

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02224276A (en) * 1988-10-28 1990-09-06 Texas Instr Inc <Ti> Non-defectiveness of improved gate silicon dioxide and method of realizing it
JPH02187069A (en) * 1988-11-10 1990-07-23 Texas Instr Inc <Ti> Transistor having radiation resistance and manufacture thereof
JPH02201928A (en) * 1989-01-30 1990-08-10 Nec Corp Formation of pattern
JPH05136421A (en) * 1991-10-24 1993-06-01 Kaho Denshi Kofun Yugenkoshi Manufacture of eeprom cell and eeprom cell
JPH0738092A (en) * 1991-11-29 1995-02-07 Sumitomo Metal Ind Ltd Manufacture of semiconductor device
JPH0730125A (en) * 1993-07-07 1995-01-31 Semiconductor Energy Lab Co Ltd Semiconductor device and its production
JPH09307007A (en) * 1996-05-17 1997-11-28 Sanyo Electric Co Ltd Method of fabricating semiconductor storage

Also Published As

Publication number Publication date
KR19990057836A (en) 1999-07-15

Similar Documents

Publication Publication Date Title
JP2934353B2 (en) Semiconductor device and manufacturing method thereof
US5470793A (en) Method of via formation for the multilevel interconnect integrated circuits
US6232656B1 (en) Semiconductor interconnect formed over an insulation and having moisture resistant material
KR20020063015A (en) Bonding pad structure of semiconductor device and method for fabricating the same
US6372616B1 (en) Method of manufacturing an electrical interconnection of a semiconductor device using an erosion protecting plug in a contact hole of interlayer dielectric layer
KR100477821B1 (en) Metal wiring formation method of semiconductor device
US4510678A (en) Method for manufacturing a monolithically integrable circuit with a multilayer wiring structure
US4601939A (en) Composite insulator structure
JPH05234935A (en) Semiconductor device and its manufacture
JP3270863B2 (en) Semiconductor device
KR100257481B1 (en) Method for forming metal-interconnection layer having tungsten plug in semiconductor device
JPH05326722A (en) Manufacture of semiconductor device
KR100458078B1 (en) Method for forming metal interconnection of semiconductor device to reduce em phenomenon and leakage current
KR100237743B1 (en) Method for forming metal interconnector in semiconductor device
JPH11260967A (en) Semiconductor device and its manufacture
KR0168164B1 (en) Method of fabricating semiconductor device
KR100216271B1 (en) Method of fabricating interconnector in semiconductor device
KR100607753B1 (en) Method for forming a metal layer of semiconductor device
KR20050032305A (en) Method of forming metal line in semiconductor devices
KR0167602B1 (en) Method of forming multilayered metal wire for ic and semiconductor devices therewith
KR100193889B1 (en) Via hole formation method of semiconductor device
KR100332131B1 (en) Method for forming metal film in semiconductor device
KR20000056260A (en) Method of forming a contact in a semiconductor device
KR100304967B1 (en) Metal line of semiconductor device and method for fabricating the same
KR0166826B1 (en) Method of interlayer insulating film in a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110222

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee