KR100332131B1 - Method for forming metal film in semiconductor device - Google Patents

Method for forming metal film in semiconductor device Download PDF

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Publication number
KR100332131B1
KR100332131B1 KR1019950051292A KR19950051292A KR100332131B1 KR 100332131 B1 KR100332131 B1 KR 100332131B1 KR 1019950051292 A KR1019950051292 A KR 1019950051292A KR 19950051292 A KR19950051292 A KR 19950051292A KR 100332131 B1 KR100332131 B1 KR 100332131B1
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metal layer
titanium
deposited
forming
tungsten
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KR1019950051292A
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Korean (ko)
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KR970052935A (en
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홍영기
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a metal film in a semiconductor device is provided to be capable of improving gap-filling and preventing generation of voids between titanium and tungsten. CONSTITUTION: After forming an insulating layer(3) on a silicon substrate(1) having a junction region(2), a contact hole is formed to expose the junction region(2) by selectively etching the insulating layer(3). A barrier metal film(10) is formed on the resultant structure by sputtering deposition. At this time, a tungsten film(4) is deposited on the bottom of the contact hole, a titanium film(5) is deposited at both sidewalls of the contact hole, and a titanium and tungsten film(6) is deposited on the insulating layer(3). A metal film(7) is formed on the resultant structure including the contact hole, and an anti-reflective coating(9) is formed on the metal film(7).

Description

반도체 소자의 금속층 형성 방법Metal layer formation method of semiconductor device

본 발명은 반도체 소자의 금속층 형성 방법에 관한 것으로, 특히 층덮힘(Step Coverage) 및 전기적 특성을 향상시킬 수 있도록 한 반도체 소자의 금속층 형성 방법에 관한 것이다.The present invention relates to a method of forming a metal layer of a semiconductor device, and more particularly to a method of forming a metal layer of a semiconductor device to improve the step coverage and electrical properties.

일반적으로 반도체 소자의 제조 공정에서 금속층은 이중 또는 다중 구조로 형성되며, 금속층 및 접합 영역 그리고 금속층간의 접속은 절연층에 형성된 콘택홀(Contact Hole)을 통해 이루어진다. 그런데 반도체 소자가 고집적화됨에 따라 상기 콘택 홀의 크기도 미세화되기 때문에 상기 콘택 홀에서 금속의 층덮힌 상태가 불량해지며, 이로 인해 금속층간의 접속이 불량지거나, 표면의 평탄화가 저하되어 소자의 수율이 저하된다. 그러면 종래 반도체 소자의 금속층 형성 방법을 설명하면 다음과 같다.In general, in the manufacturing process of a semiconductor device, the metal layer is formed in a double or multiple structure, and the metal layer, the junction region, and the connection between the metal layers are made through contact holes formed in the insulating layer. However, as the semiconductor device is highly integrated, the size of the contact hole is also miniaturized, so that the state of metal layer covering is poor in the contact hole. As a result, the connection between the metal layers is poor, or the surface flatness is lowered, thereby lowering the yield of the device. do. A method of forming a metal layer of a conventional semiconductor device is as follows.

종래에는 접합 영역이 형성된 실리콘 기판상에 절연층을 형성하고 상기 접합 영역이 노출되도록 상기 절연층을 패터닝하여 콘택 홀을 형성한다. 그리고 상기 접합 영역과의 접촉 저항을 감소시키며, 상기 실리콘 기판과의 접착성을 증가시키기 위하여 전체 상부면에 티타늄(Ti)을 증착한 후 반응성 스퍼터링(Reactive Sputtering) 방법을 이용하여 상기 티타늄상에 티타늄 나이트라이드(TiN)를 증착하고 확산 방지 효과를 증대시키기 위한 열처리 공정을 실시하여 베리어 금속층을 형성한다. 이후 전체 상부면에 알루미늄(Al)과 같은 금속을 증착하여 금속층을 형성한다. 그런데 상기와 같은 방법은 상기 베리어 금속층을 형성하기 위한 스퍼터링 증착 공정시 상기 티타늄 및 티타늄 나이트라이드의 층덮힘 상태가 불량하며, 그레인과 그레인의 계면에 보이드(Void)가 형성되기 때문에 금속층의 전기적 특성이 저하되는 문제점이 있다.Conventionally, an insulating layer is formed on a silicon substrate on which a junction region is formed, and the contact layer is formed by patterning the insulating layer to expose the junction region. In order to reduce contact resistance with the junction region and to increase adhesion to the silicon substrate, titanium (Ti) is deposited on the entire upper surface thereof, and then titanium is deposited on the titanium using a reactive sputtering method. A barrier metal layer is formed by depositing nitride (TiN) and performing a heat treatment process to increase the diffusion preventing effect. Then, a metal layer is formed by depositing a metal such as aluminum (Al) on the entire upper surface. However, in the above method, the layer covering state of the titanium and the titanium nitride is poor in the sputtering deposition process for forming the barrier metal layer, and since the voids are formed at the interface between grains and grains, the electrical characteristics of the metal layer are poor. There is a problem of deterioration.

따라서 본 발명은 콘택 홀의 저면에는 텅스텐을 , 측벽에는 티타늄을 그리고 절연층상에는 티타늄 및 텅스텐이 증착되도록 스퍼터링 증착 공정을 실시하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속층 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention provides a method for forming a metal layer of a semiconductor device that can solve the above-mentioned disadvantages by performing a sputtering deposition process so that tungsten is deposited on the bottom of the contact hole, titanium is deposited on the sidewalls, and titanium and tungsten are deposited on the insulating layer. There is a purpose.

상기한 목적을 달성하기 위한 본 발명은 접합 영역이 형성된 실리콘 기판상에 절연층을 형성하고, 상기 접합 영역이 노출되도록 상기 절연층을 패터닝하여 콘택 홀을 형성하는 단계와, 상기 단계로부터 상기 콘택 홀의 저면에는 텅스텐이 증착되며, 측벽에는 티타늄이 증착되고 상기 절연층상에는 티타늄 및 텅스텐이 증착되도록 스퍼터링 증착 공정을 실시하여 베리어 금속층을 형성하는 단계와, 상기 단계로부터 상기 베리어 금속층상에 금속층을 형성한 후 사진 공정시 상기 금속층의 높은 반사율로 인해 발생되는 불량을 방지하기 위하여 상기 금속층상에 반사 방지막을 형성하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, an insulating layer is formed on a silicon substrate on which a junction region is formed, and the contact layer is formed by patterning the insulation layer to expose the junction region. After the tungsten is deposited on the bottom surface, titanium is deposited on the sidewalls, and titanium and tungsten are deposited on the insulating layer to form a barrier metal layer, and the metal layer is formed on the barrier metal layer. Forming an anti-reflection film on the metal layer in order to prevent defects caused by the high reflectance of the metal layer during the photographing process.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제 1A 내지 제 1C 도는 본 발명에 따른 반도체 소자의 금속층 형성 방법을 설명하기 위한 소자의 단면도로서,1A to 1C are cross-sectional views of a device for explaining a method of forming a metal layer of a semiconductor device according to the present invention.

제 1A 도는 접합 영역(2)이 형성된 실리콘 기판(1)상에 절연층(3)을 형성하고, 상기 접합 영역(2)이 노출되도록 상기 절연층(3)을 패터닝하여 콘택 홀(8)을 형성한 상태의 단면도이고, 제 1B 도는 상기 콘택 홀(8)의 저면에는 텅스텐(4)이 증착되며, 측벽에는 티타늄(5)이 증착되고 상기 절연층(3)상에는 티타늄 및 텅스텐(6)이 증착되도록 스퍼터링 증착 공정을 실시하여 베리어 금속층(10)을 형성한 상태의 단면도로서, 상기 스퍼터링 증착 공정시 상기 텅스텐(4) 및 티타늄(5)은 각각 200 내지 400℃의 온도에서 400 내지 600Å의 두께로 증착한다.An insulating layer 3 is formed on the silicon substrate 1 having the 1A or the junction region 2 formed thereon, and the insulating layer 3 is patterned so that the junction region 2 is exposed to form the contact hole 8. In FIG. 1B, tungsten 4 is deposited on the bottom surface of the contact hole 8, titanium 5 is deposited on the sidewall, and titanium and tungsten 6 are deposited on the insulating layer 3. A cross-sectional view of a barrier metal layer 10 formed by performing a sputtering deposition process to be deposited. In the sputtering deposition process, the tungsten 4 and the titanium 5 each have a thickness of 400 to 600 kPa at a temperature of 200 to 400 ° C. To be deposited.

제 1C 도는 상기 베리어 금속층(10)상에 알루미늄(Al)과 같은 금속을 증착하여 금속층(7)을 형성한 후 사진 공정시 상기 금속층(7)의 높은 반사율로 인해 발생되는 불량을 방지하기 위하여 상기 금속층(7)상에 티타늄 및 티타늄 나이트라이드(Ti/TiN)를 순차적으로 증착하여 반사 방지막(9)을 형성한 상태의 단면도로서, 상기 반사 방지막(9)은 100 내지 200Å의 두께로 형성한다.In FIG. 1C, the metal layer 7 is formed by depositing a metal such as aluminum (Al) on the barrier metal layer 10, and then, in order to prevent defects caused by high reflectance of the metal layer 7 during the photolithography process. Titanium and titanium nitride (Ti / TiN) are sequentially deposited on the metal layer 7 to form an anti-reflection film 9. The anti-reflection film 9 is formed to a thickness of 100 to 200 Å.

상술한 바와 같이 본 발명에 의하면 콘택 홀의 저면에는 텅스텐을, 측벽에는 티타늄을 그리고 절연층상에는 티타늄 및 텅스텐이 증착되도록 스퍼터링 증착 공정을 실시하므로써 금속층의 층덮힘이 향상된다. 그리고 상기 티타늄 및 티타늄 텅스텐의 그레인과 그레인 사이에 보이드의 형성이 방지되어 소자의 전기적 특성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the sputtering deposition process is performed such that tungsten is deposited on the bottom of the contact hole, titanium is formed on the sidewall, and titanium and tungsten are deposited on the insulating layer. And the formation of voids between the grains and grains of the titanium and titanium tungsten is prevented has an excellent effect that can improve the electrical properties of the device.

제 1A 내지 제 1C 도는 본 발명에 따른 반도체 소자의 금속층 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a metal layer of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1: 실리콘 기판 2: 접합 영역1: silicon substrate 2: junction area

3 : 절연층 4: 텅스텐3: insulation layer 4: tungsten

5: 티타늄 6: 티타늄 나이트라이드5: titanium 6: titanium nitride

7: 금속층 8: 콘택 홀7: metal layer 8: contact hole

9: 반사 방지막 10: 베리어 금속층9: anti-reflection film 10: barrier metal layer

Claims (4)

반도체 소자의 금속층 형성 방법에 있어서,In the metal layer formation method of a semiconductor element, 접합 영역이 형성된 실리콘 기판상에 절연층을 형성하고, 상기 접합 영역이 노출되도록 상기 절연층을 패터닝하여 콘택 홀을 형성하는 단계와,Forming an insulating layer on the silicon substrate on which the bonding region is formed, and patterning the insulating layer to expose the bonding region to form a contact hole; 상기 단계로부터 상기 콘택 홀의 저면에는 텅스텐이 증착되며, 측벽에는 티타늄이 증착되고 상기 절연층상에는 티타늄 및 텅스텐이 증착되도록 스퍼터링 증착 공정을 실시하여 베리어 금속층을 형성하는 단계와,Forming a barrier metal layer by performing a sputtering deposition process such that tungsten is deposited on the bottom of the contact hole, titanium is deposited on the sidewall, and titanium and tungsten are deposited on the insulating layer; 상기 단계로부터 상기 베리어 금속층상에 금속층을 형성한 후 사진 공정시 상기 금속층의 높은 반사율로 인해 발생되는 불량을 방지하기 위하여 상기 금속층상에 반사 방지막을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.Forming a metal layer on the barrier metal layer from the step, and then forming an anti-reflection film on the metal layer to prevent defects caused by the high reflectance of the metal layer during the photolithography process. Forming method. 제 1 항에 있어서,The method of claim 1, 상기 텅스텐 및 티타늄은 각각 200 내지 400℃의 온도에서 400 내지 600Å의 두께로 증착되는 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The tungsten and titanium is a metal layer forming method of the semiconductor device, characterized in that deposited at a thickness of 400 to 600 kPa at a temperature of 200 to 400 ℃ respectively. 제 1 항에 있어서,The method of claim 1, 상기 반사 방지막은 티타늄 및 티타늄 나이트라이드가 순차적으로 증착된 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The anti-reflection film is a method of forming a metal layer of a semiconductor device, characterized in that the titanium and titanium nitride sequentially deposited. 제 1 또는 제 3 항에 있어서,The method according to claim 1 or 3, 상기 반사 방지막은 100 내지 200Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The anti-reflection film is a metal layer forming method of a semiconductor device, characterized in that formed in a thickness of 100 to 200Å.
KR1019950051292A 1995-12-18 1995-12-18 Method for forming metal film in semiconductor device KR100332131B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133646A (en) * 1984-12-03 1986-06-20 Toshiba Corp Manufacture of semiconductor device
JPH05347269A (en) * 1992-06-16 1993-12-27 Sony Corp Manufacture of semiconductor device
JPH0689897A (en) * 1992-09-08 1994-03-29 Sony Corp Formation of wiring
JPH0745702A (en) * 1993-07-27 1995-02-14 Nec Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133646A (en) * 1984-12-03 1986-06-20 Toshiba Corp Manufacture of semiconductor device
JPH05347269A (en) * 1992-06-16 1993-12-27 Sony Corp Manufacture of semiconductor device
JPH0689897A (en) * 1992-09-08 1994-03-29 Sony Corp Formation of wiring
JPH0745702A (en) * 1993-07-27 1995-02-14 Nec Corp Manufacture of semiconductor device

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