KR100265837B1 - Method for forming barrier metal layer of semiconductor device - Google Patents
Method for forming barrier metal layer of semiconductor device Download PDFInfo
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- KR100265837B1 KR100265837B1 KR1019970029090A KR19970029090A KR100265837B1 KR 100265837 B1 KR100265837 B1 KR 100265837B1 KR 1019970029090 A KR1019970029090 A KR 1019970029090A KR 19970029090 A KR19970029090 A KR 19970029090A KR 100265837 B1 KR100265837 B1 KR 100265837B1
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 title abstract description 16
- 239000002184 metal Substances 0.000 title abstract description 16
- 230000004888 barrier function Effects 0.000 title abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000004544 sputter deposition Methods 0.000 claims abstract description 6
- 239000010936 titanium Substances 0.000 claims description 42
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 29
- 238000000151 deposition Methods 0.000 claims description 17
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 238000001816 cooling Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005336 cracking Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 4
- 230000008021 deposition Effects 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
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Abstract
Description
본 발명은 반도체 소자 제조 분야에 관한 것으로 특히, 장벽금속막으로 이용되는 Ti막의 균열을 방지할 수 있는 장벽금속막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method of forming a barrier metal film capable of preventing cracking of a Ti film used as a barrier metal film.
실리콘 기판을 사용하는 반도체 소자의 전기적 연결을 위하여 Al막을 금속 배선막으로 사용하는데, 알루미늄막 증착 후의 열처리 과정에서 접합 파괴(junction spiking) 문제가 발생한다.An Al film is used as a metal wiring film for the electrical connection of a semiconductor device using a silicon substrate, and a junction spiking problem occurs in the heat treatment process after the deposition of the aluminum film.
접합 파괴는 Si과 Al이 상호 확산됨으로 인하여 접합이 파괴되는 현상으로서 이를 방지하기 위하여 Al에 수 %의 Si을 첨가하여 Al로의 실리콘 확산을 억제하거나 Si과 Al 사이에 확산 방지 역할을 하는 장벽금속막을 형성하는 것이 일반적이다.Bond breakage is a phenomenon in which junction breakage is caused by the mutual diffusion of Si and Al. In order to prevent this, several percent of Si is added to Al to suppress the diffusion of silicon into Al or a barrier metal film that serves to prevent diffusion between Si and Al. It is common to form.
장벽금속막이란 접합 파괴 방지를 위해 Al과 실리콘 접합 사이에 증착되는 확산 방지용 금속막으로서, Al 및 Si과의 반응성이 없고 고온 안정성이 우수해야하며 Al, Si 등의 확산 억제 능력이 높고 실리콘과의 저항성 접촉(ohmic contact)을 갖는 금속이어야 한다. 현재 가장 일반적으로 사용되는 금속으로서는 TiW과 TiN이 사용된다. TiW은 W에 10 % 내외의 Ti이 혼합되어 있는 타겟(target)을 사용하여 증착되며, TiN은 Ti 타겟을 Ar 및 N2분위기에서 스퍼터링(sputtering) 증착하여 TiN을 형성시키는 반응성(reactive) 스퍼터링 증착법에 의해 증착된다. 증착된 TiN은 Ti와 N 간의 화학당량비가 장벽 특성에 영향을 주며 1:1일 경우 가장 바람직하다. TiN 없이 Ti만을 사용할 때 Al과 Ti가 350 ℃부터 반응하여 Al3Ti 화합물을 형성하고, 400 ℃ 이상에서는 Si이 확산되어 Al5Ti7Si2화합물을 형성하여 접촉 불량을 일으킨다. 또한, Ti막이 얇아야 실리콘의 소모를 줄일 수 있기 때문에 안정된 저항성 접촉을 할 수 있으며 계면의 특성을 향상시킬 수 있다.The barrier metal film is a diffusion preventing metal film deposited between Al and silicon junctions in order to prevent the fracture of the junction. The barrier metal film should have no reactivity with Al and Si, and be excellent in high temperature stability. It must be a metal with an ohmic contact. Currently, TiW and TiN are used as the most commonly used metals. TiW is deposited using a target mixed with about 10% of Ti in W. TiN is a reactive sputtering deposition method in which TiN is formed by sputtering deposition of Ti target in Ar and N 2 atmospheres. Is deposited by. The deposited TiN is most preferable when the chemical equivalence ratio between Ti and N affects the barrier properties and is 1: 1. When only Ti is used without TiN, Al and Ti react to form an Al 3 Ti compound at 350 ° C., and at 400 ° C. or more, Si diffuses to form an Al 5 Ti 7 Si 2 compound, causing contact failure. In addition, since the Ti film is thin, the consumption of silicon can be reduced, thereby making stable ohmic contact and improving the interface characteristics.
종래의 Ti/TiN 장벽금속막은 300 ℃ 고온에서 Ar 가스 및 3.0 Kw의 RF 전력을 인가하여 스퍼터링 방법으로 Ti를 약 300 Å 증착하고, TiN을 약 300℃에서 증착한다. 이때 Ti막 증착 챔버(chamber)에서 TiN막 증착 챔버로 기판을 이동하는 동안 기판의 온도 강하를 막기 위하여 중간 지점을 TiN 증착 온도인 250 내지 300 ℃로 기판 온도를 유지하였다.In the conventional Ti / TiN barrier metal film, Ti is deposited at about 300 Pa by a sputtering method by applying Ar gas and 3.0 Kw of RF power at a high temperature of 300 ° C., and TiN is deposited at about 300 ° C. At this time, in order to prevent the temperature drop of the substrate while moving the substrate from the Ti film deposition chamber (Chamber) to the TiN film deposition chamber, the substrate temperature was maintained at a TiN deposition temperature of 250 to 300 ℃.
상기와 같이 이루어지는 종래 기술은 Ti 막을 고온에서 유지함으로써 그레인(grain) 크기가 증가하여 Ti막의 면저항이 낮아지고, 열처리에 의한 스트레스(stress) 증가로 Ti막에 균열이 발생하고 파편이 증가되어 Ti막 손실이 일어난다. 따라서, 알루미늄(Al)과 실리콘 기판과의 장벽 역할을 제대로 수행하지 못하게 되는 단점이 발생한다.In the prior art, the Ti film is maintained at a high temperature, the grain size is increased, the sheet resistance of the Ti film is lowered, and the Ti film is cracked and the fragments are increased due to the stress caused by heat treatment. Loss occurs. Therefore, a disadvantage arises in that it does not function properly as a barrier between aluminum (Al) and a silicon substrate.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 Ti 막의 균열을 방지할 수 있는 반도체 장치의 장벽금속막 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method of forming a barrier metal film of a semiconductor device that can prevent the crack of the Ti film.
도1은 본 발명의 일실시예에 따른 반도체 장치의 장벽금속막 형성 공정 단면도.1 is a cross-sectional view of a barrier metal film forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing
10: 실리콘 기판 11: 층간절연막10: silicon substrate 11: interlayer insulating film
12: 콘택홀 13: Ti막12: contact hole 13: Ti film
14: TiN 막 15: Al 막14: TiN film 15: Al film
상기 목적을 달성하기 위한 본 발명은, 실리콘 기판 상에 형성된 하부구조를 덮는 층간절연막을 선택적으로 식각하여 상기 실리콘 기판을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀을 통하여 상기 실리콘 기판과 접하는 티타늄(Ti)막을 증착하는 단계; 상기 실리콘 기판을 0 ℃ 내지 23 ℃ 온도 범위에서 냉각시키는 단계; 및 상기 티타늄막 상에 티타늄나이트라이드(TiN)막을 증착하는 단계를 포함하는 반도체 장치 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming a contact hole exposing a silicon substrate by selectively etching an interlayer insulating layer covering a substructure formed on the silicon substrate; Depositing a titanium (Ti) film in contact with the silicon substrate through the contact hole; Cooling the silicon substrate at a temperature ranging from 0 ° C. to 23 ° C .; And depositing a titanium nitride (TiN) film on the titanium film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 살펴본다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도1에 도시한 바와 같이 소정의 하부층 형성이 완료된 실리콘 기판(10)을 덮는 층간절연막(11)을 선택적으로 식각하여 상기 실리콘 기판(10)을 노출시키는 콘택홀(12)을 형성한 후, 약 300 ℃ 온도, Ar 20 sccm, 1.7×107torr 챔버 압력에서 약 3.0 Kw RF 전력을 인가하여 스퍼터링 방법으로 300 내지 500 Å의 Ti 막(13)을 증착한다. 이후 TiN 막을 증착하기 전 단계로서, Ti막과 TiN막 간의 접착력 개선 및 고온에 의한 Ti 막의 스트레스 변화를 줄이기 위해 0 내지 23 ℃의 상온에서 기판 냉각을 실시한다.First, as shown in FIG. 1, the
다음으로, 약 300 ℃ 온도, N220 sccm, Ar 25 sccm 정도의 가스와 1 ∼ 2×107torr의 챔버 압력에서 5.0 Kw의 RF 전력을 인가하여 스퍼터링 방법으로 700 내지 1000 Å의 TiN막(15)을 증착한다.Next, a TiN film of 700 to 1000 kPa was applied by sputtering by applying RF power of 5.0 Kw at a temperature of about 300 ° C., N 2 20 sccm, Ar 25 sccm, and a chamber pressure of 1-2 × 10 7 torr. 15) Deposit.
이후 약 250 ℃ 온도에서 약 11 Kw의 RF 전력으로 900 내지 1000Å의 알루미늄막(15)을 증착한다.Thereafter, an
다음의 표1 및 표2는 종래의 Ti막을 증착한 후 TiN막을 증착하기 위하여 챔버를 이동하는 동안에 기판 온도를 약 300 ℃로 유지하는 경우와, 본 발명에 따라 기판 온도를 약 0 ℃로 유지하는 경우의 스트레스 및 면저항을 비교한 것이다.Tables 1 and 2 below show that the substrate temperature is maintained at about 300 ° C. during the movement of the chamber to deposit the TiN film after the deposition of the conventional Ti film, and the substrate temperature is maintained at about 0 ° C. according to the present invention. The stress and sheet resistance of the case were compared.
표1에 나타난 결과와 같이 Ti막 증착과 TiN막 증착 사이에 기판 온도를 0 ℃로 유지함으로써 Ti 막의 스트레스가 감소하여 Ti막의 균열 발생이 방지된다. 또한, 표2의 결과로 알 수 있듯이 Ti 막의 면저항 변동율이 감소하여 이후에 증착되는 TiN막의 면저항 변동율도 비교적 양호하다. 참고로, 상기 면저항의 변동율은 Ti막 및 TiN막의 여러 부분에서 면저항을 측정하여 최고값과 최저값을 제외한 나머지 측정값의 평균을 구하고, 최고값과 최저값의 차이를 평균값의 2배되는 값으로 나누고 그 백분율로 구한 것이다.As shown in Table 1, by maintaining the substrate temperature at 0 ° C between the deposition of the Ti film and the deposition of the TiN film, the stress of the Ti film is reduced and the cracking of the Ti film is prevented. In addition, as can be seen from the results of Table 2, the sheet resistance variation rate of the Ti film is decreased, so that the sheet resistance variation rate of the TiN film deposited thereafter is relatively good. For reference, the variation rate of the sheet resistance is obtained by measuring the sheet resistance at various parts of the Ti film and the TiN film, obtaining an average of the remaining measured values except for the highest value and the lowest value, and dividing the difference between the highest value and the lowest value by twice the average value. It is obtained as a percentage.
본 발명에서는 Ti막 증착 단계와 TiN막 증착 단계 사이에서 기판을 0 ℃ 내지 23℃로 냉각시킴으로써 Ti막의 면저항 변동율을 줄일 수 있다. 또한, TiN막의 면저항 변동율도 양호한 것으로 보아 Ti막 상에 형성되는 TiN막에 대한 Ti막의 영향이 줄어들어 TiN막의 특성을 유지할 수 있음을 알 수 있고, Ti막 증착 후 기판을 고온으로 유지하여 발생하는 Ti막의 스트레스 변화에 의한 균열을 방지하여 Al-Si 접합 파괴 발생 및 기판 접촉 지역의 전류손실, 실리콘 기판과 계면의 특성을 향상시킬 수 있다.In the present invention, the sheet resistance variation rate of the Ti film can be reduced by cooling the substrate to 0 ° C to 23 ° C between the Ti film deposition step and the TiN film deposition step. In addition, since the TiN film has a good sheet resistance variation rate, it can be seen that the influence of the Ti film on the TiN film formed on the Ti film is reduced, thereby maintaining the properties of the TiN film. It is possible to prevent cracking due to the stress change of the film, thereby improving Al-Si junction breakdown, current loss in the contact area of the substrate, and improving the characteristics of the silicon substrate and the interface.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 Ti막의 장벽금속막으로서의 특성을 향상시켜 소자의 신뢰성을 향상시킬 수 있다.According to the present invention as described above, the reliability of the device can be improved by improving the characteristics of the Ti film as a barrier metal film.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029090A KR100265837B1 (en) | 1997-06-30 | 1997-06-30 | Method for forming barrier metal layer of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970029090A KR100265837B1 (en) | 1997-06-30 | 1997-06-30 | Method for forming barrier metal layer of semiconductor device |
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| Publication Number | Publication Date |
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| KR19990004930A KR19990004930A (en) | 1999-01-25 |
| KR100265837B1 true KR100265837B1 (en) | 2000-09-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970029090A KR100265837B1 (en) | 1997-06-30 | 1997-06-30 | Method for forming barrier metal layer of semiconductor device |
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| KR (1) | KR100265837B1 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950015651A (en) * | 1993-11-11 | 1995-06-17 | 김주용 | Method of forming diffusion preventing metal layer of semiconductor device |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950015651A (en) * | 1993-11-11 | 1995-06-17 | 김주용 | Method of forming diffusion preventing metal layer of semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR19990004930A (en) | 1999-01-25 |
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