KR20010011307A - Method for forming metal wire using zirconiumdiboride layer as diffusion barrier - Google Patents
Method for forming metal wire using zirconiumdiboride layer as diffusion barrier Download PDFInfo
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- KR20010011307A KR20010011307A KR1019990030613A KR19990030613A KR20010011307A KR 20010011307 A KR20010011307 A KR 20010011307A KR 1019990030613 A KR1019990030613 A KR 1019990030613A KR 19990030613 A KR19990030613 A KR 19990030613A KR 20010011307 A KR20010011307 A KR 20010011307A
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- film
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- diffusion barrier
- zrb
- metal wiring
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 34
- 239000002184 metal Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000004888 barrier function Effects 0.000 title claims description 31
- 229910007948 ZrB2 Inorganic materials 0.000 title abstract description 8
- VWZIXVXBCBBRGP-UHFFFAOYSA-N boron;zirconium Chemical compound B#[Zr]#B VWZIXVXBCBBRGP-UHFFFAOYSA-N 0.000 title abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- 239000010949 copper Substances 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000002313 adhesive film Substances 0.000 claims abstract description 5
- 239000002994 raw material Substances 0.000 claims abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract description 2
- 229910008117 Zr(BH4)4 Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 47
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 6
- 229910001431 copper ion Inorganic materials 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- RCKBMGHMPOIFND-UHFFFAOYSA-N sulfanylidene(sulfanylidenegallanylsulfanyl)gallane Chemical compound S=[Ga]S[Ga]=S RCKBMGHMPOIFND-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 230000003405 preventing effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 분야에 관한 것으로, 특히 금속배선의 확산방지막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for forming a diffusion barrier of metal wiring.
알루미늄을 이용한 반도체 소자의 금속배선 형성 과정에서, 접착특성을 양호하게 하기 위하여 웨팅(wetting)막으로 타이타늄(Ti)막을 형성하고, Ti막 상에 알루미늄(Al)막을 바로 증착할 경우 Ti와 Al이 서로 반응하여 TiAl3와 같은 부산물을 생성시켜 배선 저항이 증가하는 것을 방지하기 위하여 Ti막 상에 확산방지막으로서 질화타이타늄(TiN)막을 형성한 다음 Al막을 형성한다.In the process of forming a metal wiring of a semiconductor device using aluminum, a titanium (Ti) film is formed as a wetting film in order to improve the adhesion characteristics, and when the aluminum (Al) film is directly deposited on the Ti film, Ti and Al In order to prevent byproducts such as TiAl 3 from reacting with each other to increase wiring resistance, a titanium nitride (TiN) film is formed on the Ti film as a diffusion barrier and then an Al film is formed.
TiN막은 스퍼터링(sputtering)법으로 증착하기 때문에 단차 피복성(step coverage) 특성이 양호하지 못하며, 알루미늄 플로우 특성을 개선하기 위한 고온 증착 공정시 TiAlN 또는 AlN을 형성하여 배선의 저항성분을 증가시키기 때문에 소자의 집적도가 높아질수록 점차 적용이 제한되고 있는 추세이다.Since TiN film is deposited by sputtering method, step coverage property is not good. As the degree of integration increases, application tends to be increasingly limited.
구리를 이용하여 금속배선을 형성하는 경우는 물리적 기상증착법(physical vapor deposition), 화학적 기상증착법(chemical vapor deposition) 또는 전기도금 방법을 이용하여 구리를 증착한다. 구리이온(Cu2+, Cu+)은 상온에서 확산 속도가 매우 빨라서 확산방지막 없이 구리배선을 형성하면 구리이온의 확산에 의해 금속배선간 절연막의 절연특성이 저하되고, 구리이온이 활성(active) 영역으로 확산하여 트랜지스터 특성 등을 열화시키는 문제점이 있다. 따라서, 탄탈륨(Ta), 탄탈륨나이트라이드(TaN) 또는 TiN막을 스퍼터링법으로 형성하여 구리이온의 확산방지막으로 이용하고 있다.In the case of forming metal wiring using copper, copper is deposited by physical vapor deposition, chemical vapor deposition, or electroplating. Since copper ions (Cu 2+ , Cu + ) have a very fast diffusion rate at room temperature, if copper wiring is formed without a diffusion barrier, the insulation properties of the insulating film between metal wirings are degraded by diffusion of copper ions, and copper ions are active. There is a problem of deterioration of transistor characteristics and the like by diffusion to the region. Therefore, a tantalum (Ta), tantalum nitride (TaN), or TiN film is formed by sputtering and used as a diffusion barrier for copper ions.
그러나, 이 경우도 구리이온의 확산방지막을 스퍼터링법으로 형성하기 때문에 단차피복성이 양호하지 못하며 증착된 박막이 주상구조(columnar structure)를 가져 확산방지막으로서의 특성이 우수하지 못하다.However, also in this case, since the diffusion prevention film of copper ions is formed by the sputtering method, the step coverage is not good and the deposited thin film has a columnar structure, and thus the characteristics of the diffusion prevention film are not excellent.
한편, 절연을 위한 저유전율막은 다양한 종류가 있는데 일부의 폴리머(polymer)막들은 300 ℃ 정도부터 폴리머 구조가 변하여 저유전율 특성을 잃기 때문에 후속 공정 온도에 제한이 있다. 따라서, 300 ℃ 내지 400 ℃ 정도의 높은 온도에서 단차피복성을 향상시키기 위하여 화학적 기상증착법으로 확산방지막을 형성할 경우는 절연막으로 사용되는 저유전율막의 절연 특성을 저하시키는 문제점이 있다.On the other hand, there are a variety of low dielectric constant film for insulation, some of the polymer (polymer) film is limited to the subsequent process temperature because the polymer structure is changed from about 300 ℃ to lose the low dielectric constant characteristics. Therefore, when the diffusion barrier film is formed by chemical vapor deposition in order to improve the step coverage at a high temperature of about 300 ° C. to 400 ° C., there is a problem of lowering the insulating properties of the low dielectric constant film used as the insulating film.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 화학기상증착법으로 증착할 수 있어 작은 배선에서도 매립 특성 및 단차피복성이 우수하고, 저온에서 증착이 가능하여 저유전율 절연막의 열이력을 최소화시킬 수 있고, 저항 등 전기적 특성의 저하가 없고 고온 특성이 우수한 지르코늄다이보라이드를 확산방지막으로서 이용하는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention can be deposited by chemical vapor deposition, and thus excellent in buried characteristics and step coverage even in small wirings, and can be deposited at low temperatures, thereby minimizing the thermal history of the low dielectric constant insulating film. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device using zirconium diboride which is excellent in high temperature characteristics without deterioration of electrical characteristics such as resistance and as a diffusion barrier.
도1a 및 도1b는 본 발명의 일실시예에 따른 반도체 소자의 금속배선 형성 공정 단면도,1A and 1B are cross-sectional views of a metal wiring forming process of a semiconductor device according to an embodiment of the present invention;
도2a 및 도2b는 본 발명의 다른 실시예에 따른 반도체 소자의 금속배선 형성 공정 단면도.2A and 2B are cross-sectional views of a metal wiring forming process of a semiconductor device in accordance with another embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
13, 25: 접착막 14, 26: ZrB2확산방지막13, 25: adhesive film 14, 26: ZrB 2 diffusion barrier
15, 27: 금속막15, 27: metal film
상기와 같은 목적을 달성하기 위한 본 발명은 소정의 하부층 형성이 완료된 반도체 기판 상부에 ZrB2확산방지막을 형성하는 단계; 및 상기 ZrB2확산방지막 상에 금속막을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성 방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming a ZrB 2 diffusion barrier on a semiconductor substrate on which a predetermined lower layer is formed; And forming a metal film on the ZrB 2 diffusion barrier layer.
본 발명은 반도체 소자의 금속배선 형성시 장벽막으로 지르코늄다이보라이드(zirconiumdiboride)(ZrB2)막을 증착하는데 특징이 있다. 이에 따라, 금속배선을 위한 알루미늄 증착시 불필요하게 생성되는 TiAl3, TiAlN, AlN 등의 발생을 억제할 수 있으며, 구리 배선의 경우는 구리이온의 확산방지 특성을 향상시킬 수 있다.The present invention is characterized in depositing a zirconium diboride (ZrB 2 ) film as a barrier film in forming metal wirings of a semiconductor device. Accordingly, generation of TiAl 3 , TiAlN, AlN, and the like, which are unnecessarily generated during deposition of aluminum for metal wiring, can be suppressed, and in the case of copper wiring, the diffusion preventing property of copper ions can be improved.
ZrB2막의 비저항은 80 μΩ-㎝로서 종래 확산방지막으로 사용되는 TiN과 유사하여 금속배선 저항면에서도 양호하며, 화학기상증착법으로 증착 가능하기 때문에 배선 크기가 작은 콘택에 매립 특성이 양호하다. 또한, 증착시 증착온도가 150 ℃ 내지 200 ℃이므로 절연막으로 사용되는 저유전율막의 열화 등을 최소화할 수 있다. 그리고, ZrB2막은 고온 재료이므로 열안정성이 우수하여 다른 재료들보다 후속 공정의 온도 제한이 적은 장점이 있다.The specific resistance of the ZrB 2 film is 80 μΩ-cm, which is similar to TiN, which is used as a conventional diffusion barrier film, and is also good in terms of metal wiring resistance, and can be deposited by chemical vapor deposition. In addition, since the deposition temperature is 150 ℃ to 200 ℃ during the deposition can minimize the degradation of the low dielectric constant film used as an insulating film. In addition, since the ZrB 2 film is a high temperature material, the thermal stability is excellent, and thus, the temperature limit of the subsequent process is lower than that of other materials.
이하, 도1a 및 도1b를 참조하여 본 발명의 일실시예에 따른 반도체 소자의 금속배선 형성 방법을 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1A and 1B.
먼저, 도1a에 도시한 바와 같이 반도체 기판(11) 상에 형성된 층간절연막(12)을 선택적으로 식각하여 반도체 기판(11)을 노출시키는 콘택홀을 형성하고, 전체 구조 상에 접착 특성을 우수하게 하기 위하여 Ti, Zr 등의 접착막(13)을 형성한 다음, 접착막(13) 상에 확산방지막으로서 ZrB2확산방지막(14)을 형성하고, ZrB2확산방지막(14) 상에 알루미늄막(15)을 형성한다.First, as shown in FIG. 1A, the interlayer insulating film 12 formed on the semiconductor substrate 11 is selectively etched to form a contact hole for exposing the semiconductor substrate 11, and the adhesive property is excellent on the entire structure. In order to form an adhesive film 13 such as Ti and Zr, a ZrB 2 diffusion barrier 14 is formed on the adhesive layer 13 as a diffusion barrier, and an aluminum film (ZrB 2 diffusion barrier 14 is formed on the ZrB 2 diffusion barrier 14. 15).
다음으로, 도1b에 도시한 바와 같이 사진식각 공정 등으로 알루미늄막(15) 및 ZrB2확산방지막(14)을 패터닝하여 금속배선을 형성한다.Next, as shown in FIG. 1B, the aluminum film 15 and the ZrB 2 diffusion barrier film 14 are patterned by a photolithography process to form metal wiring.
이후, 층간절연막 형성, 비아콘택(via contact) 공정 등을 실시한다.Thereafter, an interlayer insulating film is formed and a via contact process is performed.
다마신(damascene) 공정을 이용한 금속배선 형성 공정에서도 ZrB2막을 확산방지막으로서 이용할 수 있다.The ZrB 2 film can also be used as a diffusion barrier in the metallization formation process using a damascene process.
이하, 도2a 및 도2b를 참조하여 본 발명의 다른 실시예에 따른 반도체 소자 의 금속배선 형성 방법을 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2A and 2B.
먼저, 도2a에 도시한 바와 같이 반도체 기판(21) 상의 제1 층간절연막(22) 상에 실리콘산화막 또는 실리콘질화막으로 이루어지는 식각정지막(23) 및 제2 층간절연막(24)을 형성하고, 제2 층간절연막(24), 식각정지막(23) 및 제1 층간절연막(22)을 선택적으로 식각하여 반도체 기판(21)을 노출시키는 콘택홀을 형성한 다음, 전체 구조 상에 접착막(25), ZrB2확산방지막(26), 금속막(27)을 차례로 형성하여 콘택홀 내부를 채운다. 상기 금속막(27)의 예로서 알루미늄막 또는 구리막을 형성한다.First, as shown in FIG. 2A, an etch stop film 23 and a second interlayer insulating film 24 made of a silicon oxide film or a silicon nitride film are formed on the first interlayer insulating film 22 on the semiconductor substrate 21. The second interlayer insulating film 24, the etch stop film 23, and the first interlayer insulating film 22 are selectively etched to form contact holes exposing the semiconductor substrate 21, and then the adhesive film 25 is formed on the entire structure. , ZrB 2 diffusion barrier layer 26 and metal layer 27 are formed in order to fill the inside of the contact hole. As an example of the metal film 27, an aluminum film or a copper film is formed.
다음으로, 도2b에 도시한 바와 같이 ZrB2확산방지막(26)이 노출될 때까지 상기 금속막(27)을 화학기계적 연마(chemical mechanical polishing)하여 금속배선을 형성한다.Next, as shown in FIG. 2B, the metal film 27 is chemical mechanical polished until the ZrB 2 diffusion barrier 26 is exposed to form metal wiring.
전술한 본 발명의 일실시예 및 다른 실시예에서 ZrB2확산방지막은 플라즈마 화학기상증착장치 또는 고밀도 플라즈마 화학기상증착 장치에서 증착하며 플라즈마에 의한 소자의 열화(plasma damage)를 최소화하기 위하여 리모트(remote) 방식을 이용한다. 플라즈마 분위기 가스로는 아르곤(Ar) 또는 헬륨(He)을 사용하며, 플라즈마 전력으로는 고주파(high frequency) 또는 저주파(low frequency)를 이용한다.In one embodiment and the other embodiments of the present invention described above, the ZrB 2 diffusion barrier layer is deposited in a plasma chemical vapor deposition apparatus or a high density plasma chemical vapor deposition apparatus, and the remote (remote) is minimized to minimize plasma damage of the device by plasma. ) Method. Argon (Ar) or helium (He) is used as the plasma atmosphere gas, and high frequency or low frequency is used as the plasma power.
ZrB2확산방지막 형성을 위한 원물질로는 Zr(BH4)4와 H2가스를 사용한다. H2는 가스 상태로 반응하여 없어지며 최종적으로 ZrB2막이 형성된다. 형성시 B/Zr의 비율은 2 이하가 되어야 한다. B/Zr의 비율이 2 보다 클 경우 B가 산소와 반응하여 B2O3등을 생성시켜 배선저항을 높이는 문제점이 있기 때문에 이 같은 부산물이 생기지 않을 정도로 가스 비율을 조절해야 한다.Zr (BH 4 ) 4 and H 2 gas are used as raw materials for forming the ZrB 2 diffusion barrier. H 2 reacts and disappears in a gaseous state, and finally a ZrB 2 film is formed. In forming, the ratio of B / Zr should be 2 or less. If the ratio of B / Zr is greater than 2 , there is a problem in that B reacts with oxygen to generate B 2 O 3 to increase wiring resistance, so that the gas ratio must be adjusted so that such by-products do not occur.
또한, ZrB2확산방지막은 100 ℃ 내지 300 ℃ 온도, 수 mTorr 내지 10 Torr 압력(즉, 10 Torr를 넘지 않는 압력), 10E5/㎠ 내지 10E15/㎠ 플라즈마 밀도 조건에서 50 Å 내지 1000 Å 두께로 증착한다.In addition, the ZrB 2 diffusion barrier film is deposited at a thickness of 50 kPa to 1000 kPa at a temperature of 100 ° C. to 300 ° C., a few mTorr to 10 Torr pressure (ie, a pressure not exceeding 10 Torr), and a plasma density of 10E5 / cm 2 to 10E15 / cm 2. do.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 지르코늄다이보라이드(ZrB2)막을 알루미늄 또는 구리 금속배선의 확산방지막으로 형성함으로써 고온특성, 단차피복성 및 열적 안정성 확보를 통한 소자의 신뢰성 향상을 이룰 수 있다.According to the present invention, the zirconium diboride (ZrB 2 ) film is formed as a diffusion barrier of aluminum or copper metal wiring, thereby improving reliability of the device through securing high temperature characteristics, step coverage, and thermal stability.
Claims (8)
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Cited By (3)
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| KR100687879B1 (en) * | 2005-06-30 | 2007-02-27 | 주식회사 하이닉스반도체 | Method for fabricating metal interconnect in semiconductor device |
| US7276725B2 (en) | 2004-12-02 | 2007-10-02 | Hynix Semiconductor Inc. | Bit line barrier metal layer for semiconductor device and process for preparing the same |
| KR100846384B1 (en) * | 2002-06-29 | 2008-07-15 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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| JPH02246159A (en) * | 1989-03-18 | 1990-10-01 | Oki Electric Ind Co Ltd | Wiring structure of semiconductor device and formation thereof |
| JPH05343354A (en) * | 1992-06-09 | 1993-12-24 | Sony Corp | Close contact layer of semiconductor device and forming method for metal plug |
| KR0136644B1 (en) * | 1994-09-07 | 1998-04-25 | 공희택 | Prewetting method and apparatus of filter having teflon membrane placed on high purity chemical line in semiconductor manufacturing process |
| KR0175030B1 (en) * | 1995-12-07 | 1999-04-01 | 김광호 | High heat-resistant metal wiring structure of semiconductor device and method of forming the same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100846384B1 (en) * | 2002-06-29 | 2008-07-15 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| US7276725B2 (en) | 2004-12-02 | 2007-10-02 | Hynix Semiconductor Inc. | Bit line barrier metal layer for semiconductor device and process for preparing the same |
| US7435670B2 (en) | 2004-12-02 | 2008-10-14 | Hynix Semiconductor Inc. | Bit line barrier metal layer for semiconductor device and process for preparing the same |
| KR100687879B1 (en) * | 2005-06-30 | 2007-02-27 | 주식회사 하이닉스반도체 | Method for fabricating metal interconnect in semiconductor device |
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