KR100376259B1 - Method of forming a copper wiring in a semiconductor device - Google Patents
Method of forming a copper wiring in a semiconductor device Download PDFInfo
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- KR100376259B1 KR100376259B1 KR10-2000-0083193A KR20000083193A KR100376259B1 KR 100376259 B1 KR100376259 B1 KR 100376259B1 KR 20000083193 A KR20000083193 A KR 20000083193A KR 100376259 B1 KR100376259 B1 KR 100376259B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 다마신 패턴을 포함한 전체 구조 상부에 확산 방지 도전막 대신에 SiN막 또는 SiC막등의 확산 방지 절연막을 형성하고 전면 식각 공정을 실시하여 다마신 패턴 내부 측벽에만 잔류시킨 후 구리 배선을 형성함으로써 트렌치의 유효 저항을 이상적으로 유지할 수 있고 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법이 제시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device. Instead of forming a diffusion preventing conductive film on the entire structure including a damascene pattern, a diffusion preventing insulating film such as a SiN film or a SiC film is formed and a full etching process is performed to form a damascene pattern. By forming a copper wiring after remaining only on the inner sidewall, a method of forming a copper wiring of a semiconductor device capable of ideally maintaining the effective resistance of a trench and improving the reliability of the wiring is proposed.
Description
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히 다마신 패턴을 포함한 전체 구조 상부에 확산 방지 도전막 대신에 SiN막 또는 SiC막등의 확산 방지 절연막을 형성한 후 구리 배선을 형성함으로써 트렌치의 유효 저항을 이상적으로 유지할 수 있고 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device. In particular, a trench wiring is formed by forming a copper wiring after forming a diffusion preventing insulating film such as a SiN film or a SiC film on the entire structure including a damascene pattern. The present invention relates to a method for forming a copper wiring of a semiconductor device which can ideally maintain an effective resistance and can improve the reliability of the wiring.
반도체 소자의 구리 배선은 일반적으로 소정의 구조가 형성된 반도체 기판 상부에 형성된 절연막에 다마신 패턴을 형성하고, 다마신 패턴상에 확산 방지 도전막을 형성한 후 구리 배선을 형성하는 공정에 의해 형성된다. 이러한 다마신 패턴상에 형성되는 확산 방지 도전막은 소자의 고집적화에 따라 듀얼 다마신 패턴의 콘택과 트렌치의 단차비가 증가하게 되어 층덮힘 특성이 매우 중요하게 작용하게 된다.Generally, the copper wiring of a semiconductor element is formed by the process of forming a damascene pattern in the insulating film formed on the semiconductor substrate in which the predetermined structure was formed, forming a diffusion prevention conductive film on a damascene pattern, and forming a copper wiring. The diffusion barrier conductive layer formed on the damascene pattern increases the step ratio between the contact and the trench of the dual damascene pattern according to the high integration of the device, so that the layer covering characteristic is very important.
상기의 확산 방지 도전막으로는 TiN, Ta, TaN, WN등이 사용되는데, 이들은 배선으로 사용되는 구리보다 큰 저항을 가지고 있다. 그리고, 확산 방지 도전막이 차지하는 비율이 증가함에 따라 트렌치에서의 유효 저항값이 증가하게 되어 알루미늄 합금 대신 저항이 낮은 구리를 사용하는 효과가 감소하게 된다. 또한, 구리층을 형성한 후 화학적 기계적 연마 공정을 실시할 때 확산 방지 도전막으로 인해 여러 단계의 연마 공정이 필요하여 공정이 복잡하고 높은 생산 단가를 요구한다. 한편, 확산 방지막을 형성함으로써 콘택과 트렌치 상부 입구가 협소해져 구리 시드층을 증착할 때 콘택 내부에 균일한 구리막을 증착하기 어렵기 때문에 전기화학적으로구리를 증착할 때 콘택 내부에 보이드가 발생되어 배선 신뢰성에 악영향을 미치는 문제가 발생된다.As the diffusion preventing conductive film, TiN, Ta, TaN, WN, and the like are used, which have a larger resistance than copper used for wiring. As the proportion of the diffusion preventing conductive film increases, the effective resistance value in the trench increases, thereby reducing the effect of using copper having low resistance instead of aluminum alloy. In addition, when the chemical mechanical polishing process is performed after the copper layer is formed, the diffusion preventing conductive film requires a polishing process of several steps, which requires a complicated process and a high production cost. On the other hand, by forming a diffusion barrier layer, the contact and the trench upper inlet are narrowed, so that it is difficult to deposit a uniform copper film inside the contact when depositing a copper seed layer. Problems that adversely affect reliability arise.
본 발명의 목적은 확산 방지 도전막을 형성함으로써 발생되는 상기의 문제를 해결할 수 있는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.An object of the present invention is to provide a method for forming a copper wiring of a semiconductor device that can solve the above problems caused by forming a diffusion preventing conductive film.
본 발명의 다른 목적은 일반적으로 사용되는 금속 계열의 확산 방지 도전막을 사용하지 않고도 구리의 확산을 방지하면서도 트렌치에서의 유효 저항을 이상적으로 유지할 수 있는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming a copper wiring of a semiconductor device which can ideally maintain effective resistance in a trench while preventing diffusion of copper without using a metal-based diffusion prevention conductive film that is generally used.
본 발명에서는 다마신 패턴을 형성한 후 원자층 증착 장비(atomic layer deposition)을 이용하여 SiN막 또는 SiC막등의 확산 방지 절연막을 다마신 패턴을 포함한 전체 구조 상부에 형성한 후 진공 파괴없이 구리 배선을 형성한다.In the present invention, after forming a damascene pattern, a diffusion barrier insulating film such as a SiN film or a SiC film is formed on the entire structure including the damascene pattern using atomic layer deposition, and then copper wiring is removed without vacuum destruction. Form.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown in order to explain a method for forming a copper wiring of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 하부 구리 배선11 semiconductor substrate 12 lower copper wiring
13 : 구리 확산 장벽층 14 : 제 1 절연막13 copper diffusion barrier layer 14 first insulating film
15 : 식각 장벽층 16 : 제 2 절연막15 etching barrier layer 16 second insulating film
17 : 하드 마스크층 18 : 구리 산화막17: hard mask layer 18: copper oxide film
19 : 확산 방지 절연막 20 : 상부 구리 배선19: diffusion prevention insulating film 20: upper copper wiring
본 발명에 따른 반도체 소자의 구리 배선 형성 방법은 소정의 구조가 형성된 반도체 기판 상부에 절연막을 형성하는 단계와, 상기 절연막에 다마신 공정을 실시하여 상기 반도체 기판의 소정 영역을 노출시키는 다마신 패턴을 형성하는 단계와, 상기 다마신 패턴을 포함한 전체 구조 상부에 확산 방지 절연막을 형성하는 단계와, 전면 식각 공정을 실시하여 상기 다마신 패턴의 측벽에 상기 확산 방지 절연막을 잔류시키고, 상기 다마신 패턴 기저부의 확산 방지 절연막을 제거하는 단계와, 상기 다마신 패턴이 매립되도록 전체 구조 상부에 구리층을 형성한 후 연마 공정을 실시하여 구리 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The method for forming a copper wiring of a semiconductor device according to the present invention includes forming an insulating film on a semiconductor substrate having a predetermined structure, and performing a damascene process on the insulating film to expose a damascene pattern for exposing a predetermined region of the semiconductor substrate. Forming a diffusion prevention insulating film on the entire structure including the damascene pattern, and performing an entire surface etching process to leave the diffusion prevention insulating film on sidewalls of the damascene pattern and to form the damascene pattern base. Removing a diffusion preventing insulating layer, and forming a copper layer by forming a copper layer on the entire structure so that the damascene pattern is embedded, and then performing a polishing process to form a copper wiring.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method for forming a copper wiring of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 하부 구리 배선(12)을 형성한다. 하부 구리 배선(12)을 포함한 전체 구조 상부에 다층 구조의 절연막을 형성한다. 다층 구조의 절연막은 예를 들어 구리 확산 장벽층(13), 제 1 절연막(14), 식각 장벽층(15), 제 2 절연막(16) 및 하드 마스크층(17)을 순차적으로 적층하여 형성한다. 구리 확산 장벽층(13)은 하부 구리 배선(12)의 구리 원자가 상부의 제 1 절연막(14)으로 확산되는 것을 방지하는 역할을 한다. 상기 적층 구조의 절연막에 듀얼 다마신 공정을 실시하여 콘택과 트렌치로 이루어진 듀얼 다마신 패턴을 형성한다. 이러한 듀얼 다마신 패턴을 형성할 때 하부 구리 배선(12)이 노출되고, 이에 의해 구리 산화막(CuOx)(18)이 형성된다.Referring to FIG. 1A, a lower copper wiring 12 is formed on a semiconductor substrate 11 on which a predetermined structure is formed. An insulating film of a multilayer structure is formed over the entire structure including the lower copper wiring 12. The multilayer insulating film is formed by sequentially stacking, for example, a copper diffusion barrier layer 13, a first insulating film 14, an etch barrier layer 15, a second insulating film 16, and a hard mask layer 17. . The copper diffusion barrier layer 13 serves to prevent the copper atoms of the lower copper wiring 12 from diffusing into the upper first insulating film 14. A dual damascene process is performed on the insulating layer having the stacked structure to form a dual damascene pattern made of a contact and a trench. When forming such a dual damascene pattern, the lower copper wiring 12 is exposed, thereby forming a copper oxide film (CuO x ) 18.
도 1(b)를 참조하면, 듀얼 다마신 패턴이 형성된 전체 구조 상부에 SiN, SiC 또는 SiON등의 확산 방지 절연막(19)을 형성한다. 확산 방지 절연막(19)은 층덮힘 특성이 우수한 원자층 증착(atomic layer deposition) 장비를 이용하여 10∼50Å정도의 두께로 형성한다.Referring to FIG. 1B, a diffusion barrier insulating film 19, such as SiN, SiC, or SiON, is formed on the entire structure in which the dual damascene pattern is formed. The diffusion barrier insulating film 19 is formed to a thickness of about 10 to 50 kV using atomic layer deposition equipment having excellent layer covering characteristics.
도 1(c)를 참조하면, 불활성 가스와 환원성 가스의 혼합 가스를 이용한 식각 공정으로 확산 방지 절연막(19)을 식각하여 하드 마스크층(17)을 노출시키고, 듀얼 다마신 패턴의 콘택 기저부에 형성된 구리 산화막(18)도 제거시킨다. 이에 의해 듀얼 다마신 패턴 측벽에 확산 방지 절연막(19)이 스페이서로 잔류하게 되어 층덮힘 감소가 특성이 0∼20% 내외로 유지된다. 식각 공정은 구리 증착 장비에서 2단계로 실시되는데, 아르곤 또는 아르곤과 질소의 혼합 가스중 어느 하나를 이용한 1단계 식각 공정으로 확산 방지 절연막(19)을 제거하고, 수소, 수소와 헬륨의 혼합 가스, 수소와 아르곤의 혼합 가스, 그리고 수소와 질소의 혼합 가스중 어느 하나를 이용한 2단계 식각 공정으로 구리 산화막(18)을 제거한다.Referring to FIG. 1C, the diffusion barrier insulating layer 19 is etched to expose the hard mask layer 17 by an etching process using a mixed gas of an inert gas and a reducing gas to form a contact base portion of a dual damascene pattern. The copper oxide film 18 is also removed. As a result, the diffusion barrier insulating film 19 remains on the dual damascene pattern sidewalls as spacers, so that the layer covering is maintained at about 0 to 20%. The etching process is performed in two steps in the copper deposition equipment, and the diffusion barrier insulating film 19 is removed by a one-step etching process using one of argon or a mixed gas of argon and nitrogen, and a mixed gas of hydrogen, hydrogen, and helium, The copper oxide film 18 is removed by a two-step etching process using either a mixed gas of hydrogen and argon and a mixed gas of hydrogen and nitrogen.
도 1(d)를 참조하면, 듀얼 다마신 패턴이 매립되도록 전체 구조 상부에 구리 시드층(도시안됨)을 형성한 후 전기화학적 구리 증착 장비를 이용하여 구리층을 매립한다다. 구리 시드층은 확산 방지 절연막(19)의 식각 공정에 사용된 증착 장비를 이용하여 500∼1500Å의 두께로 증착하는데, 이로 인해 확산 방지 절연막(19)의 식각 공정과 구리층의 증착 공정을 진공 파괴없이 단일 장비에서 실시할 수 있다. 또한, 구리층은 PVD 방법을 이용하여 저온 및 고온의 이단계로 증착할 수도 있다. 그리고, 열처리 공정과 화학적 기계적 연마 공정을 실시하여 상부 구리 배선(20)을 형성한다.Referring to FIG. 1 (d), a copper seed layer (not shown) is formed on an entire structure to fill a dual damascene pattern, and then a copper layer is embedded using an electrochemical copper deposition apparatus. The copper seed layer is deposited to a thickness of 500 to 1500 하여 using the deposition equipment used for the etching process of the diffusion barrier insulating film 19, thereby vacuum breaking the etching process of the diffusion barrier insulating film 19 and the deposition process of the copper layer. It can be performed on a single device without. In addition, the copper layer may be deposited in two stages of low temperature and high temperature using PVD method. Then, the heat treatment process and the chemical mechanical polishing process are performed to form the upper copper wiring 20.
상술한 바와 같이 본 발명에 의하면 저항이 높은 확산 방지막 대신 층덮힘 특성이 우수한 원자층 증착 장비를 이용하여 SiN 또는 SiC등의 확산 방지 절연막을 형성한 후 구리 배선을 형성함으로써 구리 배선의 실제 저항을 낮게 유지할 수 있고, 확산 방지 절연막이 듀얼 다마신 패턴의 측벽을 보호하므로 식각에 취약한 저유전 절연막의 특성을 유지할 수 있어 배선간 누설 전류를 억제할 수 있다. 또한, 확산 방지 절연막 상부에서의 구리 결정성이 기존의 확산 방지막 상부에서 보다 (111) 우선 방위를 강하게 얻을 수 있어 배선 신뢰성을 개선할 수 있다. 그리고, 확산 방지막을 형성하지 않기 때문에 구리층을 화학적 기계적 연마 공정으로 연마할 때 1개의 슬러리를 가지고 빠른 시간내에 저비용으로 연마 공정을 실시할 수 있다.As described above, according to the present invention, the diffusion resistance insulating film such as SiN or SiC is formed by using the atomic layer deposition equipment having excellent layer covering properties instead of the diffusion resistance film having high resistance, and then the copper wiring is formed to lower the actual resistance of the copper wiring. Since the diffusion preventing insulating layer protects the sidewall of the dual damascene pattern, the characteristics of the low dielectric insulating film vulnerable to etching can be maintained, and the leakage current between wirings can be suppressed. In addition, the copper crystallinity on the top of the diffusion preventing insulating film can obtain a stronger (111) preferred orientation than on the existing diffusion preventing film, so that the wiring reliability can be improved. And since a diffusion prevention film is not formed, when a copper layer is polished by a chemical mechanical polishing process, it can carry out a polishing process with one slurry at low cost in a short time.
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| JPH0637038A (en) * | 1992-07-15 | 1994-02-10 | Nippon Telegr & Teleph Corp <Ntt> | Manufacturing for semiconductor device |
| US5821168A (en) * | 1997-07-16 | 1998-10-13 | Motorola, Inc. | Process for forming a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0637038A (en) * | 1992-07-15 | 1994-02-10 | Nippon Telegr & Teleph Corp <Ntt> | Manufacturing for semiconductor device |
| US5821168A (en) * | 1997-07-16 | 1998-10-13 | Motorola, Inc. | Process for forming a semiconductor device |
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