KR20030002137A - A method for forming damascene metal wire using copper - Google Patents
A method for forming damascene metal wire using copper Download PDFInfo
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- KR20030002137A KR20030002137A KR1020010038878A KR20010038878A KR20030002137A KR 20030002137 A KR20030002137 A KR 20030002137A KR 1020010038878 A KR1020010038878 A KR 1020010038878A KR 20010038878 A KR20010038878 A KR 20010038878A KR 20030002137 A KR20030002137 A KR 20030002137A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속배선 공정에 관한 것이며, 더 자세히는 구리를 사용한 대머신(damascene) 금속배선 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a metallization process in a semiconductor device manufacturing process, and more particularly, to a damascene metallization process using copper.
금속 콘택 형성 공정은 다층화된 반도체 소자를 제조하기 위해서는 필수적으로 도입되는 기술로, 상/하부 전도층 간의 수직배선의 근간이 된다. 한편, 반도체 소자의 고집적화에 따른 디자인 룰(design rule)의 축소에 따라 콘택홀의 에스펙트 비(aspect ratio)는 점차 증가하고 있으며, 이에 따라 금속 콘택 형성 공정의 난이도와 중요성이 증대되고 있다.The metal contact forming process is an essential technique for manufacturing a multilayered semiconductor device, and is a basis of vertical wiring between upper and lower conductive layers. On the other hand, the aspect ratio of the contact hole is gradually increasing as the design rule is reduced due to the higher integration of the semiconductor device, thereby increasing the difficulty and importance of the metal contact forming process.
알루미늄(Al)은 콘택 매립 특성이 우수하지 못함에도 불구하고 비저항이 2.7μΩcm 정도로 낮고 공정이 비교적 용이하기 때문에 금속 배선 물질로서 가장 널리 사용되어 왔다. 그러나, 디자인 룰이 0.25㎛ 급으로 축소되면서 스텝 커버리지(step coverage)가 열악한 물리기상증착(Physical Vapor Deposition, PVD) 방식의 알루미늄 증착을 통해 충분한 콘택 매립을 이룰 수 없고, 일렉트로마이그레이션(electromigration) 특성 등에 의해 열화되는 문제점이 있었다.Aluminum (Al) has been most widely used as a metal wiring material because of its low resistivity as low as 2.7 μΩcm and relatively easy process, despite its poor contact embedding properties. However, due to the reduction of design rules to 0.25㎛, physical vapor deposition (PVD) -based aluminum deposition with poor step coverage cannot achieve sufficient contact filling, and electromigration characteristics. There was a problem deteriorated by.
이러한 알루미늄 금속배선의 한계를 고려하여 알루미늄에 비해 콘택 매립 특성이 우수한 구리를 금속배선 재료로 사용하는 기술에 대한 관심이 높아가고 있다. 통상적으로 구리를 사용하여 금속배선을 형성할 때 화학기상증착법(CVD)을 사용하고 있다.Considering the limitations of the aluminum metal wiring, there is a growing interest in the technology of using copper as a metal wiring material, which has better contact embedding properties than aluminum. In general, chemical vapor deposition (CVD) is used to form metal wiring using copper.
그런데, 구리는 식각 특성이 매우 불량한 단점을 가지고 있어 일반적인 금속배선 형성 공정에 적용하기 어렵다. 즉, 고단차비를 가지는 금속배선의 형성시 금속배선의 CD 균일도(critical dimension uniformity), 라인 식각 프로파일(lineetch profile) 및 포토레지스트의 식각 선택비 등에서 만족할만한 결과를 얻기 힘들다. 이러한 구리의 단점을 극복하기 위하여 대머신 금속배선 공정이 사용되고 있다.By the way, copper has a disadvantage that the etching characteristics are very poor, it is difficult to apply to the general metal wiring forming process. That is, it is difficult to obtain satisfactory results in the CD uniformity, the line etch profile and the etching selectivity of the photoresist of the metal wiring when the metal wiring having the high step ratio is formed. In order to overcome the drawbacks of copper, a metallization process is used.
통상적인 대머신 금속배선 공정은 층간절연막에 라인용 트렌치 및 콘택홀을 형성하고, 베리어 금속과 구리를 증착한 후 화학적·기계적 평탄화(chemical mechanical planarization, CMP) 기술을 이용하여 층간절연막 상부에 있는 베리어 금속 및 배선 금속을 제거하는 과정을 거치고 있다.Conventional damascene metallization processes form trenches and contact holes for interlayer dielectrics, deposit barrier metals and copper, and then use chemical mechanical planarization (CMP) technology to form barriers on top of the interlayer dielectrics. It is in the process of removing metal and wiring metal.
그러나, 이와 같이 대머신 공정을 적용하는 경우에도 문제점은 있다. 즉, 금속배선간의 피치가 작아짐에 따라 RC-지연이 증가하는 문제점이 발생한다. 이러한 대머신 타입의 금속배선의 RC-지연을 줄이기 위한 하나의 방법으로 저유전율 절연막을 사용하고 있다.However, there is a problem also in applying the damascene process in this way. In other words, the RC-delay increases as the pitch between metal wires becomes smaller. A low dielectric constant insulating film is used as a method to reduce the RC-delay of such large-machined metal wiring.
한편, 구리(Cu)는 층간절연막과 직접 접촉될 경우 구리의 확산에 의해 소자 특성 저하가 발생하기 때문에 층간절연막과 구리 배선 사이에 구리확산방지막(Cu diffusion barrier)을 필수로 사용되고 있으며, 현재 구리확산방지막으로 주로 TaN막을 사용하고 있다.On the other hand, since Cu (Cu) is in direct contact with the interlayer insulating film, the device characteristics are deteriorated due to the diffusion of copper, and a Cu diffusion barrier is essentially used between the interlayer insulating film and the copper wiring. A TaN film is mainly used as a prevention film.
그러나, TaN막을 증착하기 위한 타겟 소오스인 탄탈륨(Ta)은 희귀성이 높은 금속으로 양산성이 떨어지는 단점을 가지고 있을 뿐만 아니라, TaN막의 높은 저항값이 문제점으로 지적되고 있다. 또한, TaN막은 PVD 방식으로 증착하기 때문에 스텝 커버리지가 열악하고, 이에 따라 집적도가 증가할수록 후속 공정인 구리 씨드(seed)층 형성 공정이나 구리 전해도금 공정 진행시 갭-필(gap-fill) 문제점을내포하고 있다.However, tantalum (Ta), which is a target source for depositing a TaN film, has a disadvantage of poor productivity due to a rare metal, and the high resistance of the TaN film has been pointed out as a problem. In addition, since the TaN film is deposited by the PVD method, step coverage is poor. Accordingly, as the degree of integration increases, gap-fill problems are encountered during the subsequent copper seed layer forming process or the copper electroplating process. It is implicated.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 구리확산방지막의 저항 특성, 스텝 커버리지 및 양산성을 확보할 수 있는 구리를 사용한 대머신 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed in order to solve the problems of the prior art as described above, the object of the present invention is to provide a method for forming a metal wire using a copper that can ensure the resistance characteristics, step coverage and mass production of the copper diffusion barrier. have.
도 1 내지 도 6은 본 발명의 일 실시예에 따른 구리를 사용한 듀얼 대머신 금속배선 형성 공정도.1 to 6 is a process diagram of forming a dual damascene metal wiring using copper according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
17 : 질화된 층간절연막17 nitrided interlayer insulating film
18 : TiN막(또는 Ti/TiN막)18: TiN film (or Ti / TiN film)
19 : TiN막19: TiN film
20 : 구리 씨드층20: copper seed layer
21 : 구리막21: copper film
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 소정의 하부층 공정을 마친 기판 상에 형성된 층간절연막을 식각하여 대머신 패턴을 형성하는 제1 단계; 상기 대머신 패턴의 측벽을 이루는 상기 층간절연막 표면을 질화시키는 제2 단계; 적어도 상기 대머신 패턴의 측벽에 질화티타늄막을 포함하는 구리확산방지막을 형성하는 제3 단계; 상기 대머신 패턴 내에 구리막을 매립하는 제4 단계를 포함하는 구리를 사용한 대머신 금속배선 형성방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, a first step of forming a substitute machine pattern by etching the interlayer insulating film formed on the substrate after a predetermined lower layer process; Nitriding the surface of the interlayer dielectric layer forming sidewalls of the damascene pattern; A third step of forming a copper diffusion prevention film including a titanium nitride film on at least sidewalls of the damascene pattern; Provided is a method for forming a metal machine wiring using copper including a fourth step of embedding a copper film in the mother machine pattern.
본 발명은 구리확산방지막으로 비교적 저항값이 낮고 스텝 커버리지가 우수한 TiN막(또는 Ti/TiN막)을 사용한다. TiN막(또는 Ti/TiN막)은 지난 수 십년간 반도체 제조 공정에서 널리 사용되어 온 물질로 낮은 공정 단가와 공정의 안정성 등에 있어 더 이상의 검증이 필요 없다. 그러나, TiN막(또는 Ti/TiN막)은 구리의 확산에 대한 베리어 특성이 떨어지는 바, 본 발명에서는 이러한 베리어 특성을 보완하기 위하여 대머신 패턴을 이루는 층간절연막(주로 실리콘산화막) 표면을 질화하는 공정을 추가하였다.The present invention uses a TiN film (or Ti / TiN film) having a relatively low resistance value and excellent step coverage as the copper diffusion preventing film. TiN films (or Ti / TiN films) have been widely used in the semiconductor manufacturing process for several decades and need no further verification in terms of low process cost and process stability. However, since the TiN film (or Ti / TiN film) has a poor barrier property against copper diffusion, in the present invention, a process of nitriding the surface of an interlayer insulating film (mainly silicon oxide film) forming a damascene pattern to compensate for the barrier property. Was added.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1 내지 도 6은 본 발명의 일 실시예에 따른 구리를 사용한 듀얼 대머신 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1 to 6 illustrate a dual damascene metal wiring forming process using copper according to an embodiment of the present invention, which will be described below with reference to the drawings.
우선, 도 1에 도시된 바와 같이 소정의 하부층 공정을 마친 기판(10) 상에 하부 금속배선(11)을 형성하고, 전체 구조 표면을 따라 제1 실리콘 실리콘질화막(12)을 증착하고, 전체 구조 상부에 제1 저유전율절연막(13) 및 제2 실리콘질화막(14)을 증착하고, 비아홀 형성 영역의 제2 실리콘질화막(14)을 선택 식각한다. 이어서, 전체 구조 상부에 제2 저유전율절연막(15) 및 캡핑산화막(16)을 증착하고, 상부 금속배선 마스크를 사용한 사진 공정 및 식각 공정을 실시하여 라인용 트렌치 및 비아홀을 가진 듀얼 대머신 패턴을 형성한다. 여기서, 제1 및 제2 저유전율절연막(13, 15)은 층간절연막으로 사용된 것이며, 제1 실리콘질화막(12)은 확산방지막으로, 제2 실리콘질화막(14)은 하드 마스크층으로 사용된 것이다. 또한, 캡핑산화막(16)은 이를 실리콘질화막으로 대체할 수 있으며, 제1 및 제2 실리콘질화막(12, 14)과 갭핑산화막(16)은 각각 실리콘카바이드(SiC)막으로 대체할 수 있다.First, as shown in FIG. 1, a lower metal wiring 11 is formed on a substrate 10 having a predetermined lower layer process, a first silicon silicon nitride film 12 is deposited along the entire structure surface, and the entire structure. The first low dielectric constant insulating film 13 and the second silicon nitride film 14 are deposited on the upper portion, and the second silicon nitride film 14 in the via hole formation region is selectively etched. Subsequently, a second low dielectric constant insulating film 15 and a capping oxide film 16 are deposited on the entire structure, and a photolithography process and an etching process using an upper metal wiring mask are performed to form a dual damascene pattern having trenches and via holes for lines. Form. Here, the first and second low dielectric constant insulating films 13 and 15 are used as interlayer insulating films, the first silicon nitride film 12 is used as a diffusion barrier, and the second silicon nitride film 14 is used as a hard mask layer. . In addition, the capping oxide layer 16 may replace it with a silicon nitride layer, and the first and second silicon nitride layers 12 and 14 and the gapping oxide layer 16 may be replaced with a silicon carbide (SiC) layer, respectively.
다음으로, 도 2에 도시된 바와 같이 불활성 가스(예컨대, Ar,He, N2등)와 환원성 가스(예컨대, H2등)를 사용한 식각 공정을 통해 비아홀 저면에 형성된 구리산화물을 제거한다. 이때, 웨이퍼에 인가되는 바이어스를 -100V 이하로 설정하는 것이 바람직하다. 이어서, 듀얼 대머신 패턴의 측벽을 이루는 제1 및 제2 저유전율절연막(13, 15)의 표면을 질화시킨다. 이때, 제1 및 제2 저유전율절연막(13, 15)의 질화를 위해서 여러 가지 방법을 사용할 수 있으나, 질소 플라즈마 처리가 가장 바람직하며, 도면 부호 '17'은 질화된 층간절연막을 나타낸 것이다.Next, as shown in FIG. 2, the copper oxide formed on the bottom of the via hole is removed through an etching process using an inert gas (eg, Ar, He, N 2, etc.) and a reducing gas (eg, H 2, etc.). At this time, it is preferable to set the bias applied to the wafer to -100V or less. Subsequently, the surfaces of the first and second low dielectric constant insulating films 13 and 15 forming the sidewalls of the dual damascene pattern are nitrided. In this case, various methods may be used for nitriding the first and second low dielectric constant insulating layers 13 and 15, but nitrogen plasma treatment is most preferable, and reference numeral 17 denotes a nitrided interlayer insulating layer.
계속하여, 도 3에 도시된 바와 같이 전체 구조 표면을 따라 TiN막(또는 Ti/TiN막)(18)을 증착하고, 산소 분위기(정확하게는 질소 분위기의 대기 상태)에서 열처리를 실시하여 TiN막(18)의 일부를 산화시킨다. 이때, 열처리는 상압 열처리로에서 150∼450℃의 온도 범위로 실시하는 것이 바람직하며, 열처리 온도 및 웨이퍼 장입 속도를 조절하여 TiN막(18)에 원하는 만큼의 산소(O)가 충진되도록 한다.Subsequently, as shown in FIG. 3, a TiN film (or Ti / TiN film) 18 is deposited along the entire structure surface, and heat-treated in an oxygen atmosphere (preferably in an atmosphere of nitrogen atmosphere) to form a TiN film ( Part of 18) is oxidized. At this time, the heat treatment is preferably carried out in a temperature range of 150 ~ 450 ℃ in an atmospheric pressure heat treatment furnace, by adjusting the heat treatment temperature and the wafer loading rate so that the oxygen (O) as much as desired to the TiN film 18 is filled.
이어서, 도 4에 도시된 바와 같이 그 일부가 산화된 TiN막(18) 상에 다시 TiN막(19)을 증착하고, 그 표면에 구리 씨드층(20)을 형성한다. 앞에서 설명한 질화 공정부터 구리 씨드층(20) 형성 공정은 가급적 진공의 파괴 없이 하나의 장비(예컨대, 원자층증착(ALD) 장비, 물리기상증착(PVD) 장비) 내에서 수행하는 것이 바람직하다.Subsequently, as shown in FIG. 4, the TiN film 19 is further deposited on the TiN film 18 having a part thereof oxidized, and a copper seed layer 20 is formed on the surface thereof. From the above-described nitriding process, the copper seed layer 20 forming process is preferably performed in one equipment (for example, atomic layer deposition (ALD) equipment and physical vapor deposition (PVD) equipment) without breaking the vacuum.
다음으로, 도 5에 도시된 바와 같이 전기화학적 증착법으로 비아홀 및 라인용 트렌치에 구리막(21)을 매립하고, CMP 공정을 통해 상부 금속배선을 디파인 한다.Next, as shown in FIG. 5, the copper film 21 is embedded in the via hole and the trench for the line by electrochemical deposition, and the upper metal wiring is defined through the CMP process.
계속하여, 도 6에 도시된 바와 같이 구리막(21) 표면에 형성된 구리 산화물을 식각해 내고, 전체 구조 상부에 확산방지막인 제3 실리콘질화막(22)을 증착한다.Subsequently, as shown in FIG. 6, the copper oxide formed on the surface of the copper film 21 is etched away, and the third silicon nitride film 22, which is a diffusion barrier film, is deposited on the entire structure.
상기와 같은 공정을 실시하는 경우, 질화된 층간절연막과 TiN막(또는 Ti/TiN막)이 구리확산방지 특성을 충분히 확보할 수 있으며, TiN막(또는 Ti/TiN막)을 구리확산방지막으로 사용함으로서 콘택 저항을 낮추고 스텝 커버리지를 개선하고 생산 단가를 낮출 수 있다.In the above process, the nitrided interlayer insulating film and the TiN film (or Ti / TiN film) can sufficiently secure the copper diffusion preventing property, and the TiN film (or Ti / TiN film) is used as the copper diffusion preventing film. This reduces contact resistance, improves step coverage and lowers production costs.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 듀얼 대머신 공정을 일례로 들어 설명하였으나, 본 발명은 싱글 대머신 공정에도 적용할 수 있다.For example, in the above embodiment, the dual damascene process has been described as an example, but the present invention can be applied to a single damascene process.
전술한 본 발명은 구리를 사용한 대머신 공정시 구리확산방지막으로 TiN막을 적용함으로써 후속 구리 증착 공정을 안정화하는 효과가 있으며, 이로 인하여 반도체 소자의 동작 특성을 개선할 수 있다. 한편, 실리콘카바이드 스페이서가 후속 공정시 저유전율절연막으로부터의 탈기(outgassing)를 방지하여 금속배선의 열화를 방지할 수 있는 부수적 효과를 기대할 수 있다.The present invention described above has an effect of stabilizing a subsequent copper deposition process by applying a TiN film as a copper diffusion barrier during the damascene process using copper, thereby improving the operating characteristics of the semiconductor device. On the other hand, the silicon carbide spacer can be expected in the subsequent process to prevent outgassing (low gas) from the low dielectric constant insulating film can be expected a side effect that can prevent the deterioration of the metal wiring.
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| US7638423B2 (en) | 2006-02-03 | 2009-12-29 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming wires of semiconductor device |
| KR20140051090A (en) * | 2012-10-22 | 2014-04-30 | 도쿄엘렉트론가부시키가이샤 | Method of etching copper layer and mask |
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| US7638423B2 (en) | 2006-02-03 | 2009-12-29 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming wires of semiconductor device |
| KR20140051090A (en) * | 2012-10-22 | 2014-04-30 | 도쿄엘렉트론가부시키가이샤 | Method of etching copper layer and mask |
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