KR100744669B1 - A method for forming damascene metal wire using copper - Google Patents
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- KR100744669B1 KR100744669B1 KR1020010037398A KR20010037398A KR100744669B1 KR 100744669 B1 KR100744669 B1 KR 100744669B1 KR 1020010037398 A KR1020010037398 A KR 1020010037398A KR 20010037398 A KR20010037398 A KR 20010037398A KR 100744669 B1 KR100744669 B1 KR 100744669B1
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- 239000010949 copper Substances 0.000 title claims abstract description 59
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 title claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 9
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 9
- 230000002265 prevention Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000003754 machining Methods 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000001465 metallisation Methods 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 transition metal nitride Chemical class 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910004156 TaNx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속 배선 공정에 관한 것이며, 더 자세히는 구리를 사용한 대머신(damascene) 금속배선 형성 공정에 관한 것이다. 본 발명은 구리확산방지막의 비저항 특성을 확보할 수 있는 구리를 사용한 대머신 금속배선 형성방법을 제공하는데 그 목적이 있다. 본 발명은 구리확산방지막으로 Ta막을 사용하되, 고온(250∼500℃)에서 비저항 값이 낮은 α-Ta막으로 증착하여 사용한다. TaNx막의 경우는 화학양론(stoichiometry)에 따라 비저항값이 변화하지만, 순수한 Ta막은 β-Ta의 경우는 180∼200μΩ·㎝, α-Ta의 경우는 20∼30μΩ·㎝와 같이 상(phase)에 따라 비저항값이 다르게 나타난다. 한편, 구리 확산에 대한 Ta막의 베리어 특성을 보다 강화하기 위하여 Ta막 상부 또는 하부에 TaNx막을 더 적용할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a metal wiring process in a semiconductor device manufacturing process, and more particularly, to a damascene metal wiring forming process using copper. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal machine wiring using copper capable of securing the resistivity of a copper diffusion barrier. In the present invention, a Ta film is used as the copper diffusion preventing film, but is deposited by using an α-Ta film having a low specific resistance at high temperature (250 to 500 ° C.). In the case of TaN x film, the specific resistance value changes according to stoichiometry, but pure Ta film is 180 ~ 200μΩ · cm for β-Ta and 20-30μΩ · cm for α-Ta. The specific resistance value is different according to. On the other hand, in order to further strengthen the barrier properties of the Ta film to the copper diffusion may be further applied to the TaN x film on the upper or lower Ta film.
대머신 금속배선, 구리, 구리확산방지막, 탄탈륨막, 비저항Metallization, copper, copper diffusion prevention film, tantalum film, resistivity
Description
도 1 내지 도 4는 본 발명의 일 실시예에 따른 구리를 사용한 싱글 대머신 금속배선 형성 공정도.
1 to 4 is a process diagram of forming a single damascene metal wiring using copper according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 기판10: substrate
11 : 층간절연막11: interlayer insulating film
12 : Ta막12: Ta film
13 : 구리 씨드층13: copper seed layer
14 : 구리막
14: copper film
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속 배선 공정에 관한 것이며, 더 자세히는 구리를 사용한 대머신(damascene) 금속배선 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a metal wiring process in a semiconductor device manufacturing process, and more particularly, to a damascene metal wiring forming process using copper.
금속 콘택 형성 공정은 다층화된 반도체 소자를 제조하기 위해서는 필수적으로 도입되는 기술로, 상/하부 전도층 간의 수직배선의 근간이 된다. 한편, 반도체 소자의 고집적화에 따른 디자인 룰(design rule)의 축소에 따라 콘택홀의 에스펙트 비(aspect ratio)는 점차 증가하고 있으며, 이에 따라 금속 콘택 형성 공정의 난이도와 중요성이 증대되고 있다.The metal contact forming process is an essential technique for manufacturing a multilayered semiconductor device, and is a basis of vertical wiring between upper and lower conductive layers. On the other hand, the aspect ratio of the contact hole is gradually increasing as the design rule is reduced due to the higher integration of the semiconductor device, thereby increasing the difficulty and importance of the metal contact forming process.
알루미늄(Al)은 콘택 매립 특성이 우수하지 못함에도 불구하고 비저항이 2.7μΩcm 정도로 낮고 공정이 비교적 용이하기 때문에 금속 배선 물질로서 가장 널리 사용되어 왔다. 그러나, 디자인 룰이 0.25㎛ 급으로 축소되면서 스텝 커버리지(step coverage)가 열악한 물리기상증착(Physical Vapor Deposition, PVD) 방식의 알루미늄 증착을 통해 충분한 콘택 매립을 이룰 수 없고, 일렉트로마이그레이션(electromigration) 특성 등에 의해 열화되는 문제점이 있었다.Aluminum (Al) has been most widely used as a metal wiring material because of its low resistivity as low as 2.7 μΩcm and relatively easy process, despite its poor contact embedding properties. However, due to the design rule being reduced to 0.25㎛, physical contact deposition (PVD) -based aluminum deposition with poor step coverage could not achieve sufficient contact filling, and electromigration characteristics. There was a problem deteriorated by.
이러한 알루미늄 금속배선의 한계를 고려하여 알루미늄에 비해 콘택 매립 특성이 우수한 구리를 금속배선 재료로 사용하는 기술에 대한 관심이 높아가고 있다. 통상적으로 구리를 사용하여 금속배선을 형성할 때 화학기상증착법(CVD)을 사용하고 있다.Considering the limitations of the aluminum metal wiring, there is a growing interest in the technology of using copper as a metal wiring material, which has better contact embedding properties than aluminum. In general, chemical vapor deposition (CVD) is used to form metal wiring using copper.
그런데, 구리는 식각 특성이 매우 불량한 단점을 가지고 있어 일반적인 금속배선 형성 공정에 적용하기 어렵다. 즉, 고단차비를 가지는 금속배선의 형성시 금속배선의 CD 균일도(critical dimension uniformity), 라인 식각 프로파일(line etch profile) 및 포토레지스트의 식각 선택비 등에서 만족할만한 결과를 얻기 힘들다. 이러한 구리의 단점을 극복하기 위하여 대머신 금속배선 공정이 사용되고 있다.By the way, copper has a disadvantage that the etching characteristics are very poor, it is difficult to apply to the general metal wiring forming process. That is, it is difficult to obtain satisfactory results in the CD uniformity, the line etch profile and the etching selectivity of the photoresist of the metal wiring when the metal wiring having the high step ratio is formed. In order to overcome the drawbacks of copper, a metallization process is used.
통상적인 대머신 금속배선 공정은 층간절연막에 라인용 트렌치 및 콘택홀을 형성하고, 베리어 금속과 구리를 증착한 후 화학적·기계적 평탄화(chemical mechanical planarization, CMP) 기술을 이용하여 층간절연막 상부에 있는 베리어 금속 및 배선 금속을 제거하는 과정을 거치고 있다.Conventional damascene metallization processes form trenches and contact holes for interlayer dielectrics, deposit barrier metals and copper, and then use chemical mechanical planarization (CMP) technology to form barriers on top of the interlayer dielectrics. It is in the process of removing metal and wiring metal.
그러나, 이와 같이 대머신 공정을 적용하는 경우에도 문제점은 있다. 즉, 금속배선간의 피치가 작아짐에 따라 RC-지연이 증가하는 문제점이 발생한다. 이러한 대머신 타입의 금속배선의 RC-지연을 줄이기 위한 하나의 방법으로 저유전율 절연막을 사용하고 있다.However, there is a problem also in applying the damascene process in this way. In other words, the RC-delay increases as the pitch between metal wires becomes smaller. A low dielectric constant insulating film is used as a method to reduce the RC-delay of such large-machined metal wiring.
한편, 구리(Cu)는 알루미늄(Al)과 달리 층간절연막(주로, SiO2)을 통해 확산이 일어나며, 층간절연막을 통과하여 기판쪽으로 이동한 구리는 실리콘 내에서 딥 레벨 불순물(deep level dophant)로 작용하여 Si의 포비든 밴드(forbidden band) 내에 여러 개의 억셉터(acceptor)와 도우너(donor) 레벨을 형성시킨다. 이러한 딥 레벨 도펀트는 생성-재결합(generation-recombination)의 소오스로 작용하여 누설 전류를 유발시킨다. 따라서, 구리를 배선공정에 도입하려면 이종 금속과 접촉하는 부분은 물론이고 층간절연막으로 이루어진 측벽 부분에도 구리확산방지막(Cu diffusion barrier)을 필수적으로 사용해야 한다. On the other hand, unlike aluminum (Al), copper (Cu) diffuses through an interlayer insulating film (mainly SiO 2 ), and copper that moves through the interlayer insulating film toward the substrate is a deep level dopant in silicon. It acts to form several acceptor and donor levels in the forbidden band of Si. These deep level dopants act as sources of generation-recombination to cause leakage currents. Therefore, in order to introduce copper into the wiring process, a Cu diffusion barrier must be used not only in contact with dissimilar metals but also in sidewall portions formed of interlayer insulating films.
최근, 구리확산방지막으로 이온화 물리기상증착(ionised PVD)법으로 증착한 TaN(정확하게는, TaNx)막을 사용하고 있다. TaN은 TiN과 같은 천이금속계 질화물로서 열적으로 매우 안정한 반면, Ta2N의 경우 180∼200μΩ·㎝로 비저항 값이 높은 문제점이 있다.
In recent years, a TaN (exactly TaN x ) film deposited by ionization physical vapor deposition (ionized PVD) as a copper diffusion film is used. While TaN is thermally very stable as a transition metal nitride such as TiN, Ta 2 N has a problem of having a high specific resistance value of 180 to 200 μΩ · cm.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 구리확산방지막의 비저항 특성을 확보할 수 있는 구리를 사용한 대머신 금속배선 형성방법을 제공하는데 그 목적이 있다.
The present invention has been proposed in order to solve the problems of the prior art as described above, and an object thereof is to provide a method for forming a metal wire using a copper capable of securing the resistivity of a copper diffusion barrier.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 구리를 사용한 대머신 금속배선 형성방법에 있어서, 구리확산방지막으로서 α-Ta의 상(phase)을 가지는 탄탈륨막을 사용하는 구리를 사용한 대머신 금속배선 형성방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, in the method of forming a metal machine wiring using copper, using copper using a tantalum film having a phase of α-Ta as a copper diffusion prevention film A method of forming machine metal wiring is provided.
또한, 본 발명의 다른 측면에 따르면, 소정의 하부층 공정을 마친 기판 상에 형성된 층간절연막을 식각하여 대머신 패턴을 형성하는 제1 단계; 상기 제1 단계를 마친 전체 구조 표면을 따라, 250∼500℃의 온도에서 물리기상증착법으로 증착된 탄탈륨막을 포함하는 구리확산방지막을 형성하는 제2 단계; 상기 제2 단계를 마친 전체 구조 표면에 구리 씨드층을 형성하는 제3 단계; 및 상기 대머신 패턴 내에 구리막을 매립하는 제4 단계를 포함하는 구리를 사용한 대머신 금속배선 형성방법이 제공된다.In addition, according to another aspect of the invention, the first step of forming a damascene pattern by etching the interlayer insulating film formed on the substrate after the predetermined lower layer process; A second step of forming a copper diffusion prevention film including a tantalum film deposited by physical vapor deposition at a temperature of 250 to 500 ° C. along the entire structure surface of the first step; A third step of forming a copper seed layer on the entire surface of the structure after the second step; And a fourth step of forming a metal wire using copper, the fourth step of embedding a copper film in the damascene pattern.
본 발명은 구리확산방지막으로 Ta막을 사용하되, 고온(250∼500℃)에서 비저항 값이 낮은 α-Ta막으로 증착하여 사용한다. TaNx막의 경우는 화학양론(stoichiometry)에 따라 비저항값이 변화하지만, 순수한 Ta막은 β-Ta의 경우는 180∼200μΩ·㎝, α-Ta의 경우는 20∼30μΩ·㎝와 같이 상(phase)에 따라 비저항값이 다르게 나타난다. 한편, 구리 확산에 대한 Ta막의 베리어 특성을 보다 강화하기 위하여 Ta막 상부 또는 하부에 TaNx막을 더 적용할 수 있다.In the present invention, a Ta film is used as the copper diffusion preventing film, but is deposited by using an α-Ta film having a low specific resistance at high temperature (250 to 500 ° C.). In the case of TaN x film, the specific resistance value changes according to stoichiometry, but pure Ta film is 180 ~ 200μΩ · cm for β-Ta and 20-30μΩ · cm for α-Ta. The specific resistance value is different according to. On the other hand, in order to further strengthen the barrier properties of the Ta film to the copper diffusion may be further applied to the TaN x film on the upper or lower Ta film.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1 내지 도 4는 본 발명의 일 실시예에 따른 구리를 사용한 싱글 대머신 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1 to 4 illustrate a single damascene metal wiring forming process using copper according to an embodiment of the present invention, which will be described with reference to the following.
우선, 도 1에 도시된 바와 같이 소정의 하부층 공정을 마친 기판(10) 상에 형성된 층간절연막(11)을 선택적으로 식각하여 대머신 패턴을 형성한다.First, as shown in FIG. 1, the
다음으로, 도 2에 도시된 바와 같이 전체 구조 표면을 따라 구리확산방지막으로서 50∼500Å 두께의 Ta막(12)을 증착한다. 이때, Ta막(12)은 PVD법으로 증착 하며, 250∼500℃의 고온에서 증착하여 대부분이 α-Ta의 상(phase)을 가지도록 한다. 한편, Ta막(12)의 하부 또는 상부에 50∼500Å 두께의 TaNx막(도시되지 않음)을 더 증착하는 것이 바람직하며, 이때 TaNx막의 질소(N) 함량은 5∼40at%가 되도록 한다.Next, as shown in FIG. 2, a
이어서, 도 3에 도시된 바와 같이 무전해도금법 또는 화학기상증착(CVD)법을 이용하여 전체 구조 표면을 따라 구리 씨드층(13)을 형성한다.Next, as shown in FIG. 3, the
다음으로, 도 4에 도시된 바와 같이 전해도금법으로 대머신 패턴 내에 구리막(14)을 매립하고 화학적·기계적 연마(CMP) 공정을 실시하여 금속배선을 디파인한다.Next, as shown in FIG. 4, the
상기와 같은 공정을 실시하는 경우, 비저항 값이 20∼30μΩ·㎝로 매우 낮은 구리확산방지막을 얻을 수 있다. 한편, 구리 씨드층 형성시 기존의 PVD법 대신 무전해도금법 또는 화학기상증착(CVD)법을 이용하는데, 이는 이전 공정인 구리확산방지막 증착시 고온 공정을 이용하기 때문에 PVD법으로 구리 씨드층을 형성하면 Cu의 응집(agglomeration)을 피할 수 없기 때문이다. 즉, 무전해도금법이나 CVD법은 구리확산방지막 증착 후 웨이퍼를 진공 챔버에서 꺼내어 따로 진행하기 때문에 Cu의 응집을 염려할 필요가 없으며, CVD법의 경우 150℃ 이상의 웨이퍼 온도에서 수행하므로 프리-히팅(pre-heating) 시간을 최소화할 수 있는 장점이 있다.
When the above steps are carried out, a very low copper diffusion prevention film having a specific resistance value of 20 to 30 µΩ · cm can be obtained. In the meantime, the copper seed layer is formed using an electroless plating method or a chemical vapor deposition (CVD) method instead of the conventional PVD method, and the copper seed layer is formed by the PVD method because a high temperature process is used when the copper diffusion barrier film is deposited. This is because agglomeration of Cu cannot be avoided. That is, the electroless plating method or the CVD method takes the wafer out of the vacuum chamber after deposition of the copper diffusion film and proceeds separately, so there is no need to worry about agglomeration of Cu. There is an advantage to minimize the pre-heating time.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
삭제delete
전술한 본 발명은 구리를 사용한 대머신 공정시 비저항 값이 낮은 α-Ta의 상을 가지는 Ta막을 구리확산방지막으로 사용함으로써 기존의 TaNx에 비해 콘택 저항을 1/10 정도로 줄일 수 있는 효과가 있으며, 이로 인하여 구리배선의 신뢰도를 높일 수 있다.
The present invention described above has the effect of reducing the contact resistance by about 1/10 compared to the conventional TaNx by using a Ta film having a phase of α-Ta having a low specific resistance value as a copper diffusion film in a damascene process using copper. This can increase the reliability of the copper wiring.
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| KR100243286B1 (en) * | 1997-03-05 | 2000-03-02 | 윤종용 | Method for manufacturing a semiconductor device |
| KR20010033174A (en) * | 1997-12-19 | 2001-04-25 | 조셉 제이. 스위니 | A tailored barrier layer which provides improved copper interconnect electromigration resistance |
| KR20010050926A (en) * | 1999-10-08 | 2001-06-25 | 조셉 제이. 스위니 | Self-ionized plasma for sputtering copper |
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| KR100243286B1 (en) * | 1997-03-05 | 2000-03-02 | 윤종용 | Method for manufacturing a semiconductor device |
| KR20010033174A (en) * | 1997-12-19 | 2001-04-25 | 조셉 제이. 스위니 | A tailored barrier layer which provides improved copper interconnect electromigration resistance |
| KR20010050926A (en) * | 1999-10-08 | 2001-06-25 | 조셉 제이. 스위니 | Self-ionized plasma for sputtering copper |
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| KR20150135045A (en) * | 2014-05-23 | 2015-12-02 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Device and method for reducing contact resistance of a metal |
| KR101665784B1 (en) * | 2014-05-23 | 2016-10-12 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Device and method for reducing contact resistance of a metal |
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