KR100268788B1 - Metal wiring formation method of semiconductor device - Google Patents

Abstract

PURPOSE: A metal interconnection formation method is provided to prevent voids and to improve a surface roughness by depositing aluminum alloys using CVD(chemical vapor deposition) and PVD(physical VD). CONSTITUTION: An anti-diffusion layer(3) is formed on a planarized insulator(2). An adhesive layer(4) and a CVD aluminum alloy(5) are sequentially deposited on the anti-diffusion layer(3). A low temperature PVD aluminum alloy(6) and a high temperature PVD aluminum alloy(7) are sequentially deposited on the CVD aluminum alloy(5) by in-situ. Then, an anti-diffusion layer is formed on the resultant structure. The CVD aluminum alloy(5) is deposited at the temperature of 100-0250 °C, the low temperature PVD aluminum alloy(6) is deposited at the temperature of room temperature-100 °C, and the high temperature PVD aluminum alloy(7) is deposited at the temperature of 400-0550 °C.

Description

Metal wiring formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and more particularly, to planarization of an aluminum alloy, which is a metal wiring material.

In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is made through a subsequent process by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer. Metal wiring is used where resistance is required.

The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and excellent workability. Landfilling is the most widely used.

In the physical vapor deposition method widely used in the prior art, the process is carried out by physical apparatus without chemical reaction. In addition, the sputtering method, which is a kind of physical vapor deposition method, ionizes, ie, plasmas, a gas of low pressure by an external applied voltage to form gas ions, and the gas ions are accelerated by a potential difference to hit the negative electrode target. At this time, the atoms of the target are protruded by the collision of the gas ions to aggregate and grow on the surface of the base material to form a thin film. In general, argon is used as the low pressure gas.

The sputtering method has an advantage that the process is performed at a low temperature compared to the chemical vapor deposition method, and the process is simple.

However, there is a problem that the specific resistance of the metal thin film is increased due to the increase of defects in the metal thin film, and as the design rule becomes smaller, the resistance value of the metal wiring becomes large, and the reliability aspects such as the electromigration (EM) phenomenon to the metal thin film and RC) adversely affects device characteristics such as delay.

In order to solve this problem, the aluminum alloy planarization process using the CVD method and the PVD method has a problem that the surface roughness becomes a problem, making the etching process using the mask difficult.

Accordingly, the present invention provides a method for forming a metal wiring of a semiconductor device that can improve the characteristics and reliability of the semiconductor device by forming a flattened metal wiring to facilitate the subsequent process in order to solve the above problems of the prior art. The purpose is.

1 (a) to 1 (d) are cross-sectional views showing a metal wiring formation method of a semiconductor device in an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 planarization insulating film

3: diffusion barrier 4: wet layer

5: CVD aluminum alloy layer 6: low temperature PVD aluminum alloy layer

7: high temperature PVD aluminum alloy layer 8: flattened aluminum alloy layer

9: antireflection film

In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,

Forming a diffusion barrier over the planarization insulating film on which the contact hole is formed;

Sequentially depositing a wet layer and a CVD aluminum alloy layer on the diffusion barrier;

Forming a low-temperature PVD aluminum alloy layer and a high-temperature PVD aluminum alloy layer sequentially on the CVD aluminum alloy layer without vacuum destruction;

It characterized in that it comprises a step of forming an anti-reflection film on the high temperature PVD aluminum alloy layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 (a) to 1 (d) are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.

First, a planarization insulating film 2 having contact holes formed on the semiconductor substrate 1 is formed, a pretreatment process is performed, and then a diffusion barrier 3 is formed on the entire surface.

At this time, the planarization insulating film 2 is formed of an isolation material, a word line, a bit line and a capacitor, and then formed of an insulating material having excellent fluidity.

The diffusion barrier 3 is formed of a nitride film-based compound such as TiN, WN, TaN, or a silicon nitride film-based compound such as TiSiN, WSiN, or the like (FIG. 1 (a)).

Then, the wet layer 4 and the CVD aluminum alloy layer 5 are sequentially formed on the diffusion barrier 3.

At this time, the wet layer 4 is formed of a material such as Ti. Then, the CVD aluminum alloy layer 5 is formed to a thickness of about 400 ~ 1000 Pa at a temperature of about 100 ~ 250 ℃ by using a CVD method (Fig. 1 (b)).

Next, the low-temperature PVD aluminum alloy layer 6 and the high-temperature PVD aluminum alloy layer 7 are sequentially stacked on the CVD aluminum alloy layer 5.

At this time, the low-temperature PVD aluminum alloy layer 6 and the high-temperature PVD aluminum alloy layer 7 are sequentially stacked on the low-temperature PVD aluminum alloy layer 5.

At this time, the process of forming the low-temperature PVD aluminum alloy layer 6 and the high-temperature PVD aluminum alloy layer 7 is moved to a sputtering chamber maintained at high temperature and high vacuum without vacuum destruction after deposition of the CVD aluminum alloy layer 5 to thereby provide a semiconductor substrate. (1) That is, it is deposited in a short time with a high power of about 5 to 25 kW without heating the wafer, and then the wafer is sufficiently heated and flattened by depositing an aluminum alloy with a low deposition power of 0.1 to 5 kW or less at high temperature. It is possible to form the aluminum alloy layer 8 thus formed.

In addition, the deposition process of the low-temperature PVD aluminum alloy layer 6 and the high-temperature PVD aluminum alloy layer 7 may be formed in one chamber, or may be formed using two chambers whose temperature is controlled.

The low-temperature PVD aluminum alloy layer 6 and the high-temperature PVD aluminum alloy layer 7 are formed at temperatures of about room temperature to about 100 ° C. and about 400 to 550 ° C., respectively. At this time, the temperature of about 400 ~ 550 ° C is adjustable according to the step ratio of the contact (Fig. 1 (c)).

Next, an antireflection film 9 for patterning is formed on the planarized aluminum alloy layer 8 (FIG. 1 (d)).

In another embodiment of the present invention, a method of forming a multi-layered metal wiring includes: wafer degassing / contact oxide removal / wet layer or outgassing prevention film deposition / CVD aluminum alloy layer deposition / low temperature. PVD aluminum alloy layer deposition / high temperature PVD aluminum alloy layer deposition / antireflection film deposition and the like.

As described above, in the method of forming a metal wiring of the semiconductor device according to the present invention, deposition of an aluminum alloy layer by CVD and PVD method prevents induction of voids, and deposition of an aluminum alloy layer at high and low temperatures reduces surface roughness. This facilitates the subsequent process, thereby improving the characteristics and reliability of the semiconductor device.

Claims (7)

Forming a diffusion barrier over the planarization insulating film on which the contact hole is formed; sequentially depositing a wet layer and a CVD aluminum alloy layer over the diffusion barrier; and a low temperature PVD aluminum alloy without vacuum destruction on the CVD aluminum alloy layer And forming a layer and a high temperature PVD aluminum alloy layer sequentially, and forming an anti-reflection film on the high temperature PVD aluminum alloy layer. The method of claim 1, wherein the diffusion barrier is formed of a metal thin film of a nitride film system or a silicon nitride film system. The method of claim 1, wherein the CVD aluminum alloy layer is formed to have a thickness of 400 to 1000 kPa at a temperature of 100 to 250 ° C. 7. The method of claim 1, wherein the low-temperature PVD aluminum alloy layer is formed at room temperature to 100 ° C. at a power of 5 to 25 kW. The method of claim 1, wherein the high temperature PVD aluminum alloy layer is formed at a temperature of 400 ° C. to 550 ° C. with a deposition power of 0.1 to 5 kW. 6. The method of claim 1, 4, or 5, wherein the low temperature and high temperature PVD aluminum alloy layer is formed in one deposition chamber. 6. The method of claim 1, 4 or 5, wherein the low temperature and high temperature PVD aluminum alloy layers are formed in a deposition chamber having a thickness, respectively.

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