KR100353534B1 - Method for forming metal interconnection layer in semiconductor device - Google Patents
Method for forming metal interconnection layer in semiconductor device Download PDFInfo
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- KR100353534B1 KR100353534B1 KR1019990060291A KR19990060291A KR100353534B1 KR 100353534 B1 KR100353534 B1 KR 100353534B1 KR 1019990060291 A KR1019990060291 A KR 1019990060291A KR 19990060291 A KR19990060291 A KR 19990060291A KR 100353534 B1 KR100353534 B1 KR 100353534B1
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 80
- 229910004156 TaNx Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005755 formation reaction Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Chemical & Material Sciences (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법을 개시한다. 개시된 발명은 도전층 패턴이 구비된 반도체 기판 상에 층간 절연막을 형성하는 단계, 상기 도전층 패턴의 일부가 노출되도록 상기 층간 절연막을 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀 표면 및 상기 층간 절연막 상에 TaNx층을 형성하는 단계, 상기 TaNx층 상부에 TaNy층을 형성하는 단계, 상기 TaNx층의 일부가 TaSi2로 변환되어 오믹 콘택을 형성하는 단계, 상기 기판 전면에 배선용 금속막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method for forming metal wirings of a semiconductor device. The disclosed invention includes forming an interlayer insulating film on a semiconductor substrate having a conductive layer pattern, etching the interlayer insulating film to expose a portion of the conductive layer pattern to form a contact hole, the surface of the contact hole and the interlayer insulating film Forming a TaNx layer on the TaNx layer, forming a TaNy layer on the TaNx layer, converting a portion of the TaNx layer into TaSi 2 to form an ohmic contact, and forming a wiring metal film on the entire surface of the substrate It is characterized by including.
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 구리막에 대한 배리어 특성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of improving barrier properties for copper films.
반도체 디바이스의 고집적화에 따라, 배선 설계가 자유롭고 용이하며, 배선저항 및 전류 용량 등의 설정을 여유있게 할 수 있는 배선 기술에 관한 연구가 활발히 진행되고 있다. 이러한 고집적화에 따라 알루미늄 배선 보다 비저항이 낮고 전기 전도도가 높은 구리 배선이 사용되고 있다. 그러나, 구리 배선을 이용하는 경우에는 구리의 높은 확산도를 감안하여 콘택홀 전체에 배리어 금속막(확산 방지막)을 형성하여야 한다.BACKGROUND ART With the high integration of semiconductor devices, research on wiring technology that allows free and easy wiring design and allows setting of wiring resistance and current capacity, etc., has been actively conducted. Due to such high integration, copper wirings having a lower resistivity and higher electrical conductivity than aluminum wirings are used. However, in the case of using copper wiring, a barrier metal film (diffusion prevention film) should be formed in the entire contact hole in consideration of the high diffusivity of copper.
현재 구리 배선 공정은 주로 반도체 소자의 다층 배선 구조에서 2층 이상의 금속 배선에 적용 연구되고 있다. 즉, 구리 배선의 연구는 하나의 금속(W 또는 Al)공정 이후 절연층을 형성하고 구리 배선을 위한 콘택홀을 형성하고 Ta 또는 TaN의 확산 방지막과 구리 배선을 증착하는 기술을 적용하고 있다.Currently, the copper wiring process is mainly applied to two or more layers of metal wiring in a multilayer wiring structure of a semiconductor device. That is, the research of copper wiring is applied a technique of forming an insulating layer after a metal (W or Al) process, forming a contact hole for copper wiring, and depositing a diffusion barrier and a copper wiring of Ta or TaN.
확산 방지막으로 쓰이는 Ta은 bcc 구조의 Ta인 경우 비저항이 ~40μΩcm 이며 β-Ta인 경우 ~180μΩcm정도이다. 또한, TaN 박막은 슈도-메탈릭 (pseudo-metallic) 영역에서는 fcc구조와 정육방형(hexagonal)구조의 혼합상을 보이며 ~225μΩcm의 비저항을 가지고 포이즌(poisoned)영역에서는 비정질에 가까운 fcc구조로서 ~수 천μΩcm의 비저항을 갖는다. 따라서 질소 유량이 증가함에 따라 확산 방지막의 특성이 향상되는 잇점이 있었다.Ta used as a diffusion barrier has a specific resistance of ~ 40μΩcm for Ta of bcc structure and ~ 180μΩcm for β-Ta. In addition, TaN thin film shows a mixed phase of fcc structure and hexagonal structure in pseudo-metallic region, has a resistivity of ~ 225μΩcm, and is close to amorphous in poisoned region. It has a specific resistance of μΩcm. Therefore, there was an advantage that the characteristics of the diffusion barrier film improved as the nitrogen flow rate increased.
구리 배선 공정시 첫 번째 금속을 증착하기 위한 콘택홀을 만든 후 실리콘 기판 위에 이온주사방법에 의해 원하는 종류의 이온 도핑을 실시하여 소스/드레인 영역을 형성한 후 그 위에 적당한 두께의 Ta박막을 증착한 다음 급속 열처리에 의해 상호 확산시켜 TaSi2층을 형성한다. 이때 TaSi2층은 실리콘 기판과 금속 배선과의 스트레스를 줄이게 된다.In the copper wiring process, a contact hole for depositing the first metal was formed, and then a desired type of ion doping was performed on the silicon substrate by ion scanning to form a source / drain region, and then a Ta thin film having an appropriate thickness was deposited thereon. It is then diffused by rapid heat treatment to form a TaSi 2 layer. At this time, the TaSi 2 layer reduces the stress between the silicon substrate and the metal wiring.
그러나, 확산 방지막의 증착시 질소 유량의 증가는 막의 특성을 향상시키기는 하나, 비저항이 급격히 증가되어 금속배선의 저항이 증가되는 문제가 야기된다.However, an increase in nitrogen flow rate during deposition of the diffusion barrier film improves the film properties, but causes a problem in that the resistivity is rapidly increased to increase the resistance of the metal wiring.
또한, 급속 열처리에 의한 TaSi2층(30~45μΩcm)의 형성시 정확한 두께의 조절이 어려워 웨이퍼 내에 균일한 두께의 TaSi2층을 형성하기 어렵고, 열공정시 Ta원소가 이온 주입된 이온들과 반응을 일으켜 소스/드레인 영역을 파괴시킬 수도 있다. 이러한 문제로 인하여 콘택 저항이 증가되고 누설 전류가 증가해 반도체 소자의 특성을 열화시키므로 반도체 소자에의 적용을 어렵게 한다.In addition, when the TaSi 2 layer (30-45 μΩcm) is formed by rapid heat treatment, it is difficult to precisely control the thickness of the TaSi 2 layer, so that it is difficult to form a TaSi 2 layer with a uniform thickness in the wafer. It can also destroy the source / drain regions. Due to this problem, the contact resistance is increased and the leakage current is increased to deteriorate the characteristics of the semiconductor device, making it difficult to apply to the semiconductor device.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 기존의 구리 배선 공정에서 Ta층만 증착할 때 생기는 확산 방지막 특성의 열화문제, TaN층만을 증착할 때 생기는 저항 증가 문제 및 Ta/TaN 적층구조 적용시 생기는 공정의 복잡성등의 문제를 해결할 수 있는 반도체 소자의 금속 배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-described problems, the problem of deterioration of the diffusion barrier properties when depositing only the Ta layer in the conventional copper wiring process, the problem of increased resistance when depositing only the TaN layer and Ta / TaN lamination It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can solve problems such as the complexity of the process that occurs when applying the structure.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
10 : 반도체 기판 11 : 절연층10 semiconductor substrate 11 insulating layer
12 : TaNx층 13 : TaNy층12: TaNx layer 13: TaNy layer
14 : TaSi2층 15 : 구리 금속층14 TaSi 2 layer 15 Copper metal layer
16 : 반사방지막16: antireflection film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성방법은 도전층 패턴이 구비된 반도체 기판 상에 층간 절연막을 형성하는 단계; 층간 절연막을 식각하여 도전층 패턴의 일부를 노출시키는 콘택홀을 형성하는 단계; 층간 절연막 상에 콘택홀을 덮는 TaNx층 및 TaNy층(0<x<y<1)을 차례로 형성하는 단계; 상기 결과물에 열처리 실시하여 TaNx층의 일부를 TaSi2층으로 변환시키는 단계; TaSi2층이 형성된 기판 전면에 배선용 금속막을 형성하는 단계를 포함하는 것을 특징으로 한다.본 발명에 의하면 예정된 두께의 Ta층 또는 TaN층을 증착하는 대신 일정 두께의 TaNx/TaNy(0<x <y<1)를 증착하여 TaSi2층의 두께를 조절할 수 있다.Method of forming a metal wiring of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate provided with a conductive layer pattern; Etching the interlayer insulating film to form a contact hole exposing a portion of the conductive layer pattern; Sequentially forming a TaNx layer and a TaNy layer (0 <x <y <1) covering the contact hole on the interlayer insulating film; Heat-treating the resultant to convert a portion of the TaNx layer into a TaSi 2 layer; And forming a wiring metal film on the entire surface of the substrate on which the TaSi 2 layer is formed. According to the present invention, instead of depositing a Ta layer or a TaN layer of a predetermined thickness, TaNx / TaNy (0 <x <y) of a predetermined thickness may be used. <1) may be deposited to control the thickness of the TaSi 2 layer.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 1a는 실리콘 기판에 소정의 절연막을 형성한 후 예정된 부위에 도전층 내지는 실리콘 기판에 연결되는 금속 콘택을 형성한 후, 전처리 공정을 통해 콘택 하부에 형성된 자연 산화막을 제거한 후, 고진공으로 유지된 반응성 스퍼터링 장치를 이용하여 과잉 탄탈륨층인 TaNx층을 형성한 후의 상태를 나타낸 단면도이다. TaNx층의 증착 두께는 10~600Å이 바람직하다. TaNx층은 과잉탄탈륨층의 형태로 증착하여 고온 열처리 시에 상부의 TaNy층이 TaSi2층의 형성에는 기여하지 않고 하부 TaNx층만이 오믹 접합의 형성에 기여함으로써 매우 얇은 TaSi2층을 형성한다. 이 얇은 TaSi2층은 소스/드레인 영역의 파괴를 억제하고 오믹접합을 이루게 하여 콘택 저항을 최소화하고 누설전류를 안정화시킬 수 있다. 이들 TaNx층의 두께는 증착 장치의 성능과 소자의 콘택 단차비에 따라 다르나 일반적으로 예정된 전체 확산 방지층 두께 중 10-60%를 증착하여 추후 형성될 TaSi2층의 두께를 조절한다. 증착 후 동일 스퍼터링 챔버에서 진공 파괴없이 질소의 유량을 증가시킨 TaNy 층을 증착한 상태를 나타낸 단면도로 이는 급속 열처리 등을 이용한 후속 열처리에도 TaSi2형성에 기여하지 않고 단지 확산 방지층의 역할만을 한다. TaNx 층의 증착 조건은 증착온도가 상온~500℃, 증착압력은 1~100mtorr, 아르곤 가스 및 질소 가스의 유량은 10~200 sccm, 증착 전력은 1~100kW이다. TaNy 층의 형성은 TaNy 층이 x < y < 1인 것을 특징으로 하며 그 두께도 10~600Å인 것이 바람직하다. 또한 TaNy 층의 증착 조건도 TaNx 층의 조건과 같다.FIG. 1A illustrates a reactive film maintained at a high vacuum after forming a predetermined insulating film on a silicon substrate, forming a metal contact connected to a conductive layer or a silicon substrate at a predetermined site, and removing a natural oxide film formed under the contact through a pretreatment process. It is sectional drawing which shows the state after forming the TaNx layer which is an excess tantalum layer using a sputtering apparatus. The deposition thickness of the TaNx layer is preferably 10 to 600 Pa. The TaNx layer is deposited in the form of an excess tantalum layer so that at the time of high temperature heat treatment, the upper TaNy layer does not contribute to the formation of the TaSi 2 layer but only the lower TaNx layer contributes to the formation of the ohmic junction, thereby forming a very thin TaSi 2 layer. This thin TaSi 2 layer suppresses the breakdown of the source / drain regions and allows ohmic junctions to minimize contact resistance and stabilize leakage currents. The thickness of these TaNx layers depends on the performance of the deposition apparatus and the contact step ratio of the device, but generally deposits 10-60% of the predetermined total diffusion barrier layer thickness to control the thickness of the TaSi 2 layer to be formed later. After deposition, a cross-sectional view showing a state of depositing a TaNy layer in which the flow rate of nitrogen was increased without vacuum destruction in the same sputtering chamber. This does not contribute to TaSi 2 formation even in subsequent heat treatment using rapid heat treatment, but only serves as a diffusion barrier layer. Deposition conditions of the TaNx layer is a deposition temperature of room temperature ~ 500 ℃, deposition pressure of 1 ~ 100mtorr, argon gas and nitrogen gas flow rate of 10 ~ 200 sccm, deposition power is 1 ~ 100kW. Formation of the TaNy layer is characterized in that the TaNy layer is x <y <1, and the thickness thereof is also preferably 10 to 600 kPa. The deposition conditions of the TaNy layer are also the same as those of the TaNx layer.
도 1b는 TaNx/TaNy 층 증착 후 급속 열처리 혹은 노 등을 이용하여 열처리를 한 후의 상태를 나타낸 단면도로 실리콘 기판과 반응하여 TaN/TaSi2/실리콘 기판을 형성한 상태이다. 열처리법의 조건은 온도가 650~1000℃, 시간은 10~100초, 질소가스 또는 아르곤 가스의 분위기에서 실행시킨다.FIG. 1B is a cross-sectional view illustrating a state after the TaNx / TaNy layer is deposited, followed by rapid heat treatment or heat treatment using a furnace, and the like to form a TaN / TaSi 2 / silicon substrate by reacting with a silicon substrate. The conditions of the heat treatment method are carried out in an atmosphere of nitrogen gas or argon gas at a temperature of 650 to 1000 캜, a time of 10 to 100 seconds.
도 1c는 열처리 후 화학기상증착법(Chemical Vapor Deposition:CVD) 혹은 물리기상증착법(Physical Vapor Deposition:PVD)을 이용하여 구리의 금속 배선을 증착하고 반사방지층을 증착한 후 배선 마스크 공정 및 식각 공정을 진행하여 금속배선을 형성한 상태를 나타낸 단면도이다.FIG. 1C illustrates a process of etching a metal wire and depositing an anti-reflection layer after a heat treatment using a chemical vapor deposition (CVD) or a physical vapor deposition (PVD), followed by a wiring mask process and an etching process. Is a cross-sectional view showing a state in which metal wiring is formed.
이상에서와 같이 본 발명은 확산 방지층 형성에 있어 기존의 Ta, TaN, Ta/TaN 층 혹은 TaNx층 대신 TaNx층/TaNy 층을 형성하여 원하는 두께의 TaSi2층의 형성을 가능하게 한다.As described above, the present invention enables the formation of a TaSi 2 layer having a desired thickness by forming a TaNx layer / TaNy layer instead of the existing Ta, TaN, Ta / TaN layer or TaNx layer in forming a diffusion barrier layer.
상기한 본 발명에 의하면,확산 방지 금속층 형성을 위해 TaSi2형성하기 때문에 후속 열공정에서 과잉 탄탈륨인 TaNx 층만이 TaSi2 형성반응에 기여하므로 매우 얇은 TaSi2를 형성할 수 있고 이로 인해 양호한 콘택 특성을 얻을 수 있음과 동시에 TaNy층이 고온 열처리 후에도 매우 안정하게 유지될 수 있다. 따라서, 기존의 Ta/TaN 공정 내지는 TaNx 공정보다 개선된 결과를 얻을 수 있다.According to the present invention described above, since TaSi 2 is formed to form a diffusion preventing metal layer, only a TaNx layer, which is excess tantalum, contributes to the TaSi 2 formation reaction in a subsequent thermal process, thereby forming a very thin TaSi 2, thereby obtaining good contact characteristics. At the same time, the TaNy layer can be kept very stable even after high temperature heat treatment. Therefore, improved results can be obtained over the existing Ta / TaN process or TaNx process.
뿐만 아니라 TaNx/TaNy(x < y < 1)의 연속 증착에 의한 공정 단순화와 소자 특성이 향상되므로 소자의 수율과 신뢰성이 향상된다.In addition, process simplification and device characteristics are improved by continuous deposition of TaNx / TaNy (x <y <1), thereby improving device yield and reliability.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시될 수 있다.In addition, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the technical spirit of the present invention.
Claims (9)
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