JPH06120355A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the oxidation of metals of high melting-point even in a high-temperature oxidative atmosphere by forming a coat in the surface of a layer for wiring electrodes after the layer for wiring electrodes is formed and after that, applying thereto a heat treatment, an oxidation treatment, the deposition of an insulating film and the like. CONSTITUTION:An n-type diffused layer 2 of n-type impurities is formed in the desired region of the surface of a p-type silicon substrate 1. Consecutively, an SiO2 film 3 is deposited in the whole surface of the substrate 1, and then a contact hole 4 is opened. A layer for wiring of three-layer structure composed of a polycrystalline silicon films 5, a TiN film 6 and a W film 7 is formed in the upper part of the SiO2 film 3 including the contact hole 4. An aluminum oxide film 9 is formed on the surface of the layer for wiring and the SiO2 film 3. Next, an SiO2 film 10 is deposited in the upper surface of the aluminum oxide film 9, and consecutively a BPSG film 11 is deposited. After that, a heat treatment is applied thereto to complete the formation of a wiring. Thereby, since a heat treatment is performed in a subsequent process, the oxidation of a metal layer can be prevented.

Description

Detailed Description of the Invention

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an electrode wiring structure.

[0003]

2. Description of the Related Art Conventionally, polycrystalline silicon has been widely used as electrodes and wirings of semiconductor devices. However,
With the high integration and high speed of semiconductor devices, signal transmission delay due to low resistance of electrode wiring has become a serious problem. Particularly in the field of MOSLSI, which has a large capacity and a high degree of integration, the polycrystalline silicon conventionally used for the gate electrode is shared with the first layer wiring, so that the resistance here impairs the high speed operation of the device. Has become.

Therefore, as a wiring material replacing polycrystalline silicon, silicide of a refractory metal having thermal stability and electrical resistance is being used. Further, recently, there has been an attempt to use refractory metal itself such as W and Mo as electrode wiring. Refractory metals such as W and Mo
Has an electric resistivity two orders of magnitude lower than that of polycrystalline silicon, and is 1/4 to 1/3 of the resistivity of silicide, and is therefore expected as a low resistance electrode wiring.

The following method can be given as an example of a method for forming an electrode wiring using a refractory metal. First, a polycrystalline silicon film is deposited on a silicon substrate through a gate oxide film by the LPCVD method, an n-type or p-type impurity is introduced, and a TiN film and a W film are sequentially deposited thereon by sputtering. Next, the formation of the electrode is completed by patterning these by ordinary photolithography and reactive ion etching using a fluorine-based gas.

The electrode wiring thus formed must undergo the subsequent post-oxidation step ordinarily used for polycrystalline silicon or silicide, and the interlayer insulating film deposition step. The post-oxidation process is performed at a high temperature of 800 ° C. to 900 ° C. in an oxidizing atmosphere, and the insulating film deposition process is usually performed at 400 ° C. to 500 ° C. However, refractory metals such as W and Mo and pure metals have no resistance to oxidation,
It is easily oxidized by heat treatment in an atmosphere in which residual oxygen of about several ppm exists. For this reason, the electrode wiring using a refractory metal causes a problem such as resistance increase and film peeling due to the subsequent post-oxidation and insulating film deposition steps, and, in the worst case, disappearance of the wiring itself.

Therefore, recently, after the refractory metal is deposited,
A method has been proposed in which a metal or semiconductor having a negative oxide generation energy and a larger value than that of a refractory metal is coated, and then wiring is formed (see Japanese Patent Laid-Open No. 171852/1983). This method aims at using a metal or semiconductor film formed on a refractory metal as a protective film against oxidation.

However, in this method, during heat treatment, a reaction occurs between the refractory metal and the metal or semiconductor formed on the refractory metal to increase the wiring resistance. Further, the side wall portion of the refractory metal after the wiring is formed is exposed, and the side wall portion is oxidized by the subsequent oxidation step and insulating film deposition step. Therefore, the above method is not an effective measure.

[0009]

As described above, W, Mo
It is necessary to prevent post-oxidation or oxidation of the electrode wiring due to deposition of an insulating film or the like in the electrode wiring using a refractory metal such as the above, and attempts have been made to form a protective film on this.
However, the methods proposed so far are not effective solutions because of problems such as increased wiring resistance and oxidation from the side wall.

The present invention has been made in view of the above circumstances. An object of the present invention is to form a stable antioxidation layer on the surface and side wall of an electrode wiring using a refractory metal and to provide a high temperature oxidizing atmosphere. However, it is an object of the present invention to provide a semiconductor device manufacturing method capable of preventing the refractory metal from being oxidized, increasing the wiring resistance and preventing the film from peeling, and improving the throughput and the yield.

[Constitution of Invention]

[0012]

According to the present invention, an electrode wiring layer including a refractory metal layer is formed on a semiconductor substrate on which a semiconductor element is formed, followed by heat treatment, oxidation treatment, or insulating film deposition. In the method for manufacturing a semiconductor device having a step, after forming the electrode wiring layer, a film is formed on the surface of the electrode wiring layer, and then a step of performing heat treatment, oxidation treatment, insulating film deposition, or the like is performed. Aluminum oxide or a refractory metal boride is used as the coating.

[0013]

[Function] The diffusion coefficient of oxygen in aluminum oxide is 4 compared with the diffusion coefficient of silicon oxide which is conventionally used.
Digit smaller. Therefore, when this is used as a film, even when the semiconductor device is heat-treated in an oxidizing atmosphere, oxidizing species from the atmosphere hardly diffuse in the aluminum oxide, and the refractory metal layer that is the electrode wiring is not oxidized. .

Aluminum oxide cannot be an effective protective film because of defects and pinholes that are inevitably present in a PVD film such as chemical conversion sputtering and a film deposited by the CVD method, and also because of low density. In the present invention, aluminum oxide is formed at 500 ° C. after forming aluminum on the entire surface of the wafer.
It is formed by oxidation at the following low temperatures. Since aluminum diffuses into the refractory metal by oxidation at 500 ° C. or higher,
A uniform aluminum oxide cannot be formed. As another method of forming uniform aluminum oxide, there is a method of selectively forming aluminum on the surface of the electrode wiring layer, or a method of incorporating aluminum in a refractory metal and thermally oxidizing the same. Also in this way, high-density aluminum oxide can be formed around the electrode wiring layer.

Metal borides have a higher equilibrium oxygen partial pressure than pure metals and are less likely to be oxidized. Further, even if the boride is oxidized, the boron oxide formed at that time has a low melting point, so that it becomes liquid glass at high temperature and fills the gaps in the metal oxide layer, thereby densifying the oxide layer. To do. Therefore, the inward diffusion of oxidizing species in the oxide layer is suppressed, and the progress of oxidation becomes extremely slow.

Thus, by using aluminum oxide or a boride of a refractory metal as the coating, the oxidation resistance of the electrode wiring is dramatically improved. As a result, the process margin for the oxidation of the electrode wiring in the subsequent heat step is expanded, and it becomes unnecessary to strictly control the furnace configuration and the atmospheric conditions, so that the production throughput and the yield can be improved.

[0017]

The details of the present invention will be described below with reference to the illustrated embodiments.

1 to 3 are process cross-sectional views for explaining a manufacturing method according to the first embodiment of the present invention, which show a state of a contact portion between an electrode wiring and a diffusion layer.

First, as shown in FIG. 1A, for example, p
After n-type impurities such as arsenic are ion-implanted into a desired region of the surface of the silicon substrate 1, heat treatment is performed at 900 ° C. for 30 minutes to form the n ⁺ -type diffusion layer 2. Then, LPCV
After the SiO ₂ film 3 is deposited on the entire surface of the substrate 1 by the D method, the SiO ₂ film 3 is selectively removed by the ordinary photolithography method and the reactive ion etching technique to form the contact hole 4 in the portion corresponding to the diffusion layer 2. Was opened.

Next, as shown in FIG. 1B, a vertical LP
After depositing a polycrystalline silicon film 5 having a thickness of 50 nm on the entire surface of the SiO ₂ film 3 including the contact holes 4 in a CVD furnace,
The range (Rp) of the polycrystalline silicon film 5 is 40 from the surface.
Arsenic ions were implanted under the condition of an acceleration voltage of 65 keV so as to be about nm (near the interface between the substrate 1 and the film 5). By this arsenic ion implantation, impurities of the same conductivity type as the diffusion layer 2 are introduced into the polycrystalline silicon film 5, and the natural oxide film formed at the interface between the silicon substrate 1 and the polycrystalline silicon film 5 is destroyed by ion mixing. Thus, the polycrystalline silicon film 5 was in good contact with the diffusion layer 2.

Then, as shown in FIG. 1C, a Ti target is sputtered by a mixed gas of nitrogen and argon (50% each) by a sputter deposition method to form a TiN film having a thickness of 50 nm on the polycrystalline silicon film 5. Film 6 was deposited.

Then, as shown in FIG. 2D, H ₂ , S
A 150 nm-thickness W film 7 was deposited on the TiN film 6 by the LPCVD method using a mixed gas of iH ₄ and WF ₆ . Here, the gas pressure is H ₂ 0.173 Torr, S
iH ₄ is 0.013 Torr, WF ₆ is 0.065 Torr
The partial pressure of rr was maintained and the substrate temperature was maintained at 420 ° C. After that, as shown in FIG. 2E, the W film 7, the TiN film 6, and the polycrystalline silicon film 5 are sequentially selectively removed by normal photolithography and reactive ion etching using SF ₆ gas to perform a multi-step process. Wiring having a three-layer structure composed of the crystalline silicon film 5, the TiN film 6 and the W film 7 was formed. After that, an Al film 8 having a thickness of 20 nm was formed on the entire surface as shown in FIG. Then, the substrate was immersed in an ethylene glycol solution of ammonium borate, and a DC voltage of 20 V was applied to the wafer as an anode to carry out anodization for 10 minutes. The ethylene borate solution of ammonium borate at this time is at room temperature and is not artificially heated.

With this anodization, as shown in FIG.
An aluminum oxide film (Al ₂ O ₃ ) 9 having a thickness of about 25 nm was formed on the surface of the wiring layer having a three-layer structure including the film 7, the TiN film 6 and the polycrystalline silicon film 5 and on the SiO ₂ film 3. According to Auger electron spectroscopy (AES) analysis, it was confirmed that the Al film 8 was all oxidized into an aluminum oxide film (Al ₂ O ₃ ) 9 and that Al did not diffuse in W at all.

Then, as shown in FIGS. 3 (h) and 3 (i), the substrate was introduced into a quartz tube furnace set at 700 ° C., N ₂ gas was used as a carrier gas, TEOS gas was introduced, and the total pressure was changed. SiO by LPCVD method at 0.8 Torr
_{2 The} film 10 was deposited to a thickness of 0.1 μm. Then, the substrate was introduced into a quartz tube furnace set at 610 ° C., and TEOS20
0 sccm, PH ₃ 300 sccm, TMB (tetramethoxyborane) 20 sccm, O ₂ 300 sccc
Then, the BPSG film 11 was deposited to 0.3 μm at a total pressure of 0.8 Torr. After that, N ₂ is 30 l / min,
POCl ₃ was introduced at a rate of 4 l / min, O ₂ was introduced at a rate of 0.5 l / min, and heat treatment was performed at 850 ° C. for 15 minutes. With the above, formation of the wiring is completed. 3 (i) is shown in FIG. 3 (h).
3 is a cross-sectional view taken along line XX of FIG.

Here, the wiring formed by the conventional method,
That is, when the wiring surface was not covered with aluminum oxide formed by anodic oxidation, the W film 7 was oxidized and peeled off. However, the wiring formed by the method of this embodiment was good without any abnormality such as increase in resistance or peeling of the interlayer film.

FIG. 4 is a process sectional view for explaining a manufacturing method according to the second embodiment of the present invention.

First, as shown in FIG. 4A, the specific resistance is 6Ω.
・ Plasma C on a p-type (100) Si substrate 21 of cm
A 0.8 μm SiO ₂ film 22 was formed by a VD method at 350 ° C. using a mixed gas of SiH ₄ and N ₂ O, and then a 10 nm TiN film 23 was formed. TiN film 23
Is a Ti target with N ₂ and Ar at a substrate temperature of 200 ° C.
The pressure was set to 5 mTorr in a mixed gas (50% each), and the film was formed by the sputtering method.

[0028] Then, hydrogen by LPCVD (H _2), using a mixed gas of monosilane (SiH ₄₎ and tungsten hexafluoride (WF _6), 0.173T and H ₂
Orr and SiH ₄ are 0.013 Torr, and WF ₆ is 0.
While maintaining each partial pressure of 065 Torr, at a substrate temperature of 420 ° C., a W film (refractory metal film) 24 having a thickness of about 150 nm was formed on the TiN film 23 as shown in FIG. 4B. After that, FIG.
As shown in (c), the W film 24 and the TiN film 23 were selectively etched using ordinary lithography and reactive ion etching (RIE) to process the wiring pattern. After that, an Al film 26 of 2 to 20 nm was selectively formed only on the surface of the W / TiN wiring 25 by the LPCVD method. At this time, Al was deposited at a substrate temperature of 300 ° C., Ar was used as a carrier gas, and TIBA (triisobutylaluminum) was supplied to the reaction tank.

Then, as shown in FIG. 4D, 700 ° C.
The substrate was introduced into a quartz tube furnace set to, and N ₂ gas was used as a carrier gas, TEOS gas was introduced, and the total pressure was 0.8.
Si, which is an interlayer insulating film, is formed by LPCVD at Torr.
An O ₂ film 27 was deposited to a thickness of 0.3 μm. With the above, formation of the wiring is completed. At this time, it was found by Auger electron spectroscopy (AES) analysis that the Al film 26 was partially oxidized to become aluminum oxide (Al ₂ O ₃ ).

Here, the wiring formed by the conventional method,
That is, when the wiring surface is not covered with Al, the W film 24 is oxidized after the interlayer insulating film is formed, and the resistance is increased,
Part of the film was peeled off. However, the wiring formed by the method of this example was good without any abnormality such as increase in resistance or peeling of the interlayer film.

FIGS. 5 and 6 are process sectional views for explaining a manufacturing method according to the third embodiment of the present invention.
An example of the structure is shown.

First, as shown in FIG. 5A, the specific resistance is 5Ω.
-Cm, plane orientation (100) n-type Si substrate 31 100
10 nm SiO ₂ 32 was formed in dry oxygen at 0 ° C. Then, B ⁺ was ion-implanted at 2 × 10 ¹³ cm ⁻² at 1 MeV and heat treatment was performed at 1000 ° C. for 60 minutes to form a p-type well 33 having a boron concentration of about 1 × 10 ¹⁷ cm ⁻³ .

Next, as shown in FIG. 5 (b), channel stop ion implantation was carried out at the portion where the field oxide film is to be formed, and then a field oxide film 34 of 0.6 μm was formed.

Subsequently, after exposing the Si surface layer in the transistor formation region, heat treatment is performed at 1000 ° C. for 30 minutes in Ar in which oxygen and water vapor partial pressures are controlled to 1 ppm or less, and 850 ° C. and 10% HCl are added. A gate oxide film 35 having a thickness of 7 to 10 nm was formed in dry oxygen. After that, a 50 nm polycrystalline Si film 36 was deposited by the LPCVD method using SiH ₄ . Deposition temperature is 620 ° C., SiH ₄
Flow rate is 50-100 sccm, pressure is 0.1 Torr
Then, the deposition rate of Si was 10 to 15 nm / min. N channel MOSFE for the polycrystalline Si film 36
In the T formation region, 1 × 10 As ⁺ ions are applied at 12 keV.
¹⁵ cm ⁻² ions are implanted, and BF ₂ ⁺ ions are implanted into the p-channel MOSFET formation region at 1 × 10 ¹⁵ cm at 10 keV.
^-Ions were implanted. Selective ion implantation was performed using a resist mask.

Next, by LPCVD using Ti (N (CH ₃ ) ₂ ) ₄ , the substrate temperature is 700 to 800 ° C. and 0.01
5 nm of TiN37 was formed under the condition of 0.5 Torr. Then, a W target containing Al was set at 5 mTorr.
Was sputtered in an Ar atmosphere to form a 150 nm W-Al alloy film 38 on the TiN film 37. The Al composition in the alloy film formed at this time is preferably in the range of 1 to 75% (atomic concentration).

Next, as shown in FIG. 5C, a resist pattern having a desired electrode / wiring shape is formed by using an excimer laser lithography technique, and further Cl ₂ / He is formed.
W-Al (1
50 nm) / TiN (5 nm) / As-doped and B-doped polycrystalline Si (50 nm) laminated structures were etched.
Subsequently, the resist was stripped by oxygen plasma ashing, followed by ethylene glycol cleaning, alcohol cleaning, deionized pure water cleaning, and drying in nitrogen. With the remaining thickness of the SiO ₂ film 35 on the source and drain being 3 to 5 nm, As ⁺ ions were implanted into the n-channel MOSFET formation region at 20 keV at 1 × 10 ¹⁴ cm ⁻² to form an implantation layer 39. Ge ⁺ was ion-implanted into the p-channel MOSFET formation region at 10 keV at 1 × 10 ¹⁵ cm ^-2 ,
After amorphizing the surface of the Si substrate, BF ₂ ⁺ ions were implanted at 1 × 10 ¹⁴ cm ⁻² at 20 keV to obtain an implantation layer 4.
Formed 0.

Then, the substrate was set in a vertical furnace capable of reducing the pressure, and the pressure was reduced to 1 × 10 ⁻⁷ Torr, and then 10 l / m of nitrogen was added.
After flowing in to 1 atm and raising the temperature to 800 ° C. within 5 minutes, 200 sccm of hydrogen and 20 sccm of water vapor
It was introduced and oxidized for 30 minutes. By this oxidation step, as shown in FIG. 6D, the aluminum oxide (Al ₂ O ₃ ) film 41 having a thickness of 5 to ₂₀ nm is formed on the surface of the W—Al alloy film 38.
Was formed. Furthermore, the side wall of the polycrystalline Si film 36 has 20
nm oxide film 42 is 18 nm on the source and drain
Oxide film 43 was formed. At this time, N ₂ diluted hydrogen /
Other than steam oxidation, oxidation may be carried out in oxygen diluted with N _{2 at} 600 to 800 ° C. at a pressure of 1 atm or higher.

After that, the substrate was introduced into a quartz tube furnace set at 700 ° C., N ₂ gas was used as a carrier gas, and TE was used.
An SiO ₂ film 44, which is an interlayer insulating film, is applied over the entire surface by an LP gas method at a total pressure of 0.8 Torr by introducing OS gas.
0 nm was deposited.

Then, as shown in FIG. 6 (e), CHF
The SiO ₂ films 43 and 44 is partially removed by reactive ion etching using ₃ and H ₂ gas was selectively by leaving the SiO ₂ film on the side wall portion of the electrode and wiring. At this time the electrode
The aluminum oxide (Al ₂ O ₃ ) film on the wiring was left without being etched. And n-channel MOSF
As ⁺ ions in the ET forming region are 3.5 × at 30 keV
10 ¹⁵ cm ⁻² ions are implanted to form the implantation layer 45, and BF ₂ ⁺ ions are implanted to 20 keV in the p-channel MOSFET formation region.
5 × 10 ¹⁵ cm ^-2 ion implantation is performed to form an implantation layer 46,
0.5 μm S by LPCVD method using TEOS
An iO ₂ film 47 was deposited. After that, a source / drain was formed by performing Ar heat treatment at 1000 ° C. for 30 seconds. After that, NiSi ₂ and CoSi are added to the source / drain.
₂ , TiSi ₂ or the like may be formed. After this step
A MOS-FET is completed by depositing a BPSG film and a plasma SiO ₂ film, opening contact holes and forming wiring.

As described above, by using the method of this embodiment, no film peeling or increase in resistance due to the oxidation of W was observed.

7 and 8 are process cross-sectional views for explaining the manufacturing method according to the fourth embodiment of the present invention.

First, as shown in FIG. 7A, the specific resistance is 6Ω.
・ Plasma CV on p-type (100) Si substrate 51 of cm
By the method D, a mixed gas of SiH ₄ and N ₂ O was used at 350 ° C. to form a 0.8 μm SiO ₂ film 52 and subsequently a 10 nm TiN film 53. The TiN film 53 has a Ti target of N ₂ and Ar at a substrate temperature of 200 ° C.
The pressure was set to 5 mTorr in a mixed gas (50% each), and the film was formed by the sputtering method.

Then, by using a mixed gas of hydrogen (H ₂ ), monosilane (SiH ₄ ) and tungsten hexafluoride (WF ₆ ) by the LPCVD method, H ₂ was added at 0.173 T.
Orr and SiH ₄ are 0.013 Torr, and WF ₆ is 0.
While maintaining each partial pressure of 065 Torr, at a substrate temperature of 420 ° C., a W film (high melting point metal film) 54 of about 150 nm was formed on the TiN film 53 as shown in FIG. 7B. After that, FIG.
As shown in (c), the W film 54 and the TiN film 53 were selectively etched using ordinary lithography and reactive ion etching (RIE) to process the wiring pattern. Then, it was oxidized in dry oxygen at 400 ° C. for 15 minutes. By this oxidation, a tungsten oxide 55 having a thickness of about 10 nm was formed on the W film 54. After that, an Al film 56 of about 20 nm was formed on the entire surface of the substrate. Then, heat treatment was performed for 30 minutes in dry oxygen at 700 ° C. This heat treatment makes Al
At the same time that the film 56 is thermally oxidized from the surface, the tungsten oxide 55 on the W film 54 is reduced by the Al film 56,
Therefore, the Al film 56 in contact with the W film 54 was oxidized. As a result, the Al film 56 was oxidized from the front and back sides as shown in FIG. Here, by oxidizing the surface of the W film 54 before forming the Al film 56, the margin of the conditions for the selective oxidation of the Al film 56 is widened.

Then, as shown in FIG. 8 (e), 700 ° C.
The substrate was introduced into a quartz tube furnace set to, and N ₂ gas was used as a carrier gas, TEOS gas was introduced, and the total pressure was 0.8.
Si is a layer indirect insulation by LPCVD method at Torr
An O ₂ film 58 was deposited to 0.3 μm. With the above, formation of the wiring is completed.

Here, the wiring formed by the conventional method,
That is, when the wiring surface is not covered with Al, the W film 54 is oxidized after the interlayer insulating film is formed, and the resistance is increased,
Part of the film was peeled off. However, the wiring formed by the method of this embodiment was good without any abnormality such as increase in resistance or peeling of the interlayer film.

FIG. 9 is a cross-sectional view showing the steps for explaining the manufacturing method according to the fifth embodiment of the present invention.

First, as shown in FIG. 9A, the specific resistance is 6Ω.
・ Plasma CV on P-type (100) Si substrate 61 of cm
By the method D, a 0.8 μm SiO ₂ film 62 was formed by using a mixed gas of SiH ₄ and N ₂ O at 350 ° C., and then a 10 nm TiN film 63 was formed. The TiN film 63 has a substrate temperature of 200 ° C. and a Ti target of N ₂ and Ar.
The pressure was set to 5 mTorr in a mixed gas (50% each), and the film was formed by the sputtering method.

[0048] Then, hydrogen by LPCVD (H _2), using a mixed gas of monosilane (SiH ₄₎ and tungsten hexafluoride (WF _6), 0.173T and H ₂
Orr and SiH ₄ are 0.013 Torr, and WF ₆ is 0.
While maintaining each partial pressure of 065 Torr, a W film (high melting point metal film) 64 of about 150 nm was formed on the TiN film 63 at a substrate temperature of 420 ° C. as shown in FIG. 9B. After that, FIG.
As shown in (c), the W film 64 and the TiN film 63 were selectively etched using ordinary lithography and reactive ion etching (RIE) to process the wiring pattern.

Then, a W ₂ B ₅ film 65 (metal boride layer) is formed as a protective layer on the surface of the W film 64 by plasma boriding with a gas containing B while the substrate is heated to 400 ° C. to 800 ° C. Formed. The thickness of this boride layer is 1-5
The range of 0 nm is preferable, and the range of 5 to 30 nm is particularly desirable. This boride layer improves the oxidation resistance of W. Further, in the case of boration at 600 ° C. or higher, the surface of TiN becomes TiB ₂ in the portion where the TiN film is exposed, and the oxidation resistance of TiN is improved.

As an example, the boride layer was formed as follows. That is, the sample on which the W film 64 is formed and patterned is set in a vacuum device provided with a parallel plate type high frequency electrode, and 1 × is formed by using a turbo molecular pump.
After reducing the pressure to 10 ⁻⁷ Torr, 100 sccm of diborane (B ₂ H ₆ ) was introduced to adjust the pressure in the vacuum device to 0.33 T.
orr. In this state, high frequency power of 13.56 MHz was applied and plasma was generated for 10 minutes. At this time, the substrate was heated to about 500 ° C. by the ceramic heater. It was confirmed by X-ray photoelectron spectroscopy that a tungsten boride having a composition close to W ₂ B ₅ was formed on the surface of the W film 64 by this diborane (B ₂ H ₆ ) plasma treatment. Here, boron is 10 to 90a in the boride layer.
It is preferably present at tm%.

The above-mentioned plasma boriding is performed under the condition that plasma is stably generated, for example, 0.01 to 0.5 Torr.
It is good to carry out under the pressure of 1 to 30 minutes.

Next, the substrate was introduced into a quartz tube furnace set at 700 ° C., N ₂ gas was used as a carrier gas, and TE was used.
An OS gas was introduced, and SiO ₂ 66 as an interlayer insulating film was deposited to a thickness of 0.3 μm by LPCVD at a total pressure of 0.8 Torr. With the above, formation of the wiring is completed.

Here, the wiring formed by the conventional method,
That is, in the wiring not subjected to the surface boring treatment, the W film 64 is oxidized after the interlayer insulating film is formed, and the resistance is increased,
Part of the film was peeled off. However, the wiring formed by the method of this embodiment was good without any abnormality such as increase in resistance or peeling of the interlayer film.

10 to 12 are process cross-sectional views for explaining the manufacturing method according to the sixth embodiment of the present invention, which show the state of the contact portion between the wiring electrode and the diffusion layer.

First, as shown in FIG. 10A, for example, an n-type impurity such as arsenic is ion-implanted into a desired region on the surface of the p-type silicon substrate 71, and then heat treatment is performed at 900 ° C. for 30 minutes to form an n ⁺ type. The diffusion layer 72 was formed. Then L
After depositing the SiO ₂ film 73 on the entire surface of the substrate 71 by the PCVD method, the SiO ₂ film 73 is selectively removed by the normal photolithography method and the reactive ion etching technology to form a contact hole 74 at a portion corresponding to the diffusion layer 72. Was opened.

Then, as shown in FIG. 10B, a vertical type L
After depositing a 50-nm-thick polycrystalline silicon film 75 on the entire surface of the SiO ₂ film 73 including the contact holes 74 in a PCVD furnace under the condition that oxygen uptake is reduced, the polycrystalline silicon film 75 has a range (Rp). Arsenic ions were implanted at an acceleration voltage of 65 keV so that the distance from the surface was about 40 nm (near the interface between the substrate 71 and the film 75). By this arsenic ion implantation, the diffusion layer 7 is formed in the polycrystalline silicon film 75.
The impurity of the same conductivity type as that of 2 is introduced, and the natural oxide film formed at the interface between the silicon substrate 71 and the polycrystalline silicon film 75 is destroyed by ion mixing, so that the polycrystalline silicon film 75 is good for the diffusion layer 72. Was contacted.

Then, as shown in FIG. 10C, a Ti target is sputtered by a mixed gas of nitrogen and argon (50% each) by a sputter deposition method to form a 50 nm thick TiN film on the polycrystalline silicon film 75. 76 was deposited.

Then, as shown in FIG. 11D, H ₂ ,
A 150 nm-thickness W film 77 was deposited on the TiN film 76 by the LPCVD method using a mixed gas of SiH ₄ and WF ₆ . Here, the gas pressure is H ₂ 0.173 Tor.
r, SiH ₄ 0.013 Torr, WF ₆ 0.06
The partial pressure of 5 Torr was maintained, and the substrate temperature was maintained at 420 ° C. After that, as shown in FIG. 11E, the W film 77, the TiN film 76, and the polycrystalline silicon film 75 are sequentially selectively removed by normal photolithography and reactive ion etching using SF ₆ gas. Crystalline silicon film 7
5, a wiring having a three-layer structure composed of the TiN film 76 and the W film 77 was formed. After that, by rotating ion implantation method in which the substrate is angled at 7 degrees, B ⁺ ions are applied to the entire surface at 20 keV, 2 ×
It was injected at 10 ¹⁶ cm ^-2 . Then, this was set in a vacuum device and 1 × 10 ⁻⁶ To was obtained using a turbo molecular pump.
After reducing the pressure to rr, the oxygen partial pressure was suppressed to 10 ppm or less, Ar or N ₂ was introduced, and heat treatment was performed at 850 ° C. for 30 minutes. As a result, as shown in FIG. 11F, the W film 77
A tungsten boride layer 78 having a composition close to that of W ₂ B ₅ was formed on the surface of.

Then, as shown in FIGS. 12 (g) and 12 (h), the substrate temperature was set to 450 ° C., and monosilane (SiH ₄ ) and oxygen (O ₂ ) diluted with argon (Ar) were used.
An SiO ₂ film 79 as an interlayer insulating film was deposited to 0.5 μm on the wiring by atmospheric pressure chemical vapor deposition (APCVD) using the mixed gas of. With the above, formation of the wiring is completed. 12 (h) is a sectional view taken along the line XX 'in FIG. 12 (g).

The wiring thus formed was good without any abnormality such as increase in resistance or peeling of the interlayer film.

13 and 14 are process sectional views for explaining the manufacturing method according to the seventh embodiment of the present invention.
An example of an OS structure is shown.

First, as shown in FIG. 13A, the specific resistance 5
10 on the n-type Si substrate 81 with Ω · cm and plane orientation (100)
10 nm SiO ₂ 82 was formed in dry oxygen at 00 ° C. Then, 2 × 10 ¹³ cm ^{-2 of} B ⁺ was ion-implanted and heat treatment was performed at 1000 ° C. for 60 minutes to form a p-type well 83 having a boron concentration of about 1 × 10 ¹⁷ cm ⁻³ .

Next, as shown in FIG. 13 (b), channel stop ion implantation was carried out in the portion where the field oxide film is to be formed, and then a field oxide film 84 of 0.6 μm was formed.

Subsequently, after exposing the Si surface layer in the transistor formation region, heat treatment is performed at 1000 ° C. for 30 minutes in Ar whose oxygen and water vapor partial pressures are controlled to 1 ppm or less, and further 850 ° C. and 10% HCl are added. A gate oxide film 85 having a thickness of 7 to 10 nm was formed in dry oxygen. Then, a 50 nm polycrystalline Si film 86 was deposited by the LPCVD method using SiH ₄ . Deposition temperature is 620 ° C., SiH ₄
Flow rate is 50-100 sccm, pressure is 0.1 Torr
Then, the deposition rate of Si was 10 to 15 nm / min. N-channel MOSFE for the polycrystalline Si film 86
In the T formation region, 1 × 10 As ⁺ ions are applied at 12 keV.
¹⁵ cm ⁻² ions are implanted, and BF ₂ ⁺ ions are implanted into the p-channel MOSFET formation region at 1 × 10 ¹⁵ cm at 10 keV.
^-Ions were implanted. Selective ion implantation was performed using a resist mask.

Then, the sample in this state is set in a vacuum apparatus, and the inside of the vacuum apparatus is depressurized to 1 × 10 ⁻⁸ Torr using a turbo molecular pump having an exhaust capacity of 500 l / sec, and then halogen is applied to the substrate surface. The lamp was irradiated to raise the temperature of the Si substrate to a temperature of 450 to 700 ° C. 1 minute later, N
H ₃ , WF ₆ , H ₂ and Ar are each 100 sccm, 4
Flowing at 00 sccm, 500 sccm, and 500 sccm, the total pressure was controlled to 0.2 Torr using a throttle valve. A 20 nm W ₂ N film 87 is formed with a deposition time of 100 seconds, and then H ₂ , SiH ₄ and WF are formed.
0.173 Torr, 0.0 using mixed gas of ₆ respectively
Hold at 13 Torr, 0.065 Torr pressure, 450
100 nm W film 8 on W ₂ N film 87 at substrate temperature of ℃
8 was formed.

Next, as shown in FIG. 13C, a resist pattern having a desired electrode / wiring shape is formed by using an excimer laser lithography technique, and further Cl ₂ / H is used.
W (100
nm) / W ₂ N (20 nm) / As-doped and B-doped polycrystalline Si (50 nm) laminated structure was etched. Subsequently, the resist was stripped by oxygen plasma ashing, followed by ethylene glycol cleaning, alcohol cleaning, deionized pure water cleaning, and drying in nitrogen. With the remaining thickness of the SiO ₂ film 85 on the source and drain being 3 to 5 nm, 1 × 10 ¹⁴ cm ⁻² ions of As ⁺ ions were implanted into the n-channel MOSFET formation region at 20 keV to form an implantation layer 89. Ge ⁺ was ion-implanted into the p-channel MOSFET formation region at 10 keV at 1 × 10 ¹⁵ cm ^-2 ,
After amorphizing the surface of the Si substrate, BF ₂ ⁺ ions are implanted at 1 × 10 ¹⁴ cm ⁻² at 20 keV to obtain an implantation layer 9
0 was formed and heat treatment was performed in nitrogen at 850 ° C. for 30 minutes.

Then, the Si substrate was placed in a vacuum chamber and the pressure was reduced to 1 × 10 ⁻⁷ Torr using a turbo molecular pump.
The substrate was heated to 500 ° C. using a lamp and 1 minute later, 100 to 500 sccm of diborane (B ₂ H ₆ ) gas was introduced, and the throttle valve was set to 1 × 10 ⁻² Torr to obtain 2.45 GHz. Microwave (power: 500
W to 1 kW) was applied. About 15 to 20 nm of W is formed on the surface of the W film 88 by diborane plasma boration for 10 minutes.
_{A 2} B ₅ film 91 was formed.

Next, the substrate was set in a vertical furnace capable of reducing the pressure, and the pressure was reduced to 1 × 10 ⁻⁷ Torr, and then 10 l / m of nitrogen was added.
After flowing in to 1 atm and raising the temperature to 800 ° C. within 5 minutes, 200 sccm of hydrogen and 20 sccm of water vapor
It was introduced and oxidized for 30 minutes. As a result of this oxidation step, as shown in FIG.
Oxide film 92 of 0 nm has a thickness of 18n on the source and drain.
m oxide film 93 was formed. At this time, in addition to N ₂ diluted hydrogen / steam oxidation, post-oxidation may be performed by plasma oxidation using oxygen radicals at a pressure of 1 atm or higher in N ₂ diluted oxygen at 600 to 800 ° C. Further, a method such as anodic oxidation may be used. After that, the substrate temperature is set to 450 ° C., and the SiO ₂ film 94 is formed on the entire surface by AP (normal pressure) CVD method using SiH ₄ and O ₂ mixed gas diluted with Ar.
Was deposited to 200 nm.

Then, as shown in FIG. 14 (e), CH
The SiO ₂ film 93 and 94 is partially removed by reactive ion etching using F ₃ and H ₂ gas was selectively by leaving the SiO ₂ film on the side wall portion of the electrode and wiring. Subsequently, the Si substrate was placed in a vacuum chamber and a turbo molecular pump was used for 1 × 10 5.
^The pressure was reduced to ^-7 Torr. After that, the lamp is used to
One minute after heating to 00 ° C., diborane (B ₂ H ₆ ) gas was introduced at 100 to 500 sccm, and a throttle valve was used to set the pressure to 1 × 10 ⁻² Torr, and then microwave of 2.45 GHz (power: 500 W ~ 1 kW) was added. 1
By boring for 0 minutes, the thickness of the W ₂ B ₅ film 91 on the surface of the W film 88 was set to 20 nm again. And n channel MO
2. As ⁺ ions in the SFET formation region at 30 keV.
5 × 10 ¹⁵ cm ⁻² ions are implanted to form an implantation layer 95, and BF ₂ ⁺ ions are implanted into the p-channel MOSFET formation region to 20 times.
An ion implantation layer 96 was formed by ion implantation of 5 × 10 ¹⁵ cm ^{−2 with} keV, and a 0.5 μm SiO ₂ film 97 was deposited by the APCVD method. After that, a source / drain was formed by performing Ar heat treatment at 1000 ° C. for 30 seconds.
After that, NiSi ₂ , CoSi ₂ , T
iSi ₂ or the like may be formed. After this step, BPS
A MOSFET is completed by depositing a G film and a plasma SiO ₂ film, opening contact holes and forming wiring.

As described above, by using the method of this embodiment, no film peeling or resistance increase due to the oxidation of W was observed.

FIG. 15 shows the results of measuring the sheet resistance of the three-layer gate electrode made of W / W ₂ N / impurity-doped polycrystalline silicon formed by the method according to the seventh embodiment shown in FIGS. 13 and 14. Indicates. W ₂ formed on the surface of the W film 88
When the sheet resistance is plotted against the thickness of the B ₅ film 91, the sheet resistance is greatly reduced when W ₂ B ₅ is present on the surface, and a value of 0.7 to 0.8 Ω / □ is obtained at 5 to 40 nm. Was given. When W ₂ B ₅ was not present on the surface, that is, when surface boride was not formed, a remarkable increase in resistance of two orders of magnitude or more was observed, and a large amount of W oxide was locally grown on the surface of the W wiring. From this, it is understood that the effect of improving the oxidation resistance of boride on the W surface is great. Although the W / W ₂ N / Si structure has been described in this embodiment, W / TiN /
Similar effects were obtained for the Si structure.

When TiN was used, no mutual reaction was observed between W and polycrystalline Si even through the heating process at a temperature higher than that used in this example. When TiN is used, LPCVD-TiN
Membranes are effective. Typical film forming conditions are Ti (N (CH
₃ ) ₂ ) ₄ LPCVD using substrate temperature 700 ~ 8
The conditions are 00 ° C. and 0.01 to 0.5 Torr, and 5 to
A deposition rate of about 20 nm is obtained.

In each of the above-described embodiments, W is used as the refractory metal film, but the same effect can be obtained with a film of Mo or the like.

[0074]

According to the present invention, in a method of manufacturing a semiconductor device having a structure in which an electrode wiring layer including a refractory metal layer is provided, the exposed surface of the wiring layer is covered with the film according to the present invention after the wiring is formed. With the structure, the metal layer can be prevented from being oxidized when heat treatment, oxidation treatment, or insulating film deposition treatment is performed as a subsequent step. Therefore, it is possible to eliminate defects such as increased resistance and film peeling,
Along with the throughput, the reliability and the manufacturing yield can be greatly improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the invention in the order of steps.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps subsequent to FIG.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps subsequent to FIG.

4A to 4C are cross-sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the invention in the order of steps.

FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps subsequent to FIG. 5;

FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps subsequent to FIG. 7;

FIG. 9 is a sectional view showing a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view showing a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention in the order of steps.

FIG. 11 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the sixth exemplary embodiment of the present invention in the order of steps subsequent to FIG. 10;

FIG. 12 is a sectional view showing the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention in the order of steps subsequent to FIG.

FIG. 13 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the seventh embodiment of the present invention in the order of steps.

FIG. 14 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the seventh embodiment of the present invention in the order of steps subsequent to FIG.

FIG. 15 shows W / W ₂ N / polycrystalline silicon wiring resistance (shown by sheet resistance) and W ₂ B on the W surface in the seventh embodiment.
₅ is a characteristic diagram showing the relationship with the film thickness.

[Explanation of symbols]

1, 21, 31, 51, 61, 71, 81 ... Si substrate,
3, 23, 35, 52, 62, 73, ... SiO ₂ film,
5, 36, 75, 86 ... Si film, 6, 23, 37, 5
3, 63, 76, ... TiN film, 7, 24, 54, 64,
77, 88 ... W film, 8, 26, 56 ... Al film, 9, 4
1, 57 ... Al ₂ O ₃ film, 38 ... W-Al alloy film, 6
_5, 78, 91 ... W ₂ B ₅ film, 87 ... W ₂ N.

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, comprising forming an electrode wiring layer prior to heat treatment, oxidation treatment, or insulator deposition treatment, the method comprising the step of forming a refractory metal as a material for electrode wiring on a semiconductor substrate. A step of forming a layer, a step of selectively etching the refractory metal layer to form a patterned electrode wiring layer, a step of covering the electrode wiring layer with an aluminum film, the aluminum film, Oxidizing at a temperature lower than the temperature at which the refractory metal and aluminum are alloyed with each other, and converting the aluminum oxide film. 2. A method for manufacturing a semiconductor device, which comprises forming an electrode wiring layer prior to heat treatment, oxidation treatment, or insulator deposition treatment, the method comprising forming a high melting point metal as a material for electrode wiring on a semiconductor substrate. A step of forming a layer, a step of selectively etching the refractory metal layer to form a patterned electrode wiring layer, a step of selectively growing an aluminum film on the electrode wiring layer, and forming the electrode wiring layer Coating with an aluminum film. 3. A method for manufacturing a semiconductor device, which is a method of forming an electrode wiring layer prior to heat treatment, oxidation treatment, or insulator deposition treatment, comprising a refractory metal serving as a material for electrode wiring on a semiconductor substrate. A step of forming a layer made of an alloy with aluminum, a step of selectively etching the alloy layer to form an electrode wiring pattern, and an electrode whose surface is covered with an aluminum oxide film by oxidizing the electrode wiring pattern. And a step of forming a wiring layer. 4. A method for manufacturing a semiconductor device, which is a method of forming an electrode wiring layer prior to heat treatment, oxidation treatment, or insulator deposition treatment, the refractory metal being a material for electrode wiring on a semiconductor substrate. A step of forming a layer, a step of selectively etching the refractory metal layer to form a patterned electrode wiring layer, a step of boring the surface of the electrode wiring layer, and forming the electrode wiring layer by the refractory metal. And boride coating.