KR20040001872A - Method for forming contact in semiconductor device using tungsten layer - Google Patents
Method for forming contact in semiconductor device using tungsten layer Download PDFInfo
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- KR20040001872A KR20040001872A KR1020020037206A KR20020037206A KR20040001872A KR 20040001872 A KR20040001872 A KR 20040001872A KR 1020020037206 A KR1020020037206 A KR 1020020037206A KR 20020037206 A KR20020037206 A KR 20020037206A KR 20040001872 A KR20040001872 A KR 20040001872A
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- vapor deposition
- tungsten film
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- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 94
- 239000010937 tungsten Substances 0.000 title claims abstract description 94
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 93
- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000007789 gas Substances 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 23
- 238000005229 chemical vapour deposition Methods 0.000 claims description 19
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 11
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 239000002313 adhesive film Substances 0.000 claims description 4
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052786 argon Inorganic materials 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 230000006911 nucleation Effects 0.000 description 6
- 238000010899 nucleation Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 150000003608 titanium Chemical class 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 콘택 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a contact forming method.
최근에 반도체소자의 집적화가 급격하게 이루어지면서 데이터라인과 비트라인 등의 금속배선공정의 중요성은 더욱 부각되고 있으며, 이러한 금속배선 공정을 적용하면서 원하는 소자 특성을 얻기 위해 여러가지 공정들이 적용되고 있다. 특히, 데이터라인과 비트라인 공정의 경우 구현하고자 하는 소자의 특성을 고려할 때 필요한 전기적인 특성값을 확보하기는 더욱 어려운 실정이다.Recently, as the integration of semiconductor devices has been rapidly made, the importance of metal wiring processes such as data lines and bit lines has become more important, and various processes have been applied to obtain desired device characteristics while applying such metal wiring processes. In particular, in the case of the data line and the bit line process, it is more difficult to secure the electrical characteristic values necessary when considering the characteristics of the device to be implemented.
64M 이하의 소자에서의 비트라인의 경우에는 소자의 속도 측면과 다량의 칩 확보측면에서 그다지 어려운 공정은 아니지만, 128M 이상의 고집적 소자에서는 한정된 웨이퍼에서 보다 많은 칩수를 확보하기 위함과 동시에 고성능의 소자를 구현하기 위해 텅스텐실리사이드 공정보다는 낮은 비저항값을 갖는 텅스텐 공정을 적용하고 있다.In the case of the bit line in the device of 64M or less, it is not a difficult process in terms of the speed of the device and the securing of a large amount of chips. To this end, a tungsten process having a lower resistivity value is used rather than a tungsten silicide process.
도 1a 내지 도 1c는 종래기술에 따른 반도체소자의 콘택 형성 방법을 도시한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the related art.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 층간절연막(12)을 형성한 후, 콘택을 정의하는 마스크(13)를 식각마스크로 층간절연막(12)을 식각하여 반도체기판(11)을 노출시키는 콘택홀(14)을 형성한다.As shown in FIG. 1A, after forming the interlayer insulating film 12 on the semiconductor substrate 11, the interlayer insulating film 12 is etched using the mask 13 defining the contact as an etch mask. A contact hole 14 exposing the gap is formed.
도 1b에 도시된 바와 같이, 마스크(13)를 제거한 후, 콘택홀(14)을 포함한 전면에 배리어막(15)을 증착한 후, 배리어막(15)상에 콘택홀(14)을 채울때까지 화학기상증착법(Chemical Vapor Deposition; CVD)을 이용하여 텅스텐막(16)을 증착한다. 이때, 배리어막(15)으로는 티타늄막과 티타늄나이트라이드막의 적층구조를 이용하고, 텅스텐막(16)의 화학기상증착시 소스가스로는 육불화텅스텐(WF6) 가스를 이용한다.As shown in FIG. 1B, after removing the mask 13, depositing the barrier film 15 on the entire surface including the contact hole 14, and then filling the contact hole 14 on the barrier film 15. Until then, the tungsten film 16 is deposited using chemical vapor deposition (CVD). At this time, the barrier film 15 uses a laminated structure of a titanium film and a titanium nitride film, and a tungsten hexafluoride (WF 6 ) gas is used as a source gas during chemical vapor deposition of the tungsten film 16.
다음으로, 텅스텐막(16)상에 금속배선을 정의하는 마스크를 형성한 후, 마스크를 식각마스크로 텅스텐막(16)과 배리어막(15)을 순차적으로 식각하여 금속배선 공정을 완료한다.Next, after forming a mask defining metal wiring on the tungsten film 16, the metal wiring process is completed by sequentially etching the tungsten film 16 and the barrier film 15 using the mask as an etching mask.
후속 공정으로, 도 1c에 도시된 바와 같이, 층간절연막(12)의 표면이 드러날때까지 화학적기계적연마 또는 에치백하여 콘택홀(14)내에만 배리어막(15a)과 텅스텐막(16a)을 잔류시킨다. 이때, 잔류하는 텅스텐막(16a)을 텅스텐플러그(16a)라 한다.Subsequently, as shown in FIG. 1C, the barrier film 15a and the tungsten film 16a remain only in the contact hole 14 by chemical mechanical polishing or etching back until the surface of the interlayer insulating film 12 is exposed. Let's do it. At this time, the remaining tungsten film 16a is referred to as tungsten plug 16a.
다음으로, 텅스텐플러그(16a)상에 접착막으로서 티타늄나이트라이드막(17)을 증착하고, 티타늄나이트라이드막(17)상에 텅스텐막(18)을 증착한다. 그리고, 텅스텐막(18)과 티타늄나이트라이드막(17)을 패터닝하여 텅스텐막(18)으로 이루어진 금속배선을 형성한다.Next, a titanium nitride film 17 is deposited on the tungsten plug 16a as an adhesive film, and a tungsten film 18 is deposited on the titanium nitride film 17. Then, the tungsten film 18 and the titanium nitride film 17 are patterned to form a metal wiring made of the tungsten film 18.
그러나, 상술한 종래기술은 후속 고온 열처리 공정을 거치면 배리어막의 능력저하 및 불순물 침투에 의해 전기적인 특성이 악화되는 문제가 있다. 즉, 후속 열처리공정을 거치면서 텅스텐막 증착시 사용하는 육불화텅스텐(WF6) 가스의 불소(F)가 배리어막을 뚫고 확산되면서 배리어막의 배리어능력을 저하시킨다.However, the above-described prior art has a problem in that the electrical characteristics are deteriorated due to the degradation of the barrier film and the impurity penetration through the subsequent high temperature heat treatment process. That is, the fluorine (F) of the tungsten hexafluoride (WF 6 ) gas used in the deposition of the tungsten film during the subsequent heat treatment process is diffused through the barrier film, thereby lowering the barrier capability of the barrier film.
특히, 채우고자 하는 콘택홀의 디멘젼(dimension)이 더욱 작아짐에 따라 콘택홀에 텅스텐막을 완전히 채우는 것이 어렵고, 이로써 만족할만한 전기적인 특성을 확보하기가 어렵다.In particular, as the dimension of the contact hole to be filled becomes smaller, it is difficult to completely fill the tungsten film in the contact hole, thereby making it difficult to secure satisfactory electrical characteristics.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로, 화학기상증착법을 이용한 텅스텐플러그 형성시 육불화텅스텐가스에 의한 배리어막의 배리어특성 저하를 방지하는데 적합한 반도체소자의 콘택 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and provides a method for forming a contact of a semiconductor device suitable for preventing the barrier properties of the barrier film caused by tungsten hexafluoride gas when forming tungsten plugs using chemical vapor deposition. The purpose is.
도 1a 내지 도 1c는 종래기술에 따른 반도체소자의 콘택 형성 방법을 도시한 공정 단면도,1A to 1C are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the prior art;
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체소자의 콘택 형성 방법을 도시한 공정 단면도,2A to 2E are cross-sectional views illustrating a method of forming a contact in a semiconductor device according to an embodiment of the present invention;
도 3은 본 발명의 텅스텐막의 물리기상증착법을 위한 챔버를 도시한 도면.3 is a view showing a chamber for physical vapor deposition of the tungsten film of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 층간절연막21 semiconductor substrate 22 interlayer insulating film
24 : 콘택홀 25 : 배리어막24 contact hole 25 barrier film
26 : 제1 텅스텐막 27 : 제2 텅스텐막26: first tungsten film 27: second tungsten film
28 : 티타늄나이트라이드막 29 : 제3 텅스텐막28: titanium nitride film 29: third tungsten film
상기 목적을 달성하기 위한 본 발명의 반도체소자의 콘택 형성 방법은 반도체기판상에 층간절연막을 형성하는 단계, 상기 층간절연막을 관통하여 상기 반도체기판에 이르는 콘택홀을 형성하는 단계, 상기 콘택홀을 포함한 상기 층간절연막상에 배리어막을 형성하는 단계, 상기 배리어막상에 물리기상증착법을 통해 제1 텅스텐막을 증착하는 단계, 상기 콘택홀을 채울때까지 상기 제1 텅스텐막상에 화학기상증착법으로 제2 텅스텐막을 증착하는 단계, 및 상기 콘택홀내에만 잔류하는 텅스텐플러그를 형성하는 단계를 포함함을 특징으로 하고, 상기 텅스텐플러그를 형성한 후, 상기 텅스텐플러그상에 접착막을 증착하는 단계, 및 상기 접착막상에 물리기상증착법으로 제3 텅스텐막을 증착하는 단계를 더 포함함을 특징으로 한다.A method of forming a contact of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate, forming a contact hole through the interlayer insulating film to the semiconductor substrate, including the contact hole Forming a barrier film on the interlayer insulating film; depositing a first tungsten film on the barrier film by physical vapor deposition; depositing a second tungsten film on the first tungsten film by chemical vapor deposition until the contact hole is filled And forming a tungsten plug remaining only in the contact hole, and after forming the tungsten plug, depositing an adhesive film on the tungsten plug, and physically forming on the adhesive film. And depositing a third tungsten film by vapor deposition.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체소자의 콘택 형성 방법을 도시한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 층간절연막(22)을 형성한 후, 콘택을 정의하는 마스크(23)를 식각마스크로 층간절연막(22)을 식각하여 반도체기판(21)을 노출시키는 콘택홀(24)을 형성한다.As shown in FIG. 2A, after forming the interlayer dielectric layer 22 on the semiconductor substrate 21, the interlayer dielectric layer 22 is etched using the mask 23 defining the contact as an etch mask. A contact hole 24 is formed to expose the gap.
도 2b에 도시된 바와 같이, 마스크(23)를 제거한 후, 콘택홀(24)내 반도체기판(21) 표면에 생성된 자연산화막(native oxide)이나 불순물을 전세정(pre-cleaning) 과정을 통해 제거한다.As shown in FIG. 2B, after removing the mask 23, the native oxide or impurities generated on the surface of the semiconductor substrate 21 in the contact hole 24 may be pre-cleaned. Remove
이때, 전세정 과정은 200:1로 희석된 BOE(Buffered Oxide Etchant)를 30초∼100초동안 진행한다. BOE는 H2SO4:H2O2이 50:1인 조건이다.At this time, the pre-cleaning process is performed BOE (Buffered Oxide Etchant) diluted to 200: 1 for 30 seconds to 100 seconds. BOE is a condition wherein H 2 SO 4 : H 2 O 2 is 50: 1.
다음으로, 콘택홀(24)을 포함한 전면에 공지된 기술을 이용하여 배리어막(25)을 형성하되, 티타늄막과 티타늄나이트라이드막의 적층구조로 이루어진 배리어막(25)을 형성한다.Next, the barrier film 25 is formed on the front surface including the contact hole 24 using a known technique, and the barrier film 25 having a laminated structure of a titanium film and a titanium nitride film is formed.
이때, 도면에 도시되지 않았지만, 배리어막(25)의 형성 방법은, 먼저 티타늄막을 물리기상증착법 또는 화학기상증착법으로 50Å∼200Å 두께로 증착한 후, 700℃∼900℃의 급속열처리과정을 진행하여 티타늄실리사이드막을 형성하고, 전면에 티타늄나이트라이막을 100Å∼500Å 두께로 증착한다.At this time, although not shown in the drawing, the barrier film 25 is formed by first depositing a titanium film with a thickness of 50 kPa to 200 kPa by physical vapor deposition or chemical vapor deposition, and then proceeding with rapid thermal treatment at 700 ° C to 900 ° C. A titanium silicide film is formed, and a titanium nitride film is deposited on the entire surface in a thickness of 100 kV to 500 kV.
다음으로, 배리어막(25)상에 물리기상증착법을 이용하여 제1 텅스텐막(26)을 50Å∼500Å의 얇은 두께로 증착한다.Next, on the barrier film 25, the first tungsten film 26 is deposited to a thin thickness of 50 kV to 500 kV using physical vapor deposition.
도 3은 물리기상증착법을 이용한 제1 텅스텐막 증착의 실시예를 설명하기 위한 챔버를 도시하고 있다.3 shows a chamber for explaining an embodiment of first tungsten film deposition using physical vapor deposition.
도 3을 참조하면, 물리적기상증착 챔버는 반응성 증착 챔버(100)로서, 반응성 증착챔버(100)내에 기판지지대(102)에 의해 지지된 텅스텐막 증착될 웨이퍼(101), 웨이퍼(101)에 대향하는 위치에 타겟지지대(103)에 의해 지지된 텅스텐타겟(104), 반응성 증착 챔버(100)내에 스퍼터가스인 아르곤가스를 공급하기 위한 아르곤가스공급관(105)으로 이루어진다.Referring to FIG. 3, the physical vapor deposition chamber is a reactive deposition chamber 100, which is opposed to a wafer 101 and a wafer 101 to be deposited by a tungsten film supported by a substrate support 102 in the reactive deposition chamber 100. It consists of a tungsten target 104 supported by the target support 103 at a position, and an argon gas supply pipe 105 for supplying argon gas, which is a sputter gas, into the reactive deposition chamber 100.
여기서, 아르곤가스공급관(106)을 통해 아르곤과 같은 비활성가스가 공급되고, 아르곤가스는 밸브(도시 생략)를 통해 그 공급량 및 공급시간이 조절된다.Here, an inert gas such as argon is supplied through the argon gas supply pipe 106, and the supply amount and supply time of the argon gas are adjusted through a valve (not shown).
또한, 웨이퍼(101)의 표면이 텅스텐타겟(104)에 평행하게 일정한 간격을 유지하도록 웨이퍼(101)는 기판지지대(102)에 장착된다.In addition, the wafer 101 is mounted on the substrate support 102 so that the surface of the wafer 101 maintains a constant gap parallel to the tungsten target 104.
상술한 도 2에서 이루어지는 텅스텐막의 증착은, 먼저 300W∼1500W의 파워가 인가된 0.1mtorr∼10mtorr의 진공상태에서 반응성 증착챔버(100)내의 텅스텐타겟(104)과 웨이퍼(101) 사이에 아르곤가스를 공급한 다음, 아르곤가스를 이온화시켜 아르곤 플라즈마를 형성하고, 플라즈마를 구성하는 Ar+ 이온들을 텅스텐 타겟(104)으로 전기장에 의해 가속시켜 텅스텐타겟(104)의 표면과 충돌시킨다.In the above-described deposition of the tungsten film in FIG. 2, argon gas is first deposited between the tungsten target 104 and the wafer 101 in the reactive deposition chamber 100 in a vacuum of 0.1 mtorr to 10 mtorr applied with 300 W to 1500 W of power. After supplying, argon gas is ionized to form an argon plasma, and Ar + ions constituting the plasma are accelerated by an electric field to the tungsten target 104 to collide with the surface of the tungsten target 104.
이러한 충돌에 의한 운동량의 교환에 의하여 텅스텐타겟(104)의 표면 원자나 분자가 튀어나오고, 튀어나온 원자나 분자들(W+)은 웨이퍼(101)상에 텅스텐막(106)을 증착시킨다.The surface atoms or molecules of the tungsten target 104 come out by the exchange of momentum due to such collision, and the protruding atoms or molecules W + deposit the tungsten film 106 on the wafer 101.
도 2c에 도시된 바와 같이, 제1 텅스텐막(26)상에 화학기상증착법(CVD)을 이용한 제2 텅스텐막(27)을 증착하되, 콘택홀을 완전히 채울때까지 증착한다. 이때, 제2 텅스텐막(27)은 500Å∼5000Å 두께로 증착한다.As shown in FIG. 2C, a second tungsten film 27 using chemical vapor deposition (CVD) is deposited on the first tungsten film 26, until the contact hole is completely filled. At this time, the second tungsten film 27 is deposited to a thickness of 500 kPa to 5000 kPa.
여기서, 제2 텅스텐막(27)의 화학기상증착법은, 수소(H2) 환원법, 실란(SiH4) 환원법, 디클로로실란(SiH2C12) 환원법 등을 이용한다.As the chemical vapor deposition method of the second tungsten film 27, a hydrogen (H 2 ) reduction method, a silane (SiH 4 ) reduction method, a dichlorosilane (SiH 2 C1 2 ) reduction method, or the like is used.
먼저, 디클로로실란(SiH2C12) 환원법은 반도체기판을 화학기상증착챔버내로 장입시킨 후, 챔버내에 원료가스로서 육불화텅스텐(WF6)가스와 환원가스로서 디클로로실란을 사용하여 600℃ 정도의 고온하에서 텅스텐막을 형성한다.First, the dichlorosilane (SiH 2 C1 2 ) reduction method loads a semiconductor substrate into a chemical vapor deposition chamber, and then uses tungsten hexafluoride (WF 6 ) gas as a raw material gas and dichlorosilane as a reducing gas. A tungsten film is formed under high temperature.
두번째, 실란(SiH4)환원법은, 반도체기판을 화학기상증착챔버내로 장입시킨 후, 챔버내에 원료가스로서 육불화텅스텐(WF6)가스와 환원가스로서 실란을 사용하여 450℃ 정도의 저온하에서 텅스텐막을 형성한다.Secondly, the silane (SiH 4 ) reduction method loads a semiconductor substrate into a chemical vapor deposition chamber, and then uses tungsten hexafluoride (WF 6 ) gas as a raw material gas and silane as a reducing gas to form tungsten at a low temperature of about 450 ° C. To form a film.
마지막으로, 수소(H2) 환원법은, 반도체기판을 화학기상증착챔버내로 장입시킨 후, 챔버내에 원료가스로서 육불화텅스텐(WF6)가스와 환원가스로서 수소를 사용하여 400∼450℃ 정도의 온도하에서 텅스텐막을 형성한다.Finally, the hydrogen (H 2 ) reduction method inserts a semiconductor substrate into a chemical vapor deposition chamber, and then uses a tungsten hexafluoride (WF 6 ) gas as a raw material gas and hydrogen as a reducing gas, thereby reducing the temperature to about 400 to 450 ° C. A tungsten film is formed under temperature.
상술한 제2 텅스텐막(27)의 화학기상증착시, 모두 원료가스로서 육불화텅스텐(WF6)가스가 사용됨에 따라 배리어막(25)상에 바로 막형성을 행하려고 하면 막의 접착이 나쁘고, 막의 접착이 생기지 않는 인큐베이션 타임(incubation time)이 길어지는 경향이 있다.In the chemical vapor deposition of the above-mentioned second tungsten film 27, since all tungsten hexafluoride (WF 6 ) gas is used as the source gas, if the film is formed directly on the barrier film 25, the adhesion of the film is poor. There is a tendency for an incubation time to occur in which the adhesion of the membrane does not occur.
따라서, 전술한 제1 텅스텐막(25)을 핵생성막으로 하여 제2 텅스텐막(26)을 증착하면, 제2 텅스텐막 증착시 핵생성막 증착공정을 생략할 수 있다.Therefore, when the second tungsten film 26 is deposited using the above-described first tungsten film 25 as the nucleation film, the nucleation film deposition process may be omitted when the second tungsten film is deposited.
전술한 바와 같이, 배리어막(25)상에 증착되는 제1 텅스텐막(26)을 물리기상증착법으로 증착하기 때문에 챔버내의 타겟으로부터 떨어져 나온 텅스텐 입자가 배리어막(25)상에 증착하게 되어 육불화텅스텐가스로부터 배리어막(25)의 노출을 원천적으로 방지하고, 화학기상증착법을 이용할 경우 필연적으로 첨가되는 핵생성막의 증착도 필요없게 되므로 공정 안정성면에서 유리하다.As described above, since the first tungsten film 26 deposited on the barrier film 25 is deposited by physical vapor deposition, tungsten particles separated from the target in the chamber are deposited on the barrier film 25 to be hexafluoride. Exposure of the barrier film 25 from tungsten gas is fundamentally prevented, and chemical vapor deposition is advantageous in terms of process stability since the deposition of a nucleation film that is inevitably added is unnecessary.
결국, 물리기상증착법으로 증착된 제1 텅스텐막(26)의 경우, 막내에 불소와 같은 불순물을 전혀 함유하고 있지 않을뿐만 아니라 후속 화학기상증착법으로 증착된 제2 텅스텐막(27)에 대한 핵생성막 역할을 하므로 콘택홀을 채우지 못해서 발생할 수 있는 불량도 미연에 방지한다.As a result, the first tungsten film 26 deposited by physical vapor deposition does not contain any impurities such as fluorine in the film but also nucleates the second tungsten film 27 deposited by subsequent chemical vapor deposition. It also acts as a membrane to prevent defects that could be caused by not filling the contact holes.
비록 물리기상증착법으로 제1 텅스텐막(26)을 증착할 경우, 소자가 축속화되어 채우고자 하는 콘택안으로 증착이 용이하지 않을 수 있지만, 이 문제는 제1 텅스텐막(26) 증착공정의 공정조건을 저전압과 저압 조건으로 진행하여 원하는 핵생성막 역할을 충분히 해낼수 있다.Although the first tungsten film 26 is deposited by physical vapor deposition, the device may be condensed and not easily deposited into the contact to be filled. However, this problem is a process condition of the first tungsten film 26 deposition process. Proceed to the low voltage and low pressure conditions to fully serve the desired nucleation film.
도 2d에 도시된 바와 같이, 층간절연막(22)의 표면이 드러날때까지 화학적기계적연마 또는 에치백하여 콘택홀(24)내에만 배리어막과 제1,2 텅스텐막을 잔류시킨다. 이하, 잔류하는 배리어막, 제1,2 텅스텐막을 각각 도면부호 25a, 26a,27a라 하고, 특히 제1 텅스텐막(26a)과 제2 텅스텐막(27a)을 통틀어서 텅스텐 플러그 또는 텅스텐 콘택플러그라 한다. 이러한 텅스텐 플러그 또는 텅스텐콘택플러그는 후속 금속배선 또는 비트라인과 연결될 콘택이다.As shown in FIG. 2D, the barrier film and the first and second tungsten films are left only in the contact hole 24 by chemical mechanical polishing or etching back until the surface of the interlayer insulating film 22 is exposed. Hereinafter, the remaining barrier film and the first and second tungsten films are referred to as 25a, 26a, and 27a, respectively, and in particular, the first tungsten film 26a and the second tungsten film 27a are referred to as tungsten plugs or tungsten contact plugs. . This tungsten plug or tungsten contact plug is a contact to be connected with a subsequent metallization or bit line.
한편, 에치백 공정은 화학적기계적연마 공정보다 비용이 싼 것으로 알려져 있다.On the other hand, the etch back process is known to be cheaper than the chemical mechanical polishing process.
전술한 바와 같이, 화학적기계적연마 공정을 수행하므로써 비록 얇은 두께의 텅스텐막을 증착한 경우라 하더라도 표면거칠기가 나빠지는 것을 방지한다.As described above, by performing the chemical mechanical polishing process, even if a thin tungsten film is deposited, surface roughness is prevented from deteriorating.
도 2e에 도시된 바와 같이, 전면에 접착막(glue layer)인 티타늄나이트라이드막(28)을 물리기상증착법을 통해 50Å∼500Å의 두께로 증착한 후, 티타늄나이트라이드막(28)상에 비트라인 또는 금속배선막인 제3 텅스텐막(29)을 물리기상증착법을 통해 500Å∼1500Å 두께로 증착한다.As shown in FIG. 2E, a titanium nitride film 28, which is an adhesive layer on the entire surface, is deposited to a thickness of 50 kV to 500 kV through physical vapor deposition, and then a bit is deposited on the titanium nitride film 28. The third tungsten film 29, which is a line or metal wiring film, is deposited to have a thickness of 500 mW to 1500 mW by physical vapor deposition.
이와 같이, 물리기상증착법으로 제3 텅스텐막(29)을 증착하는 경우에는 두께에 제한없이 충분히 증착할 수 있다. 반면에, 화학기상증착법을 통해 텅스텐막을 통해 1000Å 미만의 두께로 증착하는 경우에는 높은 라인 저항값때문에 소자의 동작속도 저하를 초래한다.As described above, in the case of depositing the third tungsten film 29 by the physical vapor deposition method, it is possible to deposit sufficiently without limiting the thickness. On the other hand, when deposited to less than 1000kW through a tungsten film through chemical vapor deposition, a high line resistance value causes a decrease in operating speed of the device.
다음으로, 제3 텅스텐막(29)과 티타늄나이트라이드막(28)을 패터닝하여 금속배선을 형성한다. 여기서, 금속배선은 비트라인일 수 있는데, 이로써 텅스텐플러그 기술을 이용하여 텅스텐 비트라인을 형성할 수 있다.Next, the third tungsten film 29 and the titanium nitride film 28 are patterned to form metal wiring. Here, the metal wiring may be a bit line, thereby forming a tungsten bit line using a tungsten plug technology.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 배리어막상에 물리기상증착법으로 텅스텐막을 미리 형성하므로써 불순물 확산에 의한 배리어막의 배리어특성 저하를 방지할 수 있는 효과가 있다.The present invention described above has the effect of preventing the reduction of barrier properties of the barrier film due to the diffusion of impurities by forming the tungsten film in advance by physical vapor deposition on the barrier film.
또한, 물리기상증착법으로 미리 핵생성막 역할을 하는 텅스텐막을 형성하므로써 후속 화학기상증착시 핵생성막 공정을 생략할 수 있어 공정의 안정성을 확보할 수 있는 효과가 있다.In addition, by forming a tungsten film that acts as a nucleation film in advance by physical vapor deposition method, it is possible to omit the nucleation film process during subsequent chemical vapor deposition, thereby ensuring the stability of the process.
또한, 얇은 두께의 텅스텐막을 증착할 경우 표면거칠기가 안좋아지는데 이럴 경우 화학적기계적연마 공정을 적용하여 표면 거칠기를 개선시킬 수 있는 효과가 있다.In addition, when the tungsten film of a thin thickness is deposited, the surface roughness is not good. In this case, the surface roughness may be improved by applying a chemical mechanical polishing process.
또한, 비트라인 또는 금속배선막을 물리기상증착법을 통해 텅스텐막으로 증착하므로써 화학기상증착법에 의해 증착된 텅스텐막의 경우에 발생하는 텅스텐막 산화를 원천적으로 방지할 수 있는 효과가 있다.In addition, by depositing the bit line or the metal wiring film to the tungsten film through the physical vapor deposition method, there is an effect that the oxidation of the tungsten film generated in the case of the tungsten film deposited by the chemical vapor deposition method can be fundamentally prevented.
Claims (9)
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| KR1020020037206A KR20040001872A (en) | 2002-06-29 | 2002-06-29 | Method for forming contact in semiconductor device using tungsten layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100884339B1 (en) * | 2006-06-29 | 2009-02-18 | 주식회사 하이닉스반도체 | Method for forming W film and method for forming W connection line in semiconductor device |
| KR100885786B1 (en) * | 2006-09-06 | 2009-02-26 | 주식회사 하이닉스반도체 | Method of fabricating bit line of semiconductor memory device |
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2002
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100884339B1 (en) * | 2006-06-29 | 2009-02-18 | 주식회사 하이닉스반도체 | Method for forming W film and method for forming W connection line in semiconductor device |
| US7563718B2 (en) | 2006-06-29 | 2009-07-21 | Hynix Semiconductor Inc. | Method for forming tungsten layer of semiconductor device and method for forming tungsten wiring layer using the same |
| KR100885786B1 (en) * | 2006-09-06 | 2009-02-26 | 주식회사 하이닉스반도체 | Method of fabricating bit line of semiconductor memory device |
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