KR100197653B1 - Method of manufacturing contact in semiconductor device - Google Patents
Method of manufacturing contact in semiconductor device Download PDFInfo
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- KR100197653B1 KR100197653B1 KR1019950050467A KR19950050467A KR100197653B1 KR 100197653 B1 KR100197653 B1 KR 100197653B1 KR 1019950050467 A KR1019950050467 A KR 1019950050467A KR 19950050467 A KR19950050467 A KR 19950050467A KR 100197653 B1 KR100197653 B1 KR 100197653B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
Abstract
본 발명은 반도체소자의 콘택형성방법에 관한 것으로, 반도체기판 상부에 전도체가 형성된 절연층을 형성하고 상기 반도체기판과 전도체를 노출시키는 콘택홀을 형성한 다음, 전체표면상부에 티타늄막, 티타늄질화막, 티타늄산화막 척층구조나 티타늄막, 티타늄산화막, 티타늄질화막 적층구조 또는 이들 중 티타늄막이나 티타늄질화막이 제거된 적층구조를 갖는 콘택접합층을 형성하고 텅스텐으로 콘택플러그를 형성함으로써 티타늄막의 침식이나 절연체 형성을 억제하여 소자의 동작특성을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a contact of a semiconductor device, comprising: forming an insulating layer on which a conductor is formed on a semiconductor substrate, forming a contact hole exposing the semiconductor substrate and the conductor, and then forming a titanium film, a titanium nitride film, Forming a contact bonding layer having a titanium oxide film chuck layer structure, a titanium film, a titanium oxide film, a titanium nitride film laminated structure, or a laminate structure in which titanium or titanium nitride film is removed therefrom and forming a contact plug with tungsten to erode or insulate the titanium film. By suppressing and improving the operation characteristics of the device to improve the characteristics and reliability of the semiconductor device, and thereby to enable high integration of the semiconductor device.
Description
제1a도 내지 제1e도는 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성 공정을 도시한 단면도.1A to 1E are cross-sectional views showing a contact forming process of a semiconductor device according to a first embodiment of the present invention.
제2a도 내지 제2c도는 본 발명의 제2실시예에 따른 반도체소자의 콘택 형성 공정을 도시한 단면도.2A to 2C are cross-sectional views illustrating a process for forming a contact of a semiconductor device according to a second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 31 : 반도체 기관 13, 33 : 전도체11, 31: semiconductor organ 13, 33: conductor
15, 35 : 절연층 17, 37 : 제1콘택홀15, 35: insulation layer 17, 37: first contact hole
19, 39 : 제2콘택홀 21 : 티타늄막19, 39: second contact hole 21: titanium film
23, 45 : 티타늄 질화막 25, 43 : 티타늄 산화막23, 45: titanium nitride film 25, 43: titanium oxide film
27, 47 : 텅스텐막27, 47: tungsten film
본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 특히 화학기상 증착법에 의한 텅스텐 증착시 티타늄질화막(TiN)/티타늄의 접합층 위에 또는 티타늄질화막(TiN)과 티타늄(Ti)사이에 TiO2(티타늄 산화물)박막을 형성 또는 증착하여 CVD(화학기상증착법) 텅스텐의 반응물인 텅스텐 헥사플루오라이드(WF6)의 티타늄(Ti)침식에 의한 절연체 티타늄플루오라이트(TiF3)형성을 억제시켜 신뢰성 있는 콘택을 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to TiO 2 (titanium) on a junction layer of titanium nitride (TiN) / titanium or between titanium nitride (TiN) and titanium (Ti) during tungsten deposition by chemical vapor deposition. Oxide) thin film is formed or deposited to suppress the formation of insulator titanium fluorite (TiF 3 ) by titanium (Ti) erosion of tungsten hexafluoride (WF 6 ), a reactant of CVD tungsten, to provide reliable contact. It relates to a technique for forming.
일반적으로, CVD텅스텐막의 접합층으로 티타늄(Ti)위에 티타늄질화막(TiN)를 적층한 구조를 사용하는데, 이 접합층 형성방법으로 스퍼터링을 사용하는 경우 박막의 밀도를 높이고 박막표면에 '산소(O)'가 거의 없는 상태로 만들어도 CVD텅스텐의 반응물인 WF6가 티타늄질화막을 통과하여 티타늄과 반응하여 티타늄플루오라이트를 형성시키면서 콘택의 신뢰성을 떨어뜨린다.In general, a structure in which a titanium nitride film (TiN) is laminated on titanium (Ti) as a bonding layer of a CVD tungsten film is used. When sputtering is used as the bonding layer forming method, the density of the thin film is increased and oxygen (O) is formed on the thin film surface. Even in the absence of), WF 6 , a reactant of CVD tungsten, passes through the titanium nitride film and reacts with titanium to form titanium fluorite, thereby degrading the reliability of the contact.
그로 인하여, 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.Therefore, there is a problem in that the characteristics and reliability of the semiconductor device are lowered, thereby making it difficult to integrate the semiconductor device.
따라서, 본 발명은 티타늄질화막/티타늄의 접합층 위에 또는 티타늄 질화막과 티타늄 사이에 티타늄 산화물(TiO2)을 얇게 증착하거나 형성시켜 CVD텅스텐 반응물인 WF6과 티타늄의 반응을 억제시켜서 절연체인 TiF3형성을 억제하고 신뢰성 있는 콘택을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 콘택 형성방법을 제공하는데 그 목적이 있다.Therefore, the present invention inhibits the reaction of CVD tungsten reactant WF 6 with titanium by thinly depositing or forming titanium oxide (TiO 2 ) on the titanium nitride film / titanium junction layer or between the titanium nitride film and titanium to form TiF 3 as an insulator. It is an object of the present invention to provide a method for forming a contact of a semiconductor device, which can improve the characteristics and reliability of the semiconductor device and thereby enable the high integration of the semiconductor device by suppressing the formation of a reliable contact.
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 콘택 형성방법의 특징은, 반도체기판 상부에 전도체가 구비된 절연층을 형성하는 공정과, 상기 반도체기판과 전도체를 노출시키는 제1,2콘택홀을 각각 형성하는 공정과, 전체표면상부에 티타늄막과 티타늄질화막을 각각 일정두께 형성하는 공정과, 전체표면상부에 티타늄산화막을 일정두께 형성하여 티타늄막, 티타늄질화막, 티타늄산화막 적층구조의 콘택접합층을 형성하는 공정과, 전체표면상부에 텅스텐막을 형성하는 공정을 포함하는데 있다.In order to achieve the above object, a feature of the method for forming a contact of a semiconductor device according to the present invention includes forming an insulating layer having a conductor on an upper portion of the semiconductor substrate, and first and second contact holes exposing the semiconductor substrate and the conductor. And forming a titanium film and a titanium nitride film on the entire surface, respectively, and forming a titanium oxide film on the entire surface, and forming a contact layer of a titanium film, a titanium nitride film and a titanium oxide film. And a step of forming a tungsten film on the entire surface.
여기서, 상기 티타늄막은 물리증착방법(PVD : Physical Vapor Deposition, 이하에서 PVD라 함)방법으로 형성되는 것과, 상기 티타늄막은 화학기상증착(CVD : Chemical Vapor Deposition, 이하에서 CVD라 함)방법으로 형성되는 것과, 상기 티타늄막은 100내지 500Å 두께로 형성되는 것과, 상기 티타늄질화막은 PVD 또는 CVD방법으로 형성되는 것과, 상기 티타늄질화막은 300내지 1000Å 두께로 형성되는 것과, 상기 티타늄산화막은 티타늄 아이소-프로포옥사이드와 산소(O2)를 반응물로 하여 형성되는 것과, 상기 티타늄산화막은 150내지 250℃의 온도, 0.5 내지 2torr의 압력에서 CVD방법으로 형성되는 것과, 상기 티타늄산화막은 10내지 30Å 두께로 형성되는 것과, 상기 콘택접합층은 티타늄막, 티타늄산화막 적층구조로 형성되는 것과, 상기콘택접합층은 티타늄질화막, 티타늄산화막 적층구조로 형성되는 것과, 상기콘택접합층은 티타늄막, 티타늄산화막, 티타늄질화막 적층구조로 형성되는 것과, 상기 콘택접합층은 하나의 챔버내에서 연속적으로 형성되는 것이다.Here, the titanium film is formed by a physical vapor deposition method (PVD: Physical Vapor Deposition, PVD) method, and the titanium film is formed by a chemical vapor deposition (CVD: CVD) method The titanium film is formed to a thickness of 100 to 500Åm, The titanium nitride film is formed by PVD or CVD method, The titanium nitride film is formed to 300 to 1000Åm thick, The titanium oxide film is titanium iso-propoxide And oxygen (O 2 ) as a reactant, the titanium oxide film is formed by a CVD method at a temperature of 150 to 250 ° C., a pressure of 0.5 to 2 torr, and the titanium oxide film is formed to a thickness of 10 to 30 kPa. , The contact bonding layer is formed of a titanium film, titanium oxide film laminated structure, the contact bonding layer is titanium nitride film, titanium oxide film red That is formed of a structure, the contact bonding layer of titanium film, as that, the contact bonding layer formed of the titanium oxide film, a titanium nitride film layered structure is formed continuously within a single chamber.
본 발명의 원리는, 결합 에너지(binding energy)로 설명할 수 있는데 두 원자의 분자구조를 기본으로 실온에서의 결합에너지가 Ti-Ti 경우 141.4±21 KJmol-1, F-Ti 경우 569.±33 KJmol-1, O-Ti 경우 672.4±9.2 KJmol-1이므로, 이를 비교하면 Ti-Ti F-Ti O-Ti과 같아 Ti-Ti는 플루오라이트(Ti-F3)를 형성할 수 있지만 O-Ti 구조는 쉽게 플루오라이트를 형성할 수 없어 O-Ti 구조를 갖는 티타늄산화막으로 Ti-F3형성을 억제하는 것이다.The principle of the present invention can be explained by the binding energy. Based on the molecular structure of two atoms, the binding energy at room temperature is 141.4 ± 21 KJmol -1 for Ti-Ti and 569. ± 33 for F-Ti. In case of KJmol -1 and O-Ti, 672.4 ± 9.2 KJmol -1 . Compared to this, Ti-Ti is the same as F-Ti O-Ti. Ti-Ti can form fluorite (Ti-F 3 ), but O-Ti The structure is such that Ti-F 3 formation is suppressed with a titanium oxide film having an O-Ti structure because it cannot easily form fluorite.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1e도는 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성공정을 도시한 단면도이다.1A to 1E are cross-sectional views showing a contact forming process of a semiconductor device according to a first embodiment of the present invention.
제1a도를 참조하면, 반도체기판(11)상부에 전도체(13)가 형성된 절연층(15)을 형성한다. 그리고, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 반도체기판(11)과 전도체(13)를 노출시키는 제1콘택홀(17)과 제2콘택홀(19)을 각각 형성한다.Referring to FIG. 1A, an insulating layer 15 having a conductor 13 formed on the semiconductor substrate 11 is formed. The first contact hole 17 and the second contact hole 19 exposing the semiconductor substrate 11 and the conductor 13 are formed by an etching process using a contact mask (not shown).
제1b도를 참조하면, 전체표면상부에 PVD또는 CVD방법으로 티타늄막(21)을 100내지 500Å두께 형성한다.Referring to FIG. 1B, the titanium film 21 is formed on the entire surface by a PVD or CVD method with a thickness of 100 to 500 mm 3.
제1c도를 참조하면, 전체표면상부에 PVD또는 CVD방법으로 티타늄질화막(23)을 300내지 1000Å두께 형성한다.Referring to FIG. 1C, the titanium nitride film 23 is formed to have a thickness of 300 to 1000 Å on the entire surface by PVD or CVD.
제1d도를 참조하면, 전체표면상부에 티타늄(IV) 아이소-프로포옥사이드{Ti[OCH(CH3)2]4}와 산소(O2)를 반응물로 150내지 250℃온도, 0.5내지 2torr 압력의 증착조건에서 CVD방법에 의한 티바늄산화막(25)을 10내지 30Å두께 형성한다.Referring to FIG. 1D, titanium (IV) iso-propoxide {Ti [OCH (CH 3 ) 2 ] 4 } and oxygen (O 2 ) are reacted with 150 to 250 ° C. temperature at 0.5 to 2 torr on the entire surface. Under the pressure deposition conditions, the titanium oxide film 25 by the CVD method is formed to have a thickness of 10 to 30 kPa.
제1e도를 참조하면, 전체표면상부에 WF6와 H2를 반응물로 하여 300내지 500℃온도, 10내지 100torr압력의 증착조건에서 텅스텐막(27)을 형성함으로써 콘택을 형성한다.Referring to FIG. 1E, a contact is formed by forming a tungsten film 27 on the entire surface at a deposition condition of 300 to 500 ° C. and 10 to 100 torr pressure using WF 6 and H 2 as reactants.
제2a도 내지 제2c도는 본 발명의 제2실시예에 따른 반도체소자의 콘택형성공정을 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a process for forming a contact of a semiconductor device according to a second exemplary embodiment of the present invention.
제2a도를 참조하면, 반도체기판(11)상부에 전도체(13)가 형성된 절연층(15)을 형성한다. 그리고, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 반도체기판(11)과 전도체(13)를 노출시키는 제1콘택홀(17)과 제2콘택홀(19)을 각각 형성한다. 그리고, 전체표면상부에 PVD또는 CVD방법으로 티타늄막(21)을 100내지 500Å두께 형성한다. 그리고, 전체표면상부에 티타늄(IV) 아이소-프로옥사이드{Ti[OCH(CH3)2]4}와 산소를 반응물로 150내지 250℃온도, 0.5내지 2torr압력의 증착조건에서 CVD방법에 따라 티바늄산화막(43)을 10내지 30Å두께 형성한다.Referring to FIG. 2A, an insulating layer 15 having a conductor 13 formed on the semiconductor substrate 11 is formed. The first contact hole 17 and the second contact hole 19 exposing the semiconductor substrate 11 and the conductor 13 are formed by an etching process using a contact mask (not shown). Then, the titanium film 21 is formed to have a thickness of 100 to 500 mm on the entire surface by PVD or CVD. Then, titanium (IV) iso-prooxide {Ti [OCH (CH 3 ) 2 ] 4 } and oxygen on the entire surface were reacted with the CVD method under the deposition conditions of 150 to 250 ° C. temperature and 0.5 to 2 torr pressure. The barium oxide film 43 is formed to have a thickness of 10 to 30 microns.
제2b도를 참조하면, 전체표면상부에 PVD 또는 CVD방법으로 티타늄질화막(45)을 300~1000Å 두께 형성한다.Referring to FIG. 2B, the titanium nitride film 45 is formed to have a thickness of 300 to 1000 on the entire surface by PVD or CVD.
제2c도를 참조하면, 전체표면상부에 WF6와 H2를 반응물로 하여 300내지 500℃온도, 10내지 100torr압력의 증착조건에서 텅스텐막(47)을 형성함으로써 콘택을 형성한다.Referring to FIG. 2C, a contact is formed by forming a tungsten film 47 on the entire surface at a deposition condition of 300 to 500 ° C. and 10 to 100 torr pressure using WF 6 and H 2 as reactants.
이상에서 설명한 바와 같이 본발명에 따른 반도체소자의 콘택 형성방법은, 콘택공정시 WF6에 의한 티타늄막의 침식을 억제하고 절연체의 발생을 억제하여 콘택특성을 향상시킴으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, the method for forming a contact of a semiconductor device according to the present invention improves the characteristics and reliability of a semiconductor device by suppressing erosion of a titanium film caused by WF 6 and suppressing occurrence of an insulator, thereby improving contact characteristics. Accordingly, there is an advantage that enables high integration of the semiconductor device.
Claims (13)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050467A KR100197653B1 (en) | 1995-12-15 | 1995-12-15 | Method of manufacturing contact in semiconductor device |
| JP8352538A JP2936535B2 (en) | 1995-12-15 | 1996-12-16 | Metal wiring structure of semiconductor device and method of forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050467A KR100197653B1 (en) | 1995-12-15 | 1995-12-15 | Method of manufacturing contact in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970052237A KR970052237A (en) | 1997-07-29 |
| KR100197653B1 true KR100197653B1 (en) | 1999-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950050467A KR100197653B1 (en) | 1995-12-15 | 1995-12-15 | Method of manufacturing contact in semiconductor device |
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| Country | Link |
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| JP (1) | JP2936535B2 (en) |
| KR (1) | KR100197653B1 (en) |
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| US10833199B2 (en) | 2016-11-18 | 2020-11-10 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
| US10872964B2 (en) | 2016-06-17 | 2020-12-22 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
| US10879366B2 (en) | 2011-11-23 | 2020-12-29 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
| US10937880B2 (en) | 2002-08-12 | 2021-03-02 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US11043571B2 (en) | 2002-08-12 | 2021-06-22 | Acorn Semi, Llc | Insulated gate field effect transistor having passivated schottky barriers to the channel |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100465605B1 (en) * | 1997-12-31 | 2005-04-06 | 매그나칩 반도체 유한회사 | Manufacturing method of semiconductor device |
| KR100422356B1 (en) * | 2001-09-05 | 2004-03-11 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
| KR100857009B1 (en) * | 2006-12-28 | 2008-09-04 | 동부일렉트로닉스 주식회사 | Vertical metal line of Semiconductor device and the Fabricating Method thereof |
-
1995
- 1995-12-15 KR KR1019950050467A patent/KR100197653B1/en not_active IP Right Cessation
-
1996
- 1996-12-16 JP JP8352538A patent/JP2936535B2/en not_active Expired - Fee Related
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| US11043571B2 (en) | 2002-08-12 | 2021-06-22 | Acorn Semi, Llc | Insulated gate field effect transistor having passivated schottky barriers to the channel |
| US10937880B2 (en) | 2002-08-12 | 2021-03-02 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US10950707B2 (en) | 2002-08-12 | 2021-03-16 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US11018237B2 (en) | 2002-08-12 | 2021-05-25 | Acorn Semi, Llc | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US11056569B2 (en) | 2002-08-12 | 2021-07-06 | Acorn Semi, Llc | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US11355613B2 (en) | 2002-08-12 | 2022-06-07 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US10879366B2 (en) | 2011-11-23 | 2020-12-29 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
| US11610974B2 (en) | 2011-11-23 | 2023-03-21 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
| US11804533B2 (en) | 2011-11-23 | 2023-10-31 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
| US10872964B2 (en) | 2016-06-17 | 2020-12-22 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
| US11843040B2 (en) | 2016-06-17 | 2023-12-12 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
| US10833199B2 (en) | 2016-11-18 | 2020-11-10 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
| US11462643B2 (en) | 2016-11-18 | 2022-10-04 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09326368A (en) | 1997-12-16 |
| KR970052237A (en) | 1997-07-29 |
| JP2936535B2 (en) | 1999-08-23 |
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