KR100268792B1 - Capacitor forming method of semiconductor device - Google Patents
Capacitor forming method of semiconductor device Download PDFInfo
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- KR100268792B1 KR100268792B1 KR1019970030279A KR19970030279A KR100268792B1 KR 100268792 B1 KR100268792 B1 KR 100268792B1 KR 1019970030279 A KR1019970030279 A KR 1019970030279A KR 19970030279 A KR19970030279 A KR 19970030279A KR 100268792 B1 KR100268792 B1 KR 100268792B1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000003990 capacitor Substances 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 239000002243 precursor Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000010409 thin film Substances 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 21
- 238000009832 plasma treatment Methods 0.000 claims description 8
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 11
- 239000010936 titanium Substances 0.000 abstract description 11
- 239000010410 layer Substances 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000013212 metal-organic material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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Abstract
Description
본 발명은 차세대 반도체소자에서 캐패시터(Capacitor) 재료로서 사용이 기대되는 Ta2O5, PbTiO3, PbZr-1XTixO3, SrBi2Ta2O9, Bi4Ti3O12, BatIO3, Ba1-xSrxTiO3, SrTiO3등의 고유전체에 대한 상부 및 하부전극 재료로서 TDMAT, TEMAT, TDEAT 등의 전구체를 원료로 하여 제조한 티타늄나이트라이드(TiN)박막을 사용하는 기술에 관한 것으로 특히 TiN의 개질처리에 의해 제조된 TiN의 구조에 관한 것이다.According to the present invention, Ta 2 O 5 , PbTiO 3 , PbZ r-1X T ix O 3 , SrBi 2 Ta 2 O 9 , Bi 4 Ti 3 O 12 , and BatIO 3 are expected to be used as capacitor materials in next-generation semiconductor devices. , as the upper and lower electrode materials for the high dielectric, such as Ba 1-x SrxTiO 3, SrTiO 3 relates to a technique of using a titanium nitride (TiN) thin film prepared from a precursor, such as TDMAT, TEMAT, TDEAT as a raw material In particular, it relates to the structure of TiN produced by the modification process of TiN.
상기한 Ta2O5, PbTiO3, PbZr-1xTixO3, SrBi2Ta2O9, Ba1-XSrxTiO3, 등의 높은 유전상수를 갖는 재료위에 상,하부전극으로 사용될 재료는, 전기 전도도 이외에 높은 온도에서도 유전체와 물리적, 화학적으로 안정적인 물질이어야 한다.On the materials having high dielectric constants such as Ta 2 O 5 , PbTiO 3 , PbZ r-1x T ix O 3 , SrBi 2 Ta 2 O 9 , Ba 1-X SrxTiO 3 , In addition to the electrical conductivity, it must be a dielectric and physically and chemically stable material at high temperatures.
또한, 전후 공정에서 사용되는 절연산화물과의 반응에 의한 산화반응을 일으키지 않아야 한다. 현재 반도체 제조공정에서 가장 널리 사용되고 있는 스퍼터링 TiN 은 전기 전도도가 우수하지만 고유전 물질과 반응하여 TiO 또는 TiO2를 계면에 형성시킴으로써 캐패시터의 유전율을 떨어뜨리며 전기적으로 절연시키는 문제점이 있다.In addition, the oxidation reaction by the reaction with the insulating oxide used in the before and after process should not occur. Sputtering TiN, which is most widely used in the current semiconductor manufacturing process, has excellent electrical conductivity, but has a problem of lowering the dielectric constant of the capacitor and electrically insulating it by reacting with a high dielectric material to form TiO or TiO 2 at an interface.
특히, Ti-산화막의 형성시 부피 팽창에 기인한 막의 균열 또는 막의 벗겨짐(peeling)현상을 야기시킨다. 이에 따라 정상적인 소자의 동작은 불가능해진다. 따라서 Ti- 산화막의 형성을 최대한 막아주어야 한다.In particular, the formation of the Ti-oxide film causes cracking of the film or peeling of the film due to volume expansion. As a result, normal operation of the device becomes impossible. Therefore, the formation of Ti-oxide film should be prevented as much as possible.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 전기전도도가 우수하며, 확산장벽 및 내산화 특성이 우수하고, 고유전체막을 사용할 수 있는 상,하부전극을 형성하여 반도체소자의 고집적화를 가능하게 하는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art, the present invention has excellent electrical conductivity, excellent diffusion barrier and oxidation resistance, and enables high integration of semiconductor devices by forming upper and lower electrodes which can use a high dielectric film. It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device.
제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성 방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
1 : 콘택플러그 2 : 티타늄막1: Contact Plug 2: Titanium Film
3 : 플라즈마 처리되지않은 제1MOCVD-TiN3: 1st MOCVD-TiN not plasma treated
4 : 플라즈마 처리된 제1MOCVD-TiN4: plasma-treated first MOCVD-TiN
5 : 유전체막 6 : 플라즈마 처리된 제2MOCVD-TiN5 dielectric film 6 plasma treated second MOCVD-TiN
7 : 플라즈마 처리되지않은 제2MOCVD-TiN7: second MOCVD-TiN not plasma treated
이상의 목적을 달성하기위해 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 반도체기판의 층간절연막에 구비된 콘택홀을 매립하는 콘택플러그를 형성하는 공정과, 상기 반도체기판 상부에 Ti 박막을 형성하는 공정과, 상기 Ti 박막상에 하부전극으로써 플라즈마 처리되거나 처리되지않은 MOCVD-TiN을 적층하는 단계; 상기 적층된 MOCVD-TiN과 Ti 박막을 선택 식각하여 하부전극 패턴을 형성하는 공정과, 상기 하부전극 패턴 표면상에 유전체막을 형성하는 공정과, 상기 유전체막상에 상기 하부전극 형성공정의 역순으로 플라즈마 처리되거나 처리되지않은 MOCVD-TiN으로 적층된 구조를 갖는 상부전극을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention includes forming a contact plug for filling a contact hole provided in an interlayer insulating film of a semiconductor substrate, and forming a Ti thin film on the semiconductor substrate. Laminating MOCVD-TiN with or without plasma treatment as a lower electrode on the Ti thin film; Selectively etching the stacked MOCVD-TiN and Ti thin films to form a lower electrode pattern, forming a dielectric film on the lower electrode pattern surface, and plasma processing in the reverse order of forming the lower electrode on the dielectric film. And forming a top electrode having a structure laminated with untreated or untreated MOCVD-TiN.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention for achieving the above object is as follows.
Ta2O5, PbTiO3, PbZr-1XTixO3, SrBi2Ta2O9, Ba1-xSrxTiO3, 등의 높은 유전상수를 갖는 재료위에 상하부 전극으로 사용될 재료로서, 확산장벽 특성이 우수하며 모서리 도포성(step coverage) 이 훌륭한 MOCVD-TiN(Metal Organic Chemical Vapor Deposited - Titanium Nitride, 이하에서 MOCVD-TiN 이라 함)을 사용하여 제조함으로써 앞서 기술한 문제를 해결하고자 하였다. 이때, 상기 MOCVD-TiN 은 TDMAT, TDEAT, TEMAT 등의 금속 유기물을 전구체(precursor)로 사용하여 제조한다. 그리고, 용도에 따라 CVD-TiN 층을 플라즈마 처리함으로써 전기전도도가 우수하며 확산장벽 및 내산화 특성이 우수한 막을 제조할 수 있으며 고유전체에 대한 전극 물질로 적합하도록 하는 것이다,Diffusion barrier properties as a material to be used as upper and lower electrodes on materials with high dielectric constants such as Ta 2 O 5 , PbTiO 3 , PbZ r-1X T ix O 3 , SrBi 2 Ta 2 O 9 , Ba 1-x SrxTiO 3 , etc. By using MOCVD-TiN (Metal Organic Chemical Vapor Deposited-Titanium Nitride, hereinafter referred to as MOCVD-TiN) which has excellent edge coverage and excellent step coverage, the above-mentioned problem was solved. At this time, the MOCVD-TiN is prepared using a metal organic material such as TDMAT, TDEAT, TEMAT as a precursor (precursor). In addition, by plasma treatment of the CVD-TiN layer according to the application, it is possible to produce a film having excellent electrical conductivity, excellent diffusion barrier and oxidation resistance, and to be suitable as an electrode material for a high dielectric material,
일반적으로, MOCVD-TiN은 스퍼터 TiN 또는 TiCl4를 사용한 CVD-TiN에 비해 확산장벽 특성이 월등히 우수하다. 그리고, 박막의 구조가 치밀하지 못하여 대기에 노출될 경우 대기중의 수분 및 산소를 흡수하는 경향이 있다. 이때, 박막의 비저항은 흡수되는 양에따라 증가하게 되는데 이것은 박막의 증착후 플라즈마 처리를 이용하여 박막을 치밀화시킴으로써 대기 노출시 산소등의 흡수를 억제시켜 방지할 수 있다. 그러나, MOCVD-TiN 박막의 플라즈마 처리는 확산장벽 특성을 급격히 저하시키는 부정적인 효과도 있다.In general, MOCVD-TiN has excellent diffusion barrier properties compared to CVD-TiN using sputtered TiN or TiCl 4 . When the structure of the thin film is not dense and exposed to the air, the thin film tends to absorb moisture and oxygen in the air. At this time, the specific resistance of the thin film is increased according to the amount absorbed. This can be prevented by suppressing the absorption of oxygen or the like during atmospheric exposure by densifying the thin film by using a plasma treatment after deposition of the thin film. However, plasma treatment of the MOCVD-TiN thin film also has a negative effect of drastically reducing the diffusion barrier properties.
이러한 MOCVD-TiN이 갖는 특성을 잘 조합함으로써 전기전도도를 크게 증가시키지 않으면서 확산장벽 및 내산화성이 우수한 박막을 제조할 수 있다. 예를 들어 300Å의 TiN 박막을 제조할 경우 밑의 150Å은 플라즈마 처리를 하여주어 전기전도도를 향상시키고 위의 150Å은 플라즈마 처리를 생략함으로써 TiN위 층과의 산화반응 및 확산장벽 특성을 향상시킬 수 있다. 이렇게 제조된 MOCVD-TiN 박막은 단차피복성이 우수하여 고유전체에 대한 상,하부전극으로의 사용에 무리가 없으며 화학적, 전기적으로 요구되는 성질을 만족시킬 수 있어 그 응용이 기대된다.By combining these characteristics of MOCVD-TiN well, it is possible to produce a thin film having excellent diffusion barrier and oxidation resistance without significantly increasing the electrical conductivity. For example, in the case of manufacturing a 300Å TiN thin film, the bottom 150Å may be subjected to plasma treatment to improve electrical conductivity, and the 150Å above may omit plasma treatment to improve oxidation reaction and diffusion barrier properties with the TiN layer. . The MOCVD-TiN thin film thus prepared has excellent step coverage and is suitable for use as an upper and lower electrode for high dielectric materials, and can satisfy chemical and electrical properties required.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다,Hereinafter, with reference to the accompanying drawings will be described in detail the present invention,
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(20) 상부에 층간절연막(8)을 형성하고, 콘택마스크(도시안 됨)를 이용한 식각공정으로 상기 층간절연막(8)을 식각하여 콘택홀(10)을 형성한다. 이때, 상기 층간절연막(8)은 소자분리막, 워드라인 또는 비트라인이 형성된 것이다.First, the
그리고, 상기 콘택홀(10)을 매립하는 콘택플러그(1)를 형성한다. 이때, 상기 콘택플러그(1)는 다결정실리콘으로 상기 콘택홀(10)을 매립하고 이를 전면식각하여 형성한다.In addition, a contact plug 1 filling the
그 다음에, 상기 층간절연막(8) 상부에 Ti 박막(2)을 100~1000 Å정도의 두께로 형성한다.Next, a Ti
그리고, 상기 Ti 박막(2) 상부에 플라즈마 처리되지 않은 제1MOCVD-TiN(3)과 플라즈마 처리된 제1MOCVD-TiN (4)을 순차적으로 형성하여 전체두께가 100~1000 Å 정도의 두께로 하부전극을 형성한다.In addition, the first thin film of the first MOCVD-TiN 3 and the non-plasma treated first MOCVD-TiN 4 are sequentially formed on the Ti
이때, 상기 플라즈마 처리된 제1MOCVD-TiN(4)은 30~500 Å정도의 두께로 형성한다.At this time, the plasma-treated first MOCVD-TiN (4) is formed to a thickness of about 30 ~ 500 Å.
그리고, 상기 하부전극은, 플라즈마 처리된 제1MOCVD-TiN / 플라즈마 처리되지 않은 제1MOCVD-TiN 의 적층구조, 플라즈마 처리된 제1MOCVD-TiN / 플라즈마 처리되지 않은 제1MOCVD-TiN / 플라즈마 처리된 제1MOCVD-TiN 의 적층구조 또는 플라즈마 처리되지 않은 제1MOCVD-TiN / 플라즈마 처리된 제1MOCVD-TiN / 플라즈마처리되지않은 제1MOCVD-TiN 의 적층구조로 형성할 수도 있다.The lower electrode may include a plasma structured stack of 1MOCVD-TiN / plasma-free first MOCVD-TiN; It is also possible to form a laminate structure of TiN or a laminate structure of first MOCVD-TiN / plasma treated first MOCVD-TiN / non-plasma treated first MOCVD-TiN.
그리고, 상기 TiN은 TDMAT, TDEAT, TEMAT 등의 금속 유기물을 전구체로 하여 형성한다.(도 1a)The TiN is formed by using a metal organic material such as TDMAT, TDEAT, TEMAT as a precursor (FIG. 1A).
그 다음에, 저장전극마스크(도시안됨)를 이용한 식각공정으로 상기 플라즈마 처리된 제1MOCVD-TiN(4)과 플라즈마 처리되지 않은 제1MOCVD-TiN (3) 및 Ti박막(2)을 순차적으로 식각하여 하부전극을 형성한다.(도 1b)Subsequently, the plasma-processed first MOCVD-TiN 4 and the unprocessed first MOCVD-TiN 3 and Ti
그 다음에, 상기 하부전극이 형성된 반도체기판(20)의 전체표면상부에 유전체막(5)을 형성한다. 이때, 상기 유전체막(5)은 Ta2O5, PbTiO3, PbZr-1XTixO3, SrBi2Ta2O9, Ba1-xSrxTiO3, 등의 높은 유전상수를 갖는 재료로 형성한다.(도 1c)Next, a
그리고, 상기 유전체막(5) 상부에 상기 하부전극 형성방법과 같은 방법으로 형성하되, 역순으로 형성한다.The lower electrode is formed on the
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, TDMAT, TDEAT, TEMAT 등의 금속 유기체를 전구체로 하여 CVD 방법으로 제조된 TiN박막을 제조하여 반응성이온식각 (RIE, reactive ion etch)을 용이하게 실시할수 있도록 하고, 단차피복성을 가지며, 적절한 플라즈마처리시 유전층과의 계면을 안정적으로 유지할 수 있다. 따라서 반도체 소자의 신뢰성을 향상시킬 수 있으며 공정 단계의 축소 및 공정의 단순화에 기인한 제조 원가의 감소효과가 대단히 크다.As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, a reactive ion etch (RIE) is prepared by preparing a TiN thin film manufactured by a CVD method using metal organisms such as TDMAT, TDEAT, and TEMAT as precursors. It can be easily carried out, has a step coverage, and can stably maintain the interface with the dielectric layer during proper plasma treatment. Therefore, the reliability of the semiconductor device can be improved, and the manufacturing cost is greatly reduced due to the reduction of process steps and the simplification of the process.
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| KR970024215A (en) * | 1995-10-28 | 1997-05-30 | 김광호 | Method of forming tantalum pentoxide capacitor by vacuum annealing |
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