KR20040059971A - Method for fabricating capacitor in semiconductor device - Google Patents
Method for fabricating capacitor in semiconductor device Download PDFInfo
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- KR20040059971A KR20040059971A KR1020020086479A KR20020086479A KR20040059971A KR 20040059971 A KR20040059971 A KR 20040059971A KR 1020020086479 A KR1020020086479 A KR 1020020086479A KR 20020086479 A KR20020086479 A KR 20020086479A KR 20040059971 A KR20040059971 A KR 20040059971A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 78
- 239000010409 thin film Substances 0.000 claims description 28
- 238000005121 nitriding Methods 0.000 claims description 5
- 239000012495 reaction gas Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract 1
- 230000001546 nitrifying effect Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910021341 titanium silicide Inorganic materials 0.000 description 4
- 229910052741 iridium Inorganic materials 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- -1 H 2 O Chemical compound 0.000 description 2
- 229910019899 RuO Inorganic materials 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing capacitors in semiconductor devices.
반도체 소자, 특히 DRAM(Dynamic Random Access Memory)의 반도체 메모리의 집적도가 증가함에 따라 정보 기억을 위한 기본 단위인 메모리 셀의 면적이 급격하게 축소되고 있다.As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.
이러한 메모리 셀 면적의 축소는 셀 캐패시터의 면적 감소를 수반하여, 센싱 마진과 센싱 속도를 떨어뜨리고, α-입자에 의한 소프트 에러(Soft Error)에 대한 내구성이 저하되는 문제점을 유발하게 된다. 따라서, 제한된 셀 면적에서 충분한 정전용량을 확보할 수 있는 방안이 필요하게 되었다.Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.
캐패시터의 정전용량(C)은 하기의 수학식 1과 같이 정의된다.The capacitance C of the capacitor is defined as in Equation 1 below.
여기서, ε은 유전률, As는 전극의 유효 표면적, d는 전극간 거리를 각각 나타낸 것이다.Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.
따라서, 캐패시터의 정전용량을 늘리기 위해서는 전극의 표면적을 넓히거나, 유전체 박막의 두께를 줄이거나, 유전률을 높여야 한다.Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.
이 중에서 전극의 표면적을 넓히는 방안이 제일 먼저 고려되어 왔다. 컨케이브 구조, 실린더 구조, 다층 핀 구조 등과 같은 3차원 구조의 캐패시터는 모두 제한된 레이아웃 면적에서 전극의 유효 표면적을 증대시키기 위하여 제안된 것이다. 그러나, 이러한 방법은 반도체 소자가 초고집적화 되면서 전극의 유효 표면적을 증대시키는데 한계를 보이고 있다.Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of the electrode in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.
그리고, 전극간 거리(d)를 최소화하기 위해 유전체 박막의 두께를 감소시키는 방안은 유전체 박막의 두께가 감소함에 따라 누설전류가 증가하는 문제 때문에 역시 그 한계에 직면하고 있다.In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.
따라서, 근래에 들어서는 주로 유전체 박막의 유전율의 증대를 통한 캐패시터의 정전용량 확보에 초점을 맞추어 연구, 개발이 진행되고 있다. 전통적으로, 실리콘산화막이나 실리콘질화막을 유전체 박막 재료로 사용한 소위 NO(Nitride-Oxide) 구조의 캐패시터가 주류를 이루었으나, 최근에는 Ta2O5, Al2O3, HfO2, (Ba,Sr)TiO3(이하 BST라 함) 등의 고유전체 물질이나, (Pb,Zr)TiO3(이하 PZT라 함), (Pb,La)(Zr,Ti)O3(이하 PLZT라 함), SrBi2Ta2O9(이하 SBT라 함), Bi4-xLaxTi3O12(이하, BLT라 함) 등의 강유전체 물질을 유전체 박막 재료로 적용하고 있다.Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta 2 O 5 , Al 2 O 3 , HfO 2 , (Ba, Sr) High dielectric materials such as TiO 3 (hereinafter referred to as BST), (Pb, Zr) TiO 3 (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O 3 (hereinafter referred to as PLZT), SrBi2Ta2O 9 Ferroelectric materials such as SBT and Bi 4-x La x Ti 3 O 12 (hereinafter referred to as BLT) are applied as dielectric thin film materials.
이러한 고유전체 물질 또는 강유전체 물질을 유전체 박막 재료로 사용하는고유전체 캐패시터 또는 강유전체 캐패시터를 제조함에 있어서, 고유전체 물질 또는 강유전체 물질 특유의 유전 특성을 구현하기 위해서는 유전체 주변 물질 및 공정의 적절한 제어가 수반되어야 한다.In manufacturing a high dielectric capacitor or a ferroelectric capacitor using such a high dielectric material or ferroelectric material as a dielectric thin film material, proper control of dielectric surrounding materials and processes must be accompanied to realize dielectric properties specific to the high dielectric material or ferroelectric material. do.
일반적으로, 고유전체 캐패시터나 강유전체 캐패시터의 상, 하부전극 물질로서 노블메탈(noble metal) 또는 이들의 화합물, 예컨대 Pt, Ir, Ru, RuO2, IrO2등을 사용하고 있다.In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO 2 , IrO 2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.
도1a 및 도1b는 종래기술에 의한 반도체 장치의 캐패시터 제조방법을 나타낸 공정단면도로서, 특히 3차원 콘케이브형의 캐패시터 제조방법이다.1A and 1B are process cross-sectional views showing a method of manufacturing a capacitor of a semiconductor device according to the prior art, in particular a method of manufacturing a three-dimensional concave type capacitor.
도1a에 도시된 바와 같이, 활성영역(11)이 형성된 반도체기판(10)상에 층간절연막(12)을 형성한 후, 층간절연막(12)을 관통하여 반도체기판(10)의 활성영역(11)과 연결되는 콘택홀을 형성한다. 이어서 콘택홀을 도전성을 가지는 실리콘막으로 매립하여 스토리지 노드(storage node) 콘택플러그(13)를 형성한다.As shown in FIG. 1A, after the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, the active region 11 of the semiconductor substrate 10 passes through the interlayer insulating film 12. Form a contact hole connected to the Subsequently, the contact hole is filled with a conductive silicon film to form a storage node contact plug 13.
이어서 콘택플러그(13)상부의 일정부분을 리세스(recess)시고, 리세스시킨 영역에 티타늄실리사이드막(14)을 형성하고, 그 상부에 베리어메탈(15)을 형성한다. 여기서 티타늄실리사이드막(14)은 하부구조인 실리콘막과 상부구조의 금속막과의 오믹콘택층을 형성하기 위한 막이고, 베리어메탈(15)은 산소의 하부침투방지와 상호물질확산을 방지하기 위한 막으로서 주로 티타늄나이트라이드막을 사용한다.Subsequently, a predetermined portion of the upper portion of the contact plug 13 is recessed to form a titanium silicide film 14 in the recessed region, and a barrier metal 15 is formed on the recess plug. Here, the titanium silicide film 14 is a film for forming an ohmic contact layer between the silicon film of the lower structure and the metal film of the upper structure, and the barrier metal 15 is used to prevent the lower penetration of oxygen and diffusion of mutual materials. Mainly a titanium nitride film is used as the film.
이어서 캐패시터 형성용 절연막(16)을 캐패시터가 형성될 높이만큼 형성한 다음, 콘택플러그(13)의 상부의 베리어메탈(15)이 노출되도록 캐패시터 형성용 절연막(14)을 선택적으로 제거하여 캐패시터 형성용 홀(17)을 형성한다.Subsequently, the capacitor forming insulating film 16 is formed to have a height at which the capacitor is to be formed, and then the capacitor forming insulating film 14 is selectively removed so that the barrier metal 15 on the upper portion of the contact plug 13 is exposed. The hole 17 is formed.
이어서 도1b에 도시된 바와 같이, 캐패시터 형성용 홀(17)내부에 도전성막으로 하부전극(18)을 형성한다.Subsequently, as shown in FIG. 1B, the lower electrode 18 is formed of a conductive film in the capacitor forming hole 17.
여기서 하부전극은 3차원 구조의 캐패시터 제작에 용이하며, 오믹콘택층으 사용되는 티타늄실리사이드와 베리어메탈로 사용하는 티타늄나이트라이드와 동일계열이라는 장점으로 티타늄나이트라이드막을 사용한다.The lower electrode uses a titanium nitride film because it is easy to manufacture a capacitor having a three-dimensional structure, and has the same series as titanium nitride used as an ohmic contact layer and titanium nitride used as a barrier metal.
이어서 하부전극(18)상에 유전체박막(19)을 형성하고, 유전체 박막의 유전특성향상을 위한 열공정을 실시한다. 이전에는 유전체박막으로 실리콘계열의 유전체를 사용하였으나, 반도체 장치가 고집화되면서 일정용량이상의 캐패시턴스를 확보하기 위해 Ta2O5막, Al2O3막, HfO2막등의 고유전체를 사용한다.Subsequently, a dielectric thin film 19 is formed on the lower electrode 18, and a thermal process for improving dielectric properties of the dielectric thin film is performed. Previously, a silicon-based dielectric was used as the dielectric thin film. However, in order to secure a capacitance of more than a predetermined capacity as a semiconductor device becomes high, a high dielectric material such as a Ta 2 O 5 film, an Al 2 O 3 film, and an HfO 2 film is used.
이어서 유전체 박막(19) 상부에 도전성막을 이용하여 상부전극(20)을 형성한다.Subsequently, an upper electrode 20 is formed on the dielectric thin film 19 by using a conductive film.
전술한 바와 같이 고집적반도체에서는 캐패시터의 표면적을 높이기위해 하부전극을 3차원형태로 형성하게 되고, 유전체 박막의 스텝커버리지(step coverage)를 확보하기 위해 Ta2O5막, Al2O3막, HfO2막등의 유전체 박막을 화학기상증착법 또는 원자층증착법을 이용하여 하부전극(18)상에 형성하게 된다.As described above, in the highly integrated semiconductor, in order to increase the surface area of the capacitor, the lower electrode is formed in a three-dimensional form, and in order to secure step coverage of the dielectric thin film, a Ta 2 O 5 film, an Al 2 O 3 film, and an HfO A dielectric thin film such as two films is formed on the lower electrode 18 by chemical vapor deposition or atomic layer deposition.
그러나 원자층증착법 또는 화학기상증착법을 이용하여 유전체박막(19)을 형성할 때에 유기금속소스(organic metal source)와 함께 H2O, O2, O3등의 산소를 포함한 반응가스를 반응물로 사용하기 때문에 유전체 박막(19)을 형성하는 공정에서 산소가 하부전극(18)와 유전체 박막(19)의 계면에 침투하게 된다.However, when forming the dielectric thin film 19 using atomic layer deposition or chemical vapor deposition, a reaction gas containing oxygen such as H 2 O, O 2 , O 3 together with an organic metal source is used as a reactant. Therefore, oxygen penetrates the interface between the lower electrode 18 and the dielectric thin film 19 in the process of forming the dielectric thin film 19.
이 때 침투된 산소는 후속 열공정에서 하부전극으로 사용된 물질(티타늄타이트라이드와 반응하여 계면산화막(TiO2)으로 형성되는데, 이 때 형성된 산화막은 그 특성상 높은 누설전류특성을 보이며 상하부 전극사이의 거리를 증가시킴으로 캐패시터의 캐패시턴스를 낮추게 되고, 상변화에 따른 부피변화에 의해 캐패시터 구조의 불안정성 및 전기적 특성열화를 증대시키게 된다.At this time, the infiltrated oxygen is formed into a surface oxide film (TiO 2 by reacting with titanium nitride in the subsequent thermal process, and the formed oxide film shows high leakage current characteristics between the upper and lower electrodes. By increasing the distance, the capacitance of the capacitor is lowered, and the instability and electrical property deterioration of the capacitor structure are increased by the volume change caused by the phase change.
따라서 이를 해결하기 위해서 유전체 박막을 형성하기 전에, 하부전극 표면을 질화처리하여 후속공정에서 산소가 침투하여 산화막이 생성되는 것을 방지하고 있다.Therefore, in order to solve this problem, before forming the dielectric thin film, the lower electrode surface is nitrided to prevent oxygen from penetrating in a subsequent process to form an oxide film.
그러나, 하부전극이 캐패시터 형성용 홀의 내부에 형성되어 있기 때문에, 하부전극 표면 전체에 고르게 질화처리하기가 어렵다.However, since the lower electrode is formed in the capacitor forming hole, it is difficult to nitride evenly over the entire surface of the lower electrode.
통상적으로 기판의 상,하부에 고전압을 형성하여 NH3을 플라즈마 처리로 하여 캐패시터 형성용 홀의 내부에 형성된 하부전극의 전표면을 질화처리하게 되는데, 이 때의 공정에서 사용되는 플라즈마는 그 특성상 직진성을 가지게 되어 캐패시터 형성용 홀의 측벽면에 형성된 하부전극의 표면에는 질화처리가 잘 되지 않는다.In general, a high voltage is formed on the upper and lower portions of the substrate, and NH 3 is subjected to plasma treatment, thereby nitriding the entire surface of the lower electrode formed inside the capacitor forming hole. Nitriding treatment is poor on the surface of the lower electrode formed on the sidewall surface of the capacitor forming hole.
반도체 장치가 고집적화되면서, 캐패시터 형성용 홀의 깊이는 더 깊어지고 폭은 더 좁아지게 되어, 캐패시터 형성용 홀의 하단부 및 측벽면에 형성된 하부전극의 표면에는 고르게 질화처리하기가 더 힘들어진다.As the semiconductor device is highly integrated, the depth of the capacitor forming hole becomes deeper and the width becomes narrower, making it more difficult to evenly nitride the surface of the lower electrode formed on the lower end portion and the sidewall surface of the capacitor forming hole.
하부전극의 표면상에 질화처리가 되지 않은 부분을 후속 공정에서 저유전율의 산화막이 생성되어 캐패시턴스를 저하시키게 되어 반도체 장치의 동작상의 신뢰성을 저하 시키게된다.A portion of the lower electrode which is not nitrided on the surface of the lower electrode is formed in an oxide film having a low dielectric constant in a subsequent process to lower the capacitance, thereby lowering the operational reliability of the semiconductor device.
본 발명은 상기의 문제점을 해결하기위해 제안된 것으로 고집적 반도체 장치에서 3차원 형태의 캐패시터의 하부전극 표면을 고르게 질화처리하여 전극막과 유전체박막사이에 저유전율의 계면산화막 생성을 억제함으로서 캐패시터의 특성이 저하되지 않는 캐패시터 제조방법을 제공함을 목적으로 한다.The present invention has been proposed to solve the above problems. In the highly integrated semiconductor device, the lower electrode surface of the three-dimensional capacitor is uniformly nitrided to suppress the formation of a low dielectric constant interfacial oxide film between the electrode film and the dielectric thin film. It is an object of the present invention to provide a method of manufacturing a capacitor which does not deteriorate.
도1a 및 도1b는 종래기술에 따른 반도체 장치의 캐패시터 제조방법을 나타내는 공정단면도.1A and 1B are cross-sectional views showing a method of manufacturing a capacitor of a semiconductor device according to the prior art.
도2a 내지 도2d는 본 발명의 바람직한 실시예에 따른 반도체 장치의 캐패시터 제조방법을 나타내는 공정단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
30 : 기판30: substrate
31 : 활성영역31: active area
32 : 제1 층간절연막32: first interlayer insulating film
33 : 콘택플러그33: Contact Plug
34 : 티타늄실리사이드막34: titanium silicide film
35 : 베리어메탈35: Barrier Metal
36 : 캐패시터 형성용 절연막36: insulating film for capacitor formation
37 : 캐패시터 형성용 홀37: hole for capacitor formation
38 : 하부전극38: lower electrode
40 : 유전체박막40: dielectric thin film
41 : 상부전극41: upper electrode
상기의 목적을 달성하기 위해 본 발명은 기판상에 캐패시터가 형성될 높이만큼 캐패시터 형성용 절연막을 형성하는 단계; 캐패시터가 형성될 영역의 상기 캐패시터 형성용 절연막을 선택적으로 제거하여 캐패시터 형성용 홀을 형성하는 단계;상기 캐패시터 형성용 홀의 내부에 하부전극을 형성하는 단계; 리모트 플라즈마를 이용하여 상기 하부전극의 표면을 질화처리하는 단계; 상기 하부전극 상에 유전체 박막을 형성하는 단계; 및 상기 유전체 박막상에 상부전극을 형성하는 단계를 포함하는 반도체 장치의 캐패시터 제조방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming an insulating film for forming a capacitor to a height to form a capacitor on the substrate; Selectively removing the capacitor forming insulating layer in the region where the capacitor is to be formed to form a capacitor forming hole; forming a lower electrode in the capacitor forming hole; Nitriding the surface of the lower electrode using a remote plasma; Forming a dielectric thin film on the lower electrode; And it provides a method of manufacturing a capacitor of a semiconductor device comprising the step of forming an upper electrode on the dielectric thin film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2d는 본 발명의 바람직한 실시예에 따른 반도체 장치의 캐패시터 제조방법을 나타내는 공정단면도로서, 특히 콘케이브형 3차원캐패시터의 제조방법을 나타낸다.2A to 2D are process cross-sectional views showing a method of manufacturing a capacitor of a semiconductor device according to a preferred embodiment of the present invention, and in particular, a method of manufacturing a concave three-dimensional capacitor.
먼저 도2a에 도시된 바와 같이, 활성영역(31)이 형성된 반도체기판(30)상에 층간절연막(32)을 형성한 후, 층간절연막(32)을 관통하여 반도체기판(30)의 활성영역(31)과 연결되는 콘택홀을 형성한다. 이어서 도전성을 가지는 실리콘막을 이용하여 콘택홀이 매립되도록한 다음, 화학적기계적 연마등의 공정을 이용하여 평탄화시켜 스토리지 노드 콘택플러그(33)를 형성한다.First, as shown in FIG. 2A, the interlayer insulating film 32 is formed on the semiconductor substrate 30 on which the active region 31 is formed, and then penetrates the interlayer insulating film 32 to form an active region ( A contact hole connected to 31 is formed. Subsequently, the contact hole is buried using a conductive silicon film, and then planarized using a process such as chemical mechanical polishing to form the storage node contact plug 33.
이어서 콘택플러그(33)상부의 일정부분을 리세스(recess)시키고, 리세스시킨 영역에 티타늄실리사이드막(34)을 형성하고, 그 상부에 베리어메탈(35)을 형성한다. 베리어메탈(35)은 티타늄나이트라이드막을 이용하여 형성한다.Subsequently, a portion of the upper portion of the contact plug 33 is recessed, the titanium silicide layer 34 is formed in the recessed region, and the barrier metal 35 is formed on the recess plug. The barrier metal 35 is formed using a titanium nitride film.
또한, 층간절연막(32)은 USG(Undoped-Silicate Glass)막, PSG(Phospho-Silicate Glass)막, BPSG(Boro-Phospho-Silicate Glass)막, HDP(High density Plasma) 산화막, SOG(Spin On Glass)막, TEOS(Tetra Ethyl Ortho Silicate)막 또는 HDP(high densigy plasma)를 이용한 산화막등을 사용하거나 열 산화막(Thermal Oxide; 퍼니스에서 600~1,100℃사이의 고온으로 실리콘 기판을 산화시켜 형성하는 막)으로 형성할 수 있다.In addition, the interlayer insulating film 32 may include an undoped-silicate glass (USG) film, a phospho-silicate glass (PSG) film, a boro-phospho-silicate glass (BPSG) film, a high density plasma (HDP) oxide film, and a spin on glass (SOG) film. Film, TEOS (Tetra Ethyl Ortho Silicate) film or HDP (high densigy plasma) oxide film, etc. or Thermal Oxide (Thermal Oxide) is formed by oxidizing silicon substrate at high temperature between 600 ~ 1,100 ℃ in furnace. It can be formed as.
이어서 캐패시터 형성용 절연막(36)을 캐패시터가 형성될 높이만큼 형성한다. 여기서 캐패시터 형성용 절연막(36)은 USG(Undoped-Silicate Glass)막, PSG(Phospho-Silicate Glass)막, BPSG(Boro-Phospho-Silicate Glass)막, HDP(High density Plasma) 산화막, SOG(Spin On Glass)막, TEOS(Tetra Ethyl Ortho Silicate)막 또는 HDP(high densigy plasma)를 이용한 산화막등을 사용하거나 열 산화막(Thermal Oxide; 퍼니스에서 600~1100℃사이의 고온으로 실리콘 기판을 산화시켜 형성하는 막)으로 형성할 수 있다.Subsequently, the capacitor formation insulating film 36 is formed to a height at which the capacitor is to be formed. The capacitor forming insulating film 36 may include an undoped-silicate glass (USG) film, a phospho-silicate glass (PSG) film, a boro-phospho-silicate glass (BPSG) film, a high density plasma (HDP) oxide film, and a spin on (SOG) film. A film formed by using a glass film, a TEOS (Tetra Ethyl Ortho Silicate) film or an oxide film using HDP (high densigy plasma), or by oxidizing a silicon substrate at a high temperature between 600 and 1100 ° C in a thermal oxide (furnace). ) Can be formed.
이어서 콘택플러그(33)의 상부의 베리어베탈(35)가 노출되도록 캐패시터 형성용 절연막(36)을 선택적으로 제거하여 캐패시터 형성용 홀(37)을 형성한다.Subsequently, the capacitor formation insulating layer 36 is selectively removed so that the barrier bezel 35 on the contact plug 33 is exposed to form the capacitor formation hole 37.
이어서 도2b에 도시된 바와 같이, 캐패시터 형성용 홀(37)의 내부에 도전성막으로 하부전극(38)을 50 ~ 500Å 범위의 두께로 형성한다. 하부전극(38)은 원자층증착법 또는 화학기상증착법 공정을 이용하여 도전성 실리콘막이나 이리듐, 루세늄, 이리듐옥사이드, 루세늄옥사이드, 티타늄질화막, 텅스텐, 텅스텐질화막, 백금, 탄탈늄질화막중에서 선택된 하나를 사용하여 형성한다.Subsequently, as shown in FIG. 2B, the lower electrode 38 is formed with a conductive film in the capacitor forming hole 37 to a thickness in the range of 50 to 500 mW. The lower electrode 38 may be one selected from a conductive silicon film, an iridium, ruthenium, iridium oxide, ruthenium oxide, titanium nitride film, tungsten, tungsten nitride film, platinum, and tantalum nitride film using atomic layer deposition or chemical vapor deposition. To form.
이어서 도2c에 도시된 바와 같이, 하부전극(38) 표면에 NH3리모트(remote) 플라즈마(plasma)을 이용하여 질화(39)시킨다. 리모트 플라즈마라고 하는 것을 기판의 상하부에 고전압을 인가하여 플라즈마를 형성시키는 것이 아니고, 다른 장비에서 여기된 플라즈마를 말하여, 리모트 플라즈마는 기판의 상하부에 고전압을 인가하여 생성한 플라즈마보다 직진성이 없고 플라즈마 래디칼들의 농도구배에 따른 확산에 의해 굴곡이 있는 웨이퍼 표면전체에 균일하게 도달하게 됨으로서 캐패시터형성용 홀의 측벽 전체를 고르게 질화처리할 수 있다.Next, as illustrated in FIG. 2C, nitride 39 is formed on the surface of the lower electrode 38 by using an NH 3 remote plasma. Remote plasma is not a plasma generated by applying a high voltage to the upper and lower portions of the substrate, and refers to a plasma excited by other equipment. By uniformly reaching the entire curved surface of the wafer by diffusion due to their concentration gradient, the entire sidewall of the capacitor forming hole can be evenly nitrided.
여기서의 공정조건은 웨이퍼온도는 250 ~ 650℃로 유지하고, 반응가스로 NH3또는 N2를 50sccm ~ 1000sccm로 사용하고, 반응로의 압력을 0.05Torr ~ 5Torr로 유지한다. 플라즈마를 형성하는 방법은 Microwave, ICP(inductively coupled Plamsa), ECR(Electron Cyclotron Resonance)등의 장비를 사용하여 500 ~ 5000W의 파워를 사용한다.In the process conditions here, the wafer temperature is maintained at 250 to 650 ° C., NH 3 or N 2 is used as the reaction gas at 50 sccm to 1000 sccm, and the pressure in the reactor is maintained at 0.05 Torr to 5 Torr. Plasma formation method uses power of 500 ~ 5000W by using equipment such as microwave, inductively coupled plasma (ICP), ECR (Electron Cyclotron Resonance).
이어서 도2d에 도시된 바와 같이, 질화된 하부전극(38) 상에 원자층증착법을 이용하여 Ta2O5막, Al2O3막, Al2O3/HfO2막, HfO2막, BST막등의 고유전체 물질이나, PZT막, PLZT막, SBT막, BLT막등 강유전체 물질을 유전체 박막(40) 으로 사용하여 30 ~ 300Å 범위로 형성한다. 유전체 박막(40)은 형성하는 공정은 웨이퍼온도를 250 ~ 500℃로 유지하고, 0.1Torr ~ 5Torr로 유지하고, 반응가스로 O2, O3, H2O를 사용하여 피딩(feeding)/퍼지(purge)하는 공정을 가지며 이 때 가스플로우(gas flow rate) 비율은 10 ~ 1000sccm 범위로 유지하며 공정을 진행한다.2D, a Ta 2 O 5 film, an Al 2 O 3 film, an Al 2 O 3 / HfO 2 film, an HfO 2 film, and a BST were deposited on the nitrided lower electrode 38 by using atomic layer deposition. A high dielectric material such as a film or a ferroelectric material such as a PZT film, a PLZT film, an SBT film, or a BLT film is used as the dielectric thin film 40 to form in the range of 30 to 300 Å. The process of forming the dielectric thin film 40 is maintained at a wafer temperature of 250 ~ 500 ℃, 0.1Torr ~ 5 Torr, feeding / purging using O 2 , O 3 , H 2 O as the reaction gas It has a process to purge and at this time the gas flow rate is maintained in the range of 10 ~ 1000sccm.
이어서 도2d에 도시된 바와 같이, 유전체박막(40)상에 상부전극(41)을 형성한다. 상부전극(40)은 Pt, Ir, Ru, RuO2, IrO2,TiN의 금속막을 사용하거나 또는 전도성 실리콘막을 사용하여 50 ~ 1000Å 범위로 형성한다.Subsequently, as shown in FIG. 2D, the upper electrode 41 is formed on the dielectric thin film 40. The upper electrode 40 is formed using a metal film of Pt, Ir, Ru, RuO 2 , IrO 2 , TiN, or using a conductive silicon film in a range of 50 to 1000 Å.
전술한 바와 같이 공정을 진행하게 되면 3차원 콘케이브구조의 하부전극(38)의 표면 전체-특히 하단부분과 측벽면까지 질화처리를 고르게 하게되면, 후속의 유전막 증착공정에서 발생하는 하부전극(38)과 유전체 박막(40)의 계면에 산화막 적층을 완전히 억제하여 캐패시터의 캐패시턴스 저하를 방지할 수 있다.As described above, if the entire surface of the lower electrode 38 of the three-dimensional concave structure, in particular, the lower portion and the sidewall surface is uniformly nitrided, the lower electrode 38 generated in the subsequent dielectric film deposition process is performed. ) And the reduction of the capacitance of the capacitor can be prevented by completely suppressing the deposition of the oxide film at the interface between the dielectric film 40 and the dielectric thin film 40.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
또한 전술한 실시예에서는 콘케이브형의 캐패시터에 대해서 설명하였으나, 실린더형의 캐패시터에도 적용가능하다.In addition, in the above-described embodiment, a concave type capacitor has been described, but it is also applicable to a cylindrical type capacitor.
본 발명에 의해서 전극막과 유전체박막 사이에 계면에 저유전율의 산화막 생성이 억제되어 고 유전율의 케패시터를 신뢰성있게 제조할 수 있다.According to the present invention, formation of a low dielectric constant oxide film at an interface between an electrode film and a dielectric thin film can be suppressed, and a high dielectric constant capacitor can be reliably manufactured.
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| US8012823B2 (en) | 2008-07-10 | 2011-09-06 | Samsung Electronics Co., Ltd. | Methods of fabricating stack type capacitors of semiconductor devices |
| KR20160069388A (en) * | 2014-12-08 | 2016-06-16 | (주)광진기계 | Apparatus for lifting car window |
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| KR100401503B1 (en) | 2001-04-30 | 2003-10-17 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR20020085109A (en) * | 2001-05-04 | 2002-11-16 | 삼성전자 주식회사 | Method of Manufacturing Capacitor of Semiconductor Device |
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| US8012823B2 (en) | 2008-07-10 | 2011-09-06 | Samsung Electronics Co., Ltd. | Methods of fabricating stack type capacitors of semiconductor devices |
| KR20160069388A (en) * | 2014-12-08 | 2016-06-16 | (주)광진기계 | Apparatus for lifting car window |
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