KR20040001902A - Method for fabricating capacitor in semiconductor device - Google Patents
Method for fabricating capacitor in semiconductor device Download PDFInfo
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- KR20040001902A KR20040001902A KR1020020037236A KR20020037236A KR20040001902A KR 20040001902 A KR20040001902 A KR 20040001902A KR 1020020037236 A KR1020020037236 A KR 1020020037236A KR 20020037236 A KR20020037236 A KR 20020037236A KR 20040001902 A KR20040001902 A KR 20040001902A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 제조기술에 관한 것으로, 특히 반도체 소자의 캐패시터제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.
반도체 소자, 특히 DRAM(Dynamic Random Access Memory)의 반도체 메모리의 집적도가 증가함에 따라 정보 기억을 위한 기본 단위인 메모리 셀의 면적이 급격하게 축소되고 있다.As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.
이러한 메모리 셀 면적의 축소는 셀 캐패시터의 면적 감소를 수반하여, 센싱 마진과 센싱 속도를 떨어뜨리고, α-입자에 의한 소프트 에러(Soft Error)에 대한 내구성이 저하되는 문제점을 유발하게 된다. 따라서, 제한된 셀 면적에서 충분한 정전용량을 확보할 수 있는 방안이 필요하게 되었다.Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.
캐패시터의 정전용량(C)은 하기의 수학식 1과 같이 정의된다.The capacitance C of the capacitor is defined as in Equation 1 below.
여기서, ε은 유전률, As는 전극의 유효 표면적, d는 전극간 거리를 각각 나타낸 것이다.Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.
따라서, 캐패시터의 정전용량을 늘리기 위해서는 전극의 표면적을 넓히거나,유전체 박막의 두께를 줄이거나, 유전률을 높여야 한다.Therefore, in order to increase the capacitance of the capacitor, the surface area of the electrode, the thickness of the dielectric thin film, or the dielectric constant must be increased.
이 중에서 전극의 표면적을 넓히는 방안이 제일 먼저 고려되어 왔다. 콘케이브(concave) 구조, 실린더(sylinder) 구조, 다층 핀(fin) 구조 등과 같은 3차원 구조의 캐패시터는 모두 제한된 레이아웃 면적에서 전극의 유효 표면적을 증대시키기 위하여 제안된 것이다. 그러나, 이러한 방법은 반도체 소자가 초고집적화 되면서 전극의 유효 표면적을 증대시키는데 한계를 보이고 있다.Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of electrodes in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.
그리고, 전극간 거리(d)를 최소화하기 위해 유전체 박막의 두께를 감소시키는 방안은 유전체 박막의 두께가 감소함에 따라 누설전류가 증가하는 문제 때문에 역시 그 한계에 직면하고 있다.In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.
따라서, 근래에 들어서는 주로 유전체 박막의 유전율의 증대를 통한 캐패시터의 정전용량 확보에 초점을 맞추어 연구, 개발이 진행되고 있다. 전통적으로, 실리콘산화막이나 실리콘질화막을 유전체 박막 재료로 사용한 소위 NO(Nitride-Oxide) 구조의 캐패시터가 주류를 이루었으나, 최근에는 Ta2O5, (Ba,Sr)TiO3(이하 BST라 함) 등의 고유전체 물질이나, (Pb,Zr)TiO3(이하 PZT라 함), (Pb,La)(Zr,Ti)O3(이하 PLZT라 함), SrBi2Ta2O9(이하 SBT라 함), SrBi2(Ta1-x,Nbx)2O9(이하 SBTN이라 함), Bi4-xLaxTi3O12(이하 BLT라 함), Bi4Ti3O12(이하, BIT라 함)등의 강유전체 물질을 유전체 박막 재료로 적용하고 있다.Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta 2 O 5 , (Ba, Sr) TiO 3 (hereinafter referred to as BST) High dielectric materials such as (Pb, Zr) TiO 3 (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O 3 (hereinafter referred to as PLZT), SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT) SrBi 2 (Ta 1-x , Nbx) 2 O 9 (hereinafter referred to as SBTN), Bi 4-x La x Ti 3 O 12 (hereinafter referred to as BLT), Bi 4 Ti 3 O 12 (hereinafter referred to as BIT Ferroelectric materials are applied as dielectric thin film materials.
이러한 고유전체 물질 또는 강유전체 물질을 유전체 박막 재료로 사용하는 고유전체 캐패시터 또는 강유전체 캐패시터를 제조함에 있어서, 고유전체 물질 또는 강유전체 물질 특유의 유전 특성을 구현하기 위해서는 유전체 주변 물질 및 공정(예컨대 고온열공정)의 적절한 제어가 수반되어야 한다.In the manufacture of high dielectric capacitors or ferroelectric capacitors using such high dielectric materials or ferroelectric materials as dielectric thin film materials, dielectric materials and processes (for example, high temperature and thermal processes) in order to realize dielectric properties unique to high dielectric materials or ferroelectric materials Proper control of the
일반적으로, 고유전체 캐패시터나 강유전체 캐패시터의 상, 하부전극 물질로서 노블메탈(noble metal) 또는 이들의 화합물, 예컨대 Pt, Ir, Ru, RuO2, IrO2등을 사용하고 있다.In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO 2 , IrO 2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.
도1a 내지 도1c는 종래기술에 의한 실린더형 캐패시터 제조방법을 나타내는 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a cylindrical capacitor according to the prior art.
먼저 도1a에 도시된 바와 같이, 활성영역(11)이 형성된 반도체기판(10)상에 층간절연막(12)을 형성한 후, 층간절연막(12)을 관통하여 반도체기판(10)의 활성영역(11)과 연결되는 콘택홀을 형성한다. 콘택홀을 도전성 물질로 매립하여 콘택플러그(13)를 형성한다. 이어서 캐패시터가 형성될 크기만큼 캐패시터절연막(14)을 형성한다. 이어서 콘택플러그(13)가 노출되도록 캐패시터절연막(14)을 선택적으로 식각하여 캐패시터홀(17)을 형성한다. 여기서 캐패시터 절연막(14)은 하부전극을 형성하도록 하는 거푸집역할을 한다.First, as shown in FIG. 1A, the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, and then penetrates the interlayer insulating film 12 to form an active region ( A contact hole connected to 11) is formed. A contact plug 13 is formed by filling the contact hole with a conductive material. Subsequently, the capacitor insulating film 14 is formed as large as the capacitor is formed. Subsequently, the capacitor insulating layer 14 is selectively etched to expose the contact plug 13 to form the capacitor hole 17. Here, the capacitor insulating film 14 serves as a form for forming the lower electrode.
이어서 도1b에 도시된 바와 같이, 캐패시터홀(17) 내부에 하부전극(15)을 형성하고, 캐패시터절연막(14)을 습식식각 공정을 이용하여 제거한다.Subsequently, as shown in FIG. 1B, the lower electrode 15 is formed in the capacitor hole 17, and the capacitor insulating film 14 is removed using a wet etching process.
이어서 도1c에 도시된 바와 같이, 하부전극(15)을 덮을 수 있도록 유전체 박막(16)을 형성한다. 여기서 유전체박막(16)으로는 Ta2O5보다 유전율 특성이 좋은 HfO2박막이나 Al2O3박막을 사용한다.Subsequently, as shown in FIG. 1C, the dielectric thin film 16 is formed to cover the lower electrode 15. As the dielectric thin film 16, an HfO 2 thin film or an Al 2 O 3 thin film having better dielectric constant than Ta 2 O 5 is used.
그러나 HfO2박막의 경우 Al2O3박막에 비해 큰 유전율을 가지고 있는 것으로 알려져 있으나 HfO2박막만으로는 누설전류 특성을 만족시키지 못하는 문제점을 가지고 있다. 또한 한편으로 Al2O3박막은 우수한 누설전류 특성으로 인해 사용하고 있으나 HfO2박막 보다 유전율이 크지 않아 점점더 고집된화되는 반도체 장치에 사용하기에는 문제점을 보이고 있다.However, the HfO 2 thin film is known to have a higher dielectric constant than the Al 2 O 3 thin film, but the HfO 2 thin film alone does not satisfy the leakage current characteristics. On the other hand, Al 2 O 3 thin films are used because of their excellent leakage current characteristics. However, the Al 2 O 3 thin films do not have a higher dielectric constant than HfO 2 thin films, and thus have been shown to be used in semiconductor devices, which are increasingly highly integrated.
따라서 HfO2박막 또는 Al2O3박막을 각각 유전체 박막으로 사용하여 캐패시터를 형성할 경우에는 고집적 반도체 장치, 즉 512M,1G 디램등에서 요구하는 캐패시턴스나 누설전류 특성을 만족할 수 없다.Therefore, when the capacitor is formed using the HfO 2 thin film or the Al 2 O 3 thin film as the dielectric thin film, the capacitance and leakage current characteristics required for the highly integrated semiconductor device, ie, 512M, 1G DRAM, etc. cannot be satisfied.
본 발명은 누설전류특성이 우수하고, 높은 캐패시턴스를 유지하면서도 안정적인 공정으로 제조할 수 있는 고집적 캐패시터 제조방법을 제공함을 목적으로 한다.An object of the present invention is to provide a highly integrated capacitor manufacturing method which can be manufactured in a stable process while maintaining excellent leakage current characteristics and high capacitance.
도1a 내지 도1c는 종래기술에 의한 실린더형 캐패시터 제조방법을 나타내는 공정단면도.1A to 1C are cross-sectional views showing a method of manufacturing a cylindrical capacitor according to the prior art.
도2a 내지 도2d는 본 발명의 바람직한 실시예에 따른 반도체 캐패시터 제조방법을 나타내는 공정단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor capacitor in accordance with a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
20 : 기판20: substrate
21 : 활성영역21: active area
22: 층간절연막22: interlayer insulating film
23: 콘택플러그23: Contact Plug
24 : 캐패시터절연막24: capacitor insulating film
25 : 하부전극25: lower electrode
26 : 확산방지막26: diffusion barrier
27 : 유전체 박막27: dielectric thin film
28 : 상부전극28: upper electrode
상기의 목적을 달성하기 위한 본 발명은 기판 상에 하부전극을 형성하는 단계; 상기 하부전극 상에 Al2O3과 HfO2이 혼합된 유전체 박막을 형성하는 단계; 및 상기 유전체 박막상에 상부전극을 형성하는 단계를 포함하는 반도체 장치의 캐패시터 제조방법이 제공된다.The present invention for achieving the above object comprises the steps of forming a lower electrode on the substrate; Forming a dielectric thin film mixed with Al 2 O 3 and HfO 2 on the lower electrode; And forming an upper electrode on the dielectric thin film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2d는 본 발명에 의한 바람직한 실시예에 따른 반도체장치의 캐패시터 제조방법을 나타내는 도면이다.2A to 2D are views showing a capacitor manufacturing method of a semiconductor device according to a preferred embodiment of the present invention.
먼저 도2a에 도시된 바와 같이, 활성영역(21)이 형성된 반도체기판(20)상에 층간절연막(22)을 형성한 후, 층간절연막(22)을 관통하여 반도체기판(20)의 활성영역(21)과 연결되는 콘택홀을 형성한다. 이어서 콘택홀을 도전성 물질로 매립하여 콘택플러그(23)를 형성한다. 여기서 도시되지는 않았으나, 콘택홀 내부에 Ti막을 증착하고 열공정을 실시하여 활성영역(21)과의 계면에 오믹 콘택을 위한 티타늄실리사이드를 형성한다.First, as shown in FIG. 2A, the interlayer insulating film 22 is formed on the semiconductor substrate 20 on which the active region 21 is formed, and then penetrates the interlayer insulating film 22 to form the active region of the semiconductor substrate 20 ( A contact hole connected to 21 is formed. Subsequently, the contact hole is filled with a conductive material to form the contact plug 23. Although not shown here, a Ti film is deposited inside the contact hole and a thermal process is performed to form titanium silicide for ohmic contact at the interface with the active region 21.
이어서 텅스텐을 콘택홀에 매립하여 텅스텐 콘택플러그(23)를 형성한다.Subsequently, tungsten is embedded in the contact hole to form the tungsten contact plug 23.
이어서 캐패시터 형성을 위한 캐패시터 절연막(24)을 형성하고, 콘택플러그(23)가 노출되도록 캐패시터절연막(24)를 선택적으로 제거하여 캐패시터홀을 형성한다. 여기서 캐패시터 절연막(24)는 USG(Undoped-Silicate Glass), PSG(Phospho-Silicate Glass), BPSG(Boro-Phospho-Silicate Glass), HDP(High density Plasma) 산화막등을 사용하여 형성할 수 있다.Subsequently, a capacitor insulating film 24 for forming a capacitor is formed, and the capacitor insulating film 24 is selectively removed so that the contact plug 23 is exposed to form a capacitor hole. The capacitor insulating film 24 may be formed using USG (Undoped-Silicate Glass), PSG (Phospho-Silicate Glass), BPSG (Boro-Phospho-Silicate Glass), HDP (High density Plasma) oxide film, or the like.
이어서 도2b에 도시된 바와 같이, 캐패시터 홀내부에 폴리실리콘막으로 하부전극(25)을 형성하고, 캐패시터 절연막(24)을 제거한다. 하부전극(25)으로 형성한 폴리실리콘막에 인시츄(In-situ)로 PH3가스를 이용하여 P를 3.0E20 atoms/cc로 되도록 도핑한다.Subsequently, as shown in FIG. 2B, the lower electrode 25 is formed of a polysilicon film in the capacitor hole, and the capacitor insulating film 24 is removed. The polysilicon film formed of the lower electrode 25 is doped in-situ so that P is 3.0E20 atoms / cc using a PH 3 gas.
이어서 도2c에 도시된 바와 같이, 유전체박막(26)으로 HfO2와 Al2O3박막을 혼합하여 형성한다. 이때 유전체박막(26) 형성전 하부전극의 표면을 산소 또는 OH로 종말(termination)시켜 주기 위해, HF 세정공정후 SC-1 용액으로 세정공정을 진행하거나 급속열산화(Rapid Thermal Oxidation:RTO) 공정 또는 오존 처리를 하여준다.Subsequently, as shown in FIG. 2C, the dielectric thin film 26 is formed by mixing the HfO 2 and Al 2 O 3 thin films. At this time, in order to terminate the surface of the lower electrode with oxygen or OH before the dielectric thin film 26 is formed, a cleaning process is performed with an SC-1 solution after a HF cleaning process or a rapid thermal oxidation (RTO) process. Or ozone treatment.
유전체박막(26)은 Hafnium(HfCl4)와 Tri-methyl Aluminum((CH3)3Al)을 소스 물질로 H2O 또는 O3를 반응가스로 하여 원자층증착 방법을 이용하여 Al2O3와 HfO2의 혼합막을 30 ~ 80Å 범위로 증착하여 형성한다. 이 때 퍼지가스(purge gas)로는 N2나 Ar가스를 사용한다. Al2O3박막과 HfO2박막이 혼합된 유전체 박막은 Hf원자사이에 Al을 자리잡게 하여 보다 조밀한 유전체 박막을 형성할 수 있다. 이를 자세히 살펴보면, 원자층증착법에서 소스 피딩(feeding)시 Al과 Hf의 소스를 같이 피딩하여 주면, Hf원자들사이에 크기가 작은 Al원자가 자리를 잡게 되고, 그후 반응 가스를 주입하면 HfO2와 Al2O3의 혼합층이 형성되는 것이다. 또한 HfO2의 소스물질로 Hf(NO3)4, Hf(C5H702)4를 사용할 수 있으며 Al의 소스물질로 MTMA((CH3)3Al(C2H5)5(CH3)3)를 사용할수 있으며, 유전체 박막은 플라즈마인핸스드(Plasma enhanced) 원자층증착법으로 형성 할 수 있다.The dielectric thin film 26 is made of Al 2 O 3 using atomic layer deposition method using Hafnium (HfCl 4 ) and Tri-methyl Aluminum ((CH 3 ) 3 Al) as the source material and H 2 O or O 3 as the reaction gas. And a mixed film of HfO 2 are formed by depositing in the range of 30 ~ 80Å. At this time, N 2 or Ar gas is used as the purge gas. The dielectric thin film in which the Al 2 O 3 thin film and the HfO 2 thin film are mixed may form Al between the Hf atoms to form a denser dielectric thin film. In detail, if Al and Hf source are fed together during source feeding in atomic layer deposition, small Al atoms are placed between Hf atoms, and then HfO 2 and Al are injected when reactant gas is injected. A mixed layer of 2 O 3 is formed. In addition, Hf (NO 3 ) 4 and Hf (C 5 H 7 0 2 ) 4 can be used as the source material of HfO 2 and MTMA ((CH 3 ) 3 Al (C 2 H 5 ) 5 (CH 3 ) 3 ) can be used, and the dielectric thin film can be formed by plasma enhanced atomic layer deposition.
이어서 Al2O3와 HfO2의 혼합막 증착후 박막의 조밀화 및 표면에 소스가스로 인해 형성된 탄소(CARBON)를 제거하기 위해 N2O 또는 O2플라즈마 처리나 또는 N2O 분위기에서 로(furnace) 열처리 공정을 진행한다.Subsequently, after the deposition of the mixed film of Al 2 O 3 and HfO 2 , the thin film is densified and the furnace is heated in an N 2 O or O 2 plasma or N 2 O atmosphere to remove carbon formed by the source gas on the surface. ) The heat treatment process is performed.
이어서 도2d에 도시된 바와 같이, Al2O3와 HfO2의 혼합막과 후속공정에서 형성된 상부전극과의 상호간 물질확산방지막(27)으로 TiN막을 형성한다. TiN막 형성방법은 TiCl4, NH3를 반응가스로 하고, 450℃ ~ 630℃의 온도범위에서 증착한다.Next, as shown in FIG. 2D, a TiN film is formed of a material diffusion preventing film 27 between the mixed film of Al 2 O 3 and HfO 2 and the upper electrode formed in a subsequent step. In the TiN film forming method, TiCl 4 and NH 3 are used as a reaction gas and deposited at a temperature ranging from 450 ° C. to 630 ° C.
이어서 상부전극(28)으로 폴리실리콘막을 1000Å으로 형성한다. 상부전극(28)으로 형성한 폴리실리콘막에 인시츄(In-situ)로 PH3가스를 이용하여 P를 3.0E20 atoms/cc로 유지하도록 도핑한다.Subsequently, a polysilicon film is formed on the upper electrode 28 at 1000 Å. The polysilicon film formed of the upper electrode 28 is doped to maintain P at 3.0E20 atoms / cc using a PH 3 gas in-situ.
따라서 본 발명에 의해 누설전류 특성이 우수한 Al2O3박막과 유전율이 높은 HfO2박막이 혼합되어 유전체 박막으로 사용되어 캐패시턴스가 크면서도 누설전류특성이 우수한 캐패시터를 제조할 수 있다. 특히 단원자층 공정 방법을 이용하여 저온에서 박막을 형성할 수 있어 종래의 주로 사용하던 화학적기상증착법(CVD)로 Ta2O5박막 사용시보다 안정된 박막계면을 유지 할 수 있어 계면 산화막 형성을 억제할 수 있다. 즉 유전체박막으로 널리사용되는 화학적기상증착법(CVD)로 형성한 Ta2O5박막과 하부전극인 폴리실리콘막과의 계면 생성물 형성으로 인한 캐패시턴서 저하를 본발명에서는 막을 수 있다.Therefore, according to the present invention, an Al 2 O 3 thin film having excellent leakage current characteristics and an HfO 2 thin film having a high dielectric constant are mixed and used as a dielectric thin film, whereby a capacitor having a large capacitance and excellent leakage current characteristics can be manufactured. In particular, section jacheung step method to form a thin film at a low temperature by using it is possible to maintain a stable thin film surface than when using Ta 2 O 5 thin films by chemical vapor deposition (CVD) was conventionally mainly used for it is possible to suppress the interface between the oxide film-forming have. In other words, in the present invention, the reduction of the capacitor due to the formation of an interfacial product between the Ta 2 O 5 thin film formed by chemical vapor deposition (CVD), which is widely used as a dielectric thin film, and the polysilicon film, which is a lower electrode, can be prevented.
또한, Al2O3과 HfO2이 혼합된 유전체 박막으로 하부전극과 유전체사이의 안정된 계면의 유지는 고유전율 확보에 필수적인 고온산화열처리에 대한, 열적 공정마진을 확대시킬 수 있는 장점이 있다.In addition, maintaining a stable interface between the lower electrode and the dielectric with the Al 2 O 3 and HfO 2 mixed thin film has the advantage that the thermal process margin for the high temperature oxidation heat treatment, which is essential for securing a high dielectric constant.
따라서 본 발명에 의해 지금 512M나 1G디램에서 요구하는 캐패시터의 유전막 특성을 만족시킬 수 있어 새로운 공정개발 비용없이도 고집적 반도체 장치를 개발할 수 있다.Therefore, the present invention can satisfy the dielectric film characteristics of the capacitor required by the current 512M or 1G DRAM, so that a highly integrated semiconductor device can be developed without a new process development cost.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 의해 추가비용없이 누설전류특성과 유전율특성이 우수한 안정적인 고집적 반도체 장치의 캐패시터 장치를 제조할 수 있다.According to the present invention, it is possible to manufacture a stable high integration semiconductor device capacitor device having excellent leakage current characteristics and dielectric constant characteristics without additional cost.
Claims (8)
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| US7229888B2 (en) | 2003-11-22 | 2007-06-12 | Hynix Semiconductor Inc. | Capacitor with hafnium oxide and aluminum oxide alloyed dielectric layer and method for fabricating the same |
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| US7229888B2 (en) | 2003-11-22 | 2007-06-12 | Hynix Semiconductor Inc. | Capacitor with hafnium oxide and aluminum oxide alloyed dielectric layer and method for fabricating the same |
| US7416936B2 (en) | 2003-11-22 | 2008-08-26 | Hynix Semiconductor Inc. | Capacitor with hafnium oxide and aluminum oxide alloyed dielectric layer and method for fabricating the same |
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