KR100519514B1 - Method of forming capacitor provied with TaON dielectric layer - Google Patents
Method of forming capacitor provied with TaON dielectric layer Download PDFInfo
- Publication number
- KR100519514B1 KR100519514B1 KR10-1999-0026503A KR19990026503A KR100519514B1 KR 100519514 B1 KR100519514 B1 KR 100519514B1 KR 19990026503 A KR19990026503 A KR 19990026503A KR 100519514 B1 KR100519514 B1 KR 100519514B1
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- lower electrode
- taon
- electrode
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02249—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by combined oxidation and nitridation performed simultaneously
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
- Formation Of Insulating Films (AREA)
Abstract
고유전체 TaON막으로 이루어진 반도체장치의 커패시터 제조방법에 대해 개시되어 있다. 이 방법은 반도체 소자를 구비한 반도체기판 상부에 소자간 절연을 위한 층간절연막의 콘택홀을 통해서 반도체 소자와 접하는 도전성의 하부전극을 형성하고, 하부전극 상부면에 전극의 산화를 방지하면서 누설 전류 특성이 양호한 SiON박막을 형성하고, SiON박막 상부면에 고유전체 TaON박막을 형성한 후에, TaON박막 상부면에 도전성의 상부전극을 형성한다. 이에 따라, 본 발명은 도프트 폴리실리콘의 하부전극 상부면에 플라즈마 분위기에서 NH3와 O2(또는 N2O)를 사용하여 SiON박막을 형성함으로써 후속 공정시 하부전극의 산화를 방지하면서 누설전류에 대한 강한 내성을 가진다.A capacitor manufacturing method of a semiconductor device composed of a high dielectric TaON film is disclosed. This method forms a conductive lower electrode in contact with a semiconductor element through a contact hole of an interlayer insulating film for inter-element insulation on a semiconductor substrate having a semiconductor element, and prevents oxidation of the electrode on the upper surface of the lower electrode while preventing leakage current characteristics. After forming this favorable SiON thin film and forming a high dielectric TaON thin film on the SiON thin film upper surface, a conductive upper electrode is formed on the TaON thin film upper surface. Accordingly, the present invention forms a SiON thin film using NH 3 and O 2 (or N 2 O) in the plasma atmosphere on the upper surface of the lower electrode of the doped polysilicon to prevent oxidation of the lower electrode during the subsequent process while preventing leakage current. Has strong resistance to
Description
본 발명은 반도체 장치의 커패시터 제조방법에 관한 것으로서, 특히 커패시터의 용량 및 전기적 특성을 향상시킬 수 있도록 고유전체의 TaON를 갖는 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor having TaON of a high dielectric material so as to improve the capacity and electrical characteristics of the capacitor.
현재 반도체 소자의 고집적화를 달성하기 위하여 셀 면적의 감소 및 동작 전압의 저전압화에 관한 연구/개발이 활발하게 진행되고 있다. 더구나 반도체 소자의 고집적화가 이루어질수록 커패시터의 면적이 급격하게 감소되지만 기억소자의 동작에 필요한 전하 즉, 단위 면적에 확보되는 커패시턴스는 증가되어야만 한다.In order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices increases, the area of the capacitor decreases drastically, but the charge required for the operation of the memory device, that is, the capacitance secured in the unit area must be increased.
이를 위해 커패시터의 충분한 용량을 확보하기 위해서 통상의 실린더 구조 변경을 통해 커패시터 면적을 증가하거나 유전체막의 두께 감소를 통해 충분한 커패시턴스를 확보시키는 방법이 이루어지고 있으며, 기존 실리콘 산화막으로 사용하던 유전체막을 NO(Nitride-Oxide) 또는 ONO(Oxide-Nitride-Oxide)구조라든지 높은 커패시턴스(유전상수=20∼25)를 확보할 수 있는 Ta2O5, TaON 내지 BST(BaSrTiO3) 등으로 대체하려는 재료적인 연구가 진행되고 있다.To this end, in order to secure a sufficient capacity of the capacitor, a method of securing a sufficient capacitance by increasing the capacitor area or reducing the thickness of the dielectric film by changing a conventional cylinder structure is being performed. The dielectric film used as a conventional silicon oxide film is NO (Nitride). -Oxide) or ONO (Oxide-Nitride-Oxide) structure or material research to replace with Ta 2 O 5 , TaON to BST (BaSrTiO 3 ) which can secure high capacitance (dielectric constant = 20-25) It is becoming.
한편, 최근에는 NO유전체를 갖는 커패시터가 256M 이상의 차세대 메모리에 필요한 용량을 확보하는데 한계를 보이고 있기 때문에 Ta2O5 유전체 개발이 연구 진행중에 있다. 하지만, 이 Ta2O5 박막 역시 불안정한 화학양론비(stoichiometry)를 갖고 있어 Ta와 O의 조성비 차이에 기인한 치환형 Ta원자가 박막내에 존재하기 때문에 유전체박막 공정시 Ta2O5의 전구체인 Ta(OC2H5)5의 유기물과 O2(또는 N2O)가스의 반응으로 인해 불순물인 탄소원자와 탄소화합물(C, CH4, C2H4 등) 및 물(H 2O)이 생성된다. 결국, Ta2O5 박막내에 불순물로 존재하는 탄소원자, 이온과 라디칼로 인해서 커패시터의 누설전류가 증가하게 되고 유전특성이 열화된다. 이러한 Ta2O5 박막내의 불순물을 제거하기 위하여 저온 열처리(예를 들면, plasma N2O 또는 UV-O3)를 이중, 삼중으로 처리하고 있지만 이 역시 제조 과정이 복잡하며 Ta2O5 박막의 산화 저항성이 낮기 때문에 하부전극의 산화가 발생하게 된다.On the other hand, Ta 2 O 5 dielectric development is currently under study because the capacitor having a NO dielectric shows a limit in securing the capacity required for the next-generation memory of more than 256M. However, this Ta 2 O 5 thin film also has an unstable stoichiometry, and because Ta-type substituted Ta atoms exist in the thin film due to the difference in the composition ratio of Ta and O, Ta (the precursor of Ta 2 O 5 in the dielectric thin film process) Reaction of organic compounds of OC 2 H 5 ) 5 with O 2 (or N 2 O) gas produces impurities such as carbon atoms, carbon compounds (C, CH 4 , C 2 H 4, etc.) and water (H 2 O) do. As a result, the leakage current of the capacitor increases and dielectric properties deteriorate due to the carbon atoms, ions and radicals present as impurities in the Ta 2 O 5 thin film. A low temperature in order to remove the impurities in such a Ta 2 O 5 thin film heat-treating (e.g., plasma N 2 O or a UV-O 3) a double, and triple-treatment with, but is too complicated manufacturing process, and the Ta 2 O 5 thin film Since the oxidation resistance is low, oxidation of the lower electrode occurs.
이러한 Ta2O5 박막의 불안정한 화학양론비를 개선하기 위하여 최근에 개발이 이루어지고 있는 TaON 유전체박막은 도프트 폴리실리콘이 증착된 하부전극 위에 기존에 유전체박막으로 자주 이용되던 Ta2O5의 근원물질인 Ta(OC2H5)5에 O2와 NH3를 첨가하여 금속유기화학기상증착법(metal-organic chemical vapor deposition)으로 증착하였다. 하지만, TaON박막은 Ta2O5에 비해 산화저항 특성은 우수하지만 하부전극에 대한 산화 특성은 불량하여 이를 방지하기 위한 NH3 전처리가 진행되고 있다. 기존의 NH3 전처리 방법은, 850℃∼950℃의 온도에서 30초∼1분정도로 하부전극의 NH3처리가 실시된다. 이에 하부전극의 폴리실리콘막 표면에 수십 Å이하의 실리콘질화박막이 형성되고 이 막은 후속 공정의 산소 분위기에서 산화 반응을 일으켜 하부전극 표면이 산화되는 것을 막아준다. 그러나, 이러한 질화처리 공정은 고온에서 실시되므로 다른 반도체 소자의 특성에 영향을 주게 되는 단점이 있다. 또한, 질화처리 공정에 의해 하부전극 상부면에 형성된 실리콘질화박막은 저유전율의 실리콘산화막의 형성을 방지하여 커패시터의 용량을 유지하는데에는 효과가 있으나 누설전류 감소를 위한 방지 기능의 역할은 한계가 있었다.The TaON dielectric thin film, which has been recently developed to improve the unstable stoichiometry of such Ta 2 O 5 thin films, is the source of Ta 2 O 5 , which is often used as a dielectric thin film on the lower electrode on which doped polysilicon is deposited. O ( 2) and NH 3 were added to Ta (OC 2 H 5 ) 5, which was deposited by metal-organic chemical vapor deposition. However, TaON thin film has better oxidation resistance than Ta 2 O 5 , but poor oxidation property for the lower electrode, and NH 3 pretreatment is being performed to prevent this. In the conventional NH 3 pretreatment method, the NH 3 treatment of the lower electrode is performed at a temperature of 850 ° C to 950 ° C for about 30 seconds to 1 minute. Accordingly, a silicon nitride thin film of several tens of kPa or less is formed on the surface of the polysilicon film of the lower electrode, and this film prevents oxidation of the lower electrode surface by causing an oxidation reaction in an oxygen atmosphere of a subsequent process. However, since the nitriding process is performed at a high temperature, there is a disadvantage in that it affects the characteristics of other semiconductor devices. In addition, the silicon nitride thin film formed on the upper surface of the lower electrode by the nitriding process is effective in maintaining the capacitance of the capacitor by preventing the formation of a low dielectric constant silicon oxide film, but the role of the prevention function for reducing the leakage current was limited. .
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 유전율이 높은 TaON을 이용한 커패시터 제조 공정시 도프트 폴리실리콘의 하부전극 상부면에 플라즈마 분위기에서 NH3와 O2(또는 N2O)를 사용하여 SiON박막을 형성함으로써 후속 공정시 하부전극의 산화를 방지하면서 누설전류에 대한 강한 내성을 가지고 있는 TaON박막을 갖는 커패시터 제조방법을 제공하는데 있다.An object of the present invention to solve the problems of the prior art as described above NH 3 and O 2 (or N 2 O) in the plasma atmosphere on the upper surface of the lower electrode of the doped polysilicon during the capacitor manufacturing process using a high dielectric constant TaON The present invention provides a method of manufacturing a capacitor having a TaON thin film having a strong resistance to leakage current while preventing the oxidation of the lower electrode in a subsequent process by forming a SiON thin film.
상기 목적을 달성하기 위하여 본 발명은 반도체기판의 활성영역과 접촉하는 하부 전극과 그 위의 상부전극 및 상기 전극들 사이에 내재된 고유전체 TaON박막으로 이루어진 커패시터의 제조 공정에 있어서, 반도체 소자를 구비한 반도체기판 상부에 소자간 절연을 위한 층간절연막의 콘택홀을 통해서 반도체 소자와 접하며 도전층으로 이루어진 하부전극을 형성하는 단계와, 하부전극 상부면에 전극의 산화를 방지하기 위한 SiON박막을 형성하는 단계와, SiON박막 상부면에 고유전체 TaON박막을 형성하는 단계와, TaON박막 상부면에 도전층으로 이루어진 상부전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor device in a capacitor manufacturing process comprising a lower electrode in contact with an active region of a semiconductor substrate, an upper electrode thereon, and a high dielectric TaON thin film embedded between the electrodes. Forming a lower electrode made of a conductive layer in contact with a semiconductor device through a contact hole of an interlayer insulating film for inter-element insulation on an upper surface of the semiconductor substrate, and forming a SiON thin film on the upper surface of the lower electrode to prevent oxidation of the electrode; And forming a high dielectric TaON thin film on the upper surface of the SiON thin film, and forming an upper electrode made of a conductive layer on the upper surface of the TaON thin film.
본 발명에 따르면, TaON 박막을 갖는 커패시터 제조 공정시 하부전극 형성후에, 하부전극에 대한 산화 특성을 양호하게 하기 위해서 플라즈마 분위기에서 NH3와 O2(또는 N2O)를 사용하여 SiON박막을 형성함으로써, 하부전극 상부면의 산화 반응을 억제하면서 누설 전류 감소를 방지하는 역할을 한다.According to the present invention, after forming a lower electrode in a capacitor manufacturing process having a TaON thin film, a SiON thin film is formed using NH 3 and O 2 (or N 2 O) in a plasma atmosphere in order to improve oxidation characteristics of the lower electrode. As a result, the leakage current is prevented while suppressing the oxidation reaction of the upper surface of the lower electrode.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 고유전체 TaON을 갖는 반도체장치의 커패시터 제조방법을 순서적으로 설명하기 위한 공정 순서도이다.1 to 4 are process flowcharts for sequentially explaining a capacitor manufacturing method of a semiconductor device having a high dielectric TaON according to the present invention.
도 1에 도시된 바와 같이, 반도체기판으로서 실리콘기판(10)의 활성 영역 상부면에 게이트 전극, 소스/드레인 등을 갖는 반도체소자(도시하지 않음)를 형성하고, 그 기판(10) 전면에 USG(Undoped Silicate Glass), BPSG(Boro Phospho Silicate Glass) 및 SiON 중에서 선택한 물질을 증착하고 화학적기계적연마(Chemical Mechanical Polishing) 공정을 실시하여 평탄화된 층간절연막(20)을 형성한다. 기판(10)의 활성영역 즉, 드레인 영역과 접촉하는 커패시터의 단면적을 확보하기 위하여 사진 및 식각 공정으로 층간절연막(20)을 선택 식각하여 콘택홀(도시하지 않음)을 형성한다. As shown in FIG. 1, a semiconductor device (not shown) having a gate electrode, a source / drain, or the like is formed on an upper surface of an active region of a silicon substrate 10 as a semiconductor substrate, and USG is formed on the entire surface of the substrate 10. (Undoped Silicate Glass), BPSG (Boro Phospho Silicate Glass) and SiON material selected from the deposition and chemical mechanical polishing (Chemical Mechanical Polishing) process is performed to form a planarized interlayer insulating film (20). In order to secure the cross-sectional area of the capacitor in contact with the active region of the substrate 10, that is, the drain region, the interlayer insulating layer 20 is selectively etched by photolithography and etching to form a contact hole (not shown).
그리고, 상기 콘택홀내에 도전층으로서 도프트 폴리 실리콘 내지 비정질 실리콘을 증착하여 하부전극(30)을 형성한다. 이때, 커패시터의 하부전극 구조는 스택, 실린더, 핀, 스택실린더 중에서 어느 하나로 하며 특히 본 실시예에서는 실린더 형태로 형성하기로 한다. 한편, 도면에 도시하지는 않았지만, 하부전극의 평면적을 늘리기 위하여 상부면이 HSG(Hemi Sperical Grain) 형태를 갖는 하부전극을 형성할 수도 있다. 즉, 상기 콘택홀을 갖는 층간절연막(20) 전면에 도전물질로서 비정질의 도프트 실리콘을 매립하도록 증착하고 식각 공정을 이용하여 이 실리콘층을 실린더 구조 형태로 패터닝한 후에 결정화 온도 이하 상태에서 전극의 상부면에 비정질 상태의 시드(seed)를 반구형 요철형태로 성장시켜서 HSG 구조의 하부전극(30)을 형성한다. 그리고 나서, 하부전극(30)에 충분한 P(phosphorus)를 공급, 예를 들어 1×10E20/㎤ 이상의 농도를 가지도록 하기 위하여 PH3처리를 실시해준다.The lower electrode 30 is formed by depositing doped polysilicon or amorphous silicon as the conductive layer in the contact hole. In this case, the lower electrode structure of the capacitor is any one of a stack, a cylinder, a pin, and a stack cylinder, and in particular, in the present embodiment, it is formed in the form of a cylinder. Although not shown in the drawing, in order to increase the planar area of the lower electrode, an upper surface may form a lower electrode having a HSG (Hemi Sperical Grain) shape. That is, depositing amorphous doped silicon as a conductive material on the entire surface of the interlayer insulating film 20 having the contact hole and patterning the silicon layer in a cylindrical structure by using an etching process. An amorphous seed is grown on the top surface in a hemispherical irregular shape to form the bottom electrode 30 of the HSG structure. Then, a sufficient P (phosphorus) is supplied to the lower electrode 30, for example, PH 3 treatment is performed to have a concentration of 1 × 10 E 20 / cm 3 or more.
이어서, 도 2에 도시된 바와 같이, 후속 TaON박막의 증착공정시 하부전극(30)의 산화를 방지하면서 누설 전류 특성을 높이기 위해서 SiON박막(32)을 형성한다. 상기 공정은, 저압화학기상증착(low pressure chemical vapor deposition) 챔버에서 인시튜(in-situ)공정으로 200℃∼600℃ 온도에서 플라즈마를 이용하여 NH3와 함께 O2 가스(또는 N2O)를 공급해서 하부전극(30)의 표면을 질산화시킨다. 이때 공정은, NH3와 O2 가스를 10sccm∼1000sccm으로 각각 정량을 공급하고, 하부전극 표면에 산화막의 생성을 억제하기 위해서 NH3가스를 먼저 주입하고 O2 내지 N2O 가스를 후에 주입하도록 한다. 이로 인해, 급속 열처리 공정에 의한 질화처리보다 저온에서 진행되기 때문에 이미 형성되어 있는 트랜지스터 등의 다른 소자의 전기적 특성 열화를 방지할 수 있다.Subsequently, as shown in FIG. 2, in order to prevent leakage of the lower electrode 30 during the subsequent deposition process of the TaON thin film, a SiON thin film 32 is formed to increase leakage current characteristics. The process is an in-situ process in a low pressure chemical vapor deposition chamber with an O 2 gas (or N 2 O) together with NH 3 using a plasma at a temperature of 200 ° C. to 600 ° C. Is supplied to nitrify the surface of the lower electrode 30. In this process, the NH 3 and O 2 gas is supplied at 10 sccm to 1000 sccm, respectively, in order to suppress the formation of the oxide film on the lower electrode surface, the NH 3 gas is first injected and the O 2 to N 2 O gas is injected later. do. For this reason, since it advances at low temperature rather than the nitriding process by a rapid heat processing process, deterioration of the electrical characteristic of other elements, such as a transistor which is already formed, can be prevented.
그 다음, 도 3에 도시된 바와 같이, 상기 SiON박막(32) 상부면에 Ta 화학증기와 반응 가스 O2 및 NH3를 공급해서 TaON을 80Å∼200Å정도 증착함으로써 고유전체 TaON박막(34)을 형성한다. 이때의 공정은, 웨이퍼에서 일어나는 표면 화학반응(surface chemical reaction)을 통해 비정질 TaON박막을 형성하고, 보다 상세하게는 기상반응(gas phase reaction)을 억제시키면서 다음과 같은 화학증기를 사용하여 비정질 TaON박막을 증착시킨다.3, the TaON thin film 34 is formed by supplying Ta chemical vapor and reactant gases O 2 and NH 3 to the upper surface of the SiON thin film 32 and depositing TaON by about 80 to 200 mW. Form. In this process, the amorphous TaON thin film is formed by the surface chemical reaction occurring on the wafer, and more specifically, the amorphous TaON thin film using chemical vapor as follows while suppressing the gas phase reaction. Is deposited.
먼저, Ta성분의 화학증기는 Ta(OC2H5)5과 같은 Ta화합물을 질량 유량제어기(MFC, Mass Flow Controller)를 통해서 정량된 양을 증발기 또는 증발관으로 공급한 후에 일정량을 150℃∼200℃의 온도 범위에서 증발시켜서 얻는다. 이와 같은 방법을 통해 얻어진 Ta의 화학증기와 반응가스인 O2와 NH3를 10sccm∼1000sccm 정도 사용하고 300℃∼600℃의 저압 화학기상증착용 챔버내에서 표면반응시키면 비정질 TaON박막이 형성된다.First, the chemical vapor of Ta component supplies Ta compound such as Ta (OC 2 H 5 ) 5 to the evaporator or the evaporator after supplying the quantified amount through a mass flow controller (MFC). Obtained by evaporation in the temperature range of 200 degreeC. When the chemical vapor of Ta and the reaction gas O 2 and NH 3 obtained through the above method are used at about 10 sccm to 1000 sccm, and surface reacted in a low pressure chemical vapor deposition chamber at 300 ° C. to 600 ° C., an amorphous TaON thin film is formed.
본 실시예에서는 부가적으로 고유전체 TaON박막(34)의 고밀도화를 위해서, 비정질의 TaON박막(34) 상부에 인시튜 또는 엑스시튜(ex-situ)에서 플라즈마를 이용하여 200℃∼600℃, NH3 분위기에서 표면을 질화시키거나 또는 N2O(O2) 분위기에서 질산화처리하여 계면의 마이크로 크랙 (micro crack)및 핀 홀(pin hloe)과 같은 구조 결함을 보강하고 균질(homogeniety)도 향상시킨다. 또한, 비정질 TaON박막을 증착한 후 급속열처리 공정 또는 전기로에서 700℃∼950℃, NH3 분위기(또는 N2/H2, N2O, O2분위기)에서 30초에서 30분동안 질화시키거나 산화시켜서 결정화를 이룰 수도 있다.In this embodiment, in order to further increase the density of the high-k dielectric TaON thin film 34, 200 ° C. to 600 ° C. using plasma in situ or ex-situ on the amorphous TaON thin film 34. Nitriding the surface in NH 3 atmosphere or nitrifying in N 2 O (O 2 ) atmosphere to reinforce structural defects such as micro cracks and pin holes in the interface and to improve homogeneity Let's do it. In addition, after the amorphous TaON thin film is deposited, it is nitrided at a temperature of 700 ° C. to 950 ° C., NH 3 (or N 2 / H 2 , N 2 O, O 2 ) in a rapid heat treatment process or an electric furnace for 30 seconds to 30 minutes, or It may be oxidized to achieve crystallization.
그 다음 도 4에 도시된 바와 같이, 고유전체 TaON박막(34) 상부에 도프트 폴리실리콘을 증착하여 상부전극(36)을 형성한다. 이때, 상부전극(36)과 고유전체 TaON박막(34)의 전도 장벽(conduction barrier)역할을 하는 금속을 추가할 수 있는데, 그 금속으로는 TiN, TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2, Pt 등이 있다.Next, as shown in FIG. 4, doped polysilicon is deposited on the high dielectric TaON thin film 34 to form the upper electrode 36. In this case, a metal serving as a conduction barrier of the upper electrode 36 and the high-k dielectric TaON thin film 34 may be added. Examples of the metal include TiN, TaN, W, WN, WSi, Ru, and RuO 2. , Ir, IrO 2 , Pt and the like.
상기한 바와 같이, 본 발명은 고유전체막으로서 TaON을 사용하기 때문에 유전율이 다른 유전체에 비하여 높고 구조적으로도 안정된 Ta-O-N 결합 구조를 갖고 있어 Ta2O5 박막보다 안정하여 하부전극과의 산화반응성도 작아서 등가 산화막 두께를 더 낮출 수 있어 높은 용량을 확보할 수 있다.As described above, since the present invention uses TaON as the high-k dielectric film, the dielectric constant is higher than that of other dielectrics and has a structurally stable Ta-ON bonding structure, which is more stable than the Ta 2 O 5 thin film, thereby oxidizing and reacting with the lower electrode. The smaller the thickness of the equivalent oxide film can be further lowered, thereby ensuring a high capacity.
그리고, 본 발명은 TaON 증착이전에 하부전극의 표면을 SiON계열의 막으로 코팅하여 후속 공정에서의 산화 저항성을 높이고, 폴리실리콘과의 일함수차에 대해서 SiON막이 종래 NH3 전처리에 의해 형성되는 SiN막보다 크기 때문에 누설 전류 특성이 커진다.In addition, the present invention improves oxidation resistance in a subsequent process by coating the surface of the lower electrode with a SiON-based film prior to TaON deposition, and SiN film is formed by conventional NH 3 pretreatment with respect to work function difference with polysilicon. Since it is larger than the film, the leakage current characteristic is increased.
또한, 본 발명은 하부전극 상부에 실시되는 SiON 증착 공정이 종래 하부전극의 NH3 전처리 공정보다 저온에서 진행하기 때문에 다른 소자의 전기적 특성의 열화를 방지하고, 유전체 TaON 증착 장비에서 인시튜로 진행이 가능하기 때문에 제조 과정이 단순하다는 이점이 있다.In addition, the present invention prevents deterioration of electrical characteristics of other devices, and proceeds in situ in the dielectric TaON deposition equipment because the SiON deposition process performed on the lower electrode proceeds at a lower temperature than the conventional NH 3 pretreatment process. Since it is possible, there is an advantage that the manufacturing process is simple.
도 1 내지 도 4는 본 발명에 따른 고유전체 TaON을 갖는 반도체장치의 커패시터 제조방법을 순서적으로 설명하기 위한 공정 순서도. 1 to 4 are process flowcharts for sequentially explaining a capacitor manufacturing method of a semiconductor device having a high dielectric TaON according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 실리콘기판 20: 층간절연막10: silicon substrate 20: interlayer insulating film
30: 하부 전극 32: 질화처리막30: lower electrode 32: nitrided film
34: 고유전체 TaON박막 36: 상부전극34: high dielectric TaON thin film 36: upper electrode
Claims (4)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0026503A KR100519514B1 (en) | 1999-07-02 | 1999-07-02 | Method of forming capacitor provied with TaON dielectric layer |
| TW089113015A TW474000B (en) | 1999-07-02 | 2000-06-30 | Method of manufacturing capacitor for semiconductor device |
| JP2000199534A JP2001053255A (en) | 1999-07-02 | 2000-06-30 | Manufacture of capacitor of semiconductor memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0026503A KR100519514B1 (en) | 1999-07-02 | 1999-07-02 | Method of forming capacitor provied with TaON dielectric layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010008586A KR20010008586A (en) | 2001-02-05 |
| KR100519514B1 true KR100519514B1 (en) | 2005-10-07 |
Family
ID=19598833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1999-0026503A KR100519514B1 (en) | 1999-07-02 | 1999-07-02 | Method of forming capacitor provied with TaON dielectric layer |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2001053255A (en) |
| KR (1) | KR100519514B1 (en) |
| TW (1) | TW474000B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100313091B1 (en) * | 1999-12-29 | 2001-11-07 | 박종섭 | Method of forming gate dielectric layer with TaON |
| KR100388466B1 (en) * | 2001-06-30 | 2003-06-25 | 주식회사 하이닉스반도체 | Ferroelectric capacitor having ruthenium bottom electrode and forming method thereof |
| KR100388465B1 (en) * | 2001-06-30 | 2003-06-25 | 주식회사 하이닉스반도체 | Ferroelectric capacitor having ruthenium bottom electrode and forming method thereof |
| US20170114465A1 (en) * | 2015-10-22 | 2017-04-27 | Applied Materials, Inc. | Methods Of Depositing Flowable Films Comprising SiO and SiN |
| WO2017161236A1 (en) | 2016-03-17 | 2017-09-21 | Applied Materials, Inc. | Methods for gapfill in high aspect ratio structures |
| CN112086441A (en) * | 2020-08-26 | 2020-12-15 | 中国电子科技集团公司第十三研究所 | Passive device preparation method and passive device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06244364A (en) * | 1993-02-17 | 1994-09-02 | Nec Corp | Manufacture of semiconductor device |
| KR970018202A (en) * | 1995-09-13 | 1997-04-30 | 김광호 | Method for manufacturing a tantalum pentoxide (Ta_2 O_5) dielectric film capacitor |
| KR970054106A (en) * | 1995-12-29 | 1997-07-31 | 김광호 | Semiconductor manufacturing method |
| KR980012500A (en) * | 1996-07-23 | 1998-04-30 | 김광호 | Method for manufacturing capacitor of semiconductor device |
| KR20000008014A (en) * | 1998-07-09 | 2000-02-07 | 윤종용 | Capacitor of semiconductor devices and method thereof |
-
1999
- 1999-07-02 KR KR10-1999-0026503A patent/KR100519514B1/en not_active IP Right Cessation
-
2000
- 2000-06-30 JP JP2000199534A patent/JP2001053255A/en active Pending
- 2000-06-30 TW TW089113015A patent/TW474000B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06244364A (en) * | 1993-02-17 | 1994-09-02 | Nec Corp | Manufacture of semiconductor device |
| KR970018202A (en) * | 1995-09-13 | 1997-04-30 | 김광호 | Method for manufacturing a tantalum pentoxide (Ta_2 O_5) dielectric film capacitor |
| KR970054106A (en) * | 1995-12-29 | 1997-07-31 | 김광호 | Semiconductor manufacturing method |
| KR980012500A (en) * | 1996-07-23 | 1998-04-30 | 김광호 | Method for manufacturing capacitor of semiconductor device |
| KR20000008014A (en) * | 1998-07-09 | 2000-02-07 | 윤종용 | Capacitor of semiconductor devices and method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010008586A (en) | 2001-02-05 |
| TW474000B (en) | 2002-01-21 |
| JP2001053255A (en) | 2001-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100640631B1 (en) | Capacitor of semiconductor device and method for fabricating the same | |
| KR100386447B1 (en) | Method of forming capacitor in semiconductor device | |
| US20040063275A1 (en) | Capacitor of a semiconductor memory device and method of forming the seme | |
| US7750385B2 (en) | Semiconductor interconnection structures and capacitors including poly-SiGe layers and metal contact plugs | |
| KR100321178B1 (en) | Method of forming capacitor with TaON dielectic layer | |
| KR100417855B1 (en) | capacitor of semiconductor device and method for fabricating the same | |
| KR100464650B1 (en) | Capacitor of semiconductor device having dual dielectric layer structure and method for fabricating the same | |
| KR100504435B1 (en) | Method of forming capacitor in semiconducotr device | |
| KR100327584B1 (en) | Method of forming high efficiency capacitor in semiconductor device | |
| KR100519514B1 (en) | Method of forming capacitor provied with TaON dielectric layer | |
| KR20010008527A (en) | Forming method of capacitor with TaON thin film | |
| KR100371143B1 (en) | Method of forming high efficiency capacitor in semiconductor device | |
| KR100395507B1 (en) | Semiconductor device and the method of fabricating same | |
| KR100327587B1 (en) | Method of forming capacitor provided with TaON dielectric layer | |
| KR100331271B1 (en) | Method of forming capacitor with TaON dielectric layer | |
| KR20010008503A (en) | Method of forming capacitor provied with TaON dielectric layer | |
| KR100321180B1 (en) | Method for forming Ta2O5 capacitor of semiconductor device | |
| KR100504434B1 (en) | Method of forming capacitor | |
| KR100414868B1 (en) | Method for fabricating capacitor | |
| KR100611386B1 (en) | Method For Treating The High Temperature Of Tantalium Oxide Capacitor | |
| KR100434701B1 (en) | Method for manufacturing capacitor of semiconductor device | |
| KR100331280B1 (en) | Method for manufacturing high capacitance with capacitor of semiconductor device | |
| KR100636661B1 (en) | Method for forming high reliability capacitor | |
| KR100574473B1 (en) | Capacitor Manufacturing Method of Semiconductor Device_ | |
| KR20010059236A (en) | Method of forming capacitor provided with TaON dielectric layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080820 Year of fee payment: 4 |
|
| LAPS | Lapse due to unpaid annual fee |