KR20010008503A - Method of forming capacitor provied with TaON dielectric layer - Google Patents
Method of forming capacitor provied with TaON dielectric layer Download PDFInfo
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- KR20010008503A KR20010008503A KR1019990026379A KR19990026379A KR20010008503A KR 20010008503 A KR20010008503 A KR 20010008503A KR 1019990026379 A KR1019990026379 A KR 1019990026379A KR 19990026379 A KR19990026379 A KR 19990026379A KR 20010008503 A KR20010008503 A KR 20010008503A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
Abstract
Description
본 발명은 반도체 장치의 커패시터 제조방법에 관한 것으로서, 특히 커패시터의 용량 및 전기적 특성을 향상시킬 수 있도록 고유전체의 TaON를 갖는 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor having TaON of a high dielectric material so as to improve the capacity and electrical characteristics of the capacitor.
현재 반도체 소자의 고집적화를 달성하기 위하여 셀 면적의 감소 및 동작 전압의 저전압화에 관한 연구/개발이 활발하게 진행되고 있다. 더구나 반도체 소자의 고집적화가 이루어질수록 커패시터의 면적이 급격하게 감소되지만 기억소자의 동작에 필요한 전하 즉, 단위 면적에 확보되는 커패시턴스는 증가되어야만 한다.In order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices increases, the area of the capacitor decreases drastically, but the charge required for the operation of the memory device, that is, the capacitance secured in the unit area must be increased.
이를 위해 커패시터의 충분한 용량을 확보하기 위해서 통상의 실린더 구조 변경을 통해 커패시터 면적을 증가하거나 유전체막의 두께 감소를 통해 충분한 커패시턴스를 확보시키는 방법이 이루어지고 있으며, 기존 실리콘 산화막으로 사용하던 유전체막을 NO(Nitride-Oxide) 또는 ONO(Oxide-Nitride-Oxide)구조라든지 높은 커패시턴스(유전상수=20∼25)를 확보할 수 있는 Ta2O5, TaON 내지 BST(BaSrTiO3) 등으로 대체하려는 재료적인 연구가 진행되고 있다.To this end, in order to secure a sufficient capacity of the capacitor, a method of securing a sufficient capacitance by increasing the capacitor area or reducing the thickness of the dielectric film by changing a conventional cylinder structure is being performed. The dielectric film used as a conventional silicon oxide film is NO (Nitride). -Oxide) or ONO (Oxide-Nitride-Oxide) structure or material research to replace with Ta 2 O 5 , TaON to BST (BaSrTiO 3 ) which can secure high capacitance (dielectric constant = 20-25) It is becoming.
한편, 최근에는 NO유전체를 갖는 커패시터가 256M 이상의 차세대 메모리에 필요한 용량을 확보하는데 한계를 보이고 있기 때문에 Ta2O5유전체 개발이 연구 진행중에 있다. 하지만, 이 Ta2O5박막 역시 불안정한 화학양론비(stoichiometry)를 갖고 있어 Ta와 O의 조성비 차이에 기인한 치환형 Ta원자가 박막내에 존재하기 때문에 유전체박막 공정시 Ta2O5의 전구체인 Ta(OC2H5)5의 유기물과 O2(또는 N2O)가스의 반응으로 인해 불순물인 탄소원자와 탄소화합물(C, CH4, C2H4등) 및 물(H2O)이 생성된다. 결국, Ta2O5박막내에 불순물로 존재하는 탄소원자, 이온과 라디칼로 인해서 커패시터의 누설전류가 증가하게 되고 유전특성이 열화된다. 이러한 Ta2O5박막내의 불순물을 제거하기 위하여 저온 열처리(예를 들면, plasma N2O 또는 UV-O3)를 이중, 삼중으로 처리하고 있지만 이 역시 제조 과정이 복잡하며 Ta2O5박막의 산화 저항성이 낮기 때문에 하부전극의 산화가 발생하게 된다.On the other hand, Ta 2 O 5 dielectric development is currently under study because the capacitor having a NO dielectric shows a limit in securing the capacity required for the next-generation memory of more than 256M. However, this Ta 2 O 5 thin film also has an unstable stoichiometry, and because Ta-type substituted Ta atoms exist in the thin film due to the difference in the composition ratio of Ta and O, Ta (the precursor of Ta 2 O 5 in the dielectric thin film process) Reaction of organic compounds of OC 2 H 5 ) 5 with O 2 (or N 2 O) gas produces impurities such as carbon atoms, carbon compounds (C, CH 4 , C 2 H 4, etc.) and water (H 2 O) do. As a result, the leakage current of the capacitor increases and dielectric properties deteriorate due to the carbon atoms, ions and radicals present as impurities in the Ta 2 O 5 thin film. A low temperature in order to remove the impurities in such a Ta 2 O 5 thin film heat-treating (e.g., plasma N 2 O or a UV-O 3) a double, and triple-treatment with, but is too complicated manufacturing process, and the Ta 2 O 5 thin film Since the oxidation resistance is low, oxidation of the lower electrode occurs.
이러한 Ta2O5박막의 불안정한 화학양론비를 개선하기 위하여 최근에 개발이 이루어지고 있는 TaON 유전체박막은 도프트 폴리실리콘이 증착된 하부전극 위에 기존에 유전체박막으로 자주 이용되던 Ta2O5의 근원물질인 Ta(OC2H5)5에 O2와 NH3를 첨가하여 금속유기화학기상증착법(metal-organic chemical vapor deposition)으로 증착하였다. 이때, 우수한 유전율을 가지는 TaON박막을 형성하려면, 박막 형성시에 소스물질의 분해 반응이 원활하게 일어나야 하고, 또 분해된 소스 물질과 첨가된 반응가스(O2,NH3)사이의 생성반응이 박막표면에서 활발하게 이루어져 밀도가 높은 박막을 얻을 수 있는데, 이는 어떤 소스 물질과 반응가스를 선택하느냐에 따라서 크게 달라진다.The TaON dielectric thin film, which has been recently developed to improve the unstable stoichiometry of such Ta 2 O 5 thin films, is the source of Ta 2 O 5 , which is often used as a dielectric thin film on the lower electrode on which doped polysilicon is deposited. O ( 2) and NH 3 were added to Ta (OC 2 H 5 ) 5, which was deposited by metal-organic chemical vapor deposition. At this time, in order to form a TaON thin film having excellent dielectric constant, the decomposition reaction of the source material should occur smoothly when forming the thin film, and the formation reaction between the decomposed source material and the added reaction gas (O 2 , NH 3 ) is thin film. Actively formed on the surface, a dense thin film can be obtained, depending on which source material and reactant gas are selected.
그러나, TaON의 증착공정시 반응 가스 중에서 O2는 활성화되는 정도가 N2O 또는 O3가스에 비해 떨어지므로 Ta(OC2H5)5와 반응이 느리게 일어나 TaON박막내에 다량의 탄소가 존재하게 된다. 이에 따라, TaON박막내에는 산소 공핍이 일어나서 전기적 특성인 누설 전류 감소에 영향을 주게 된다.However, since the degree of activation of O 2 in the reaction gas during TaON deposition is lower than that of N 2 O or O 3 gas, the reaction with Ta (OC 2 H 5 ) 5 is slow, resulting in a large amount of carbon in the TaON thin film. do. As a result, oxygen depletion occurs in the TaON thin film, which affects the leakage current, which is an electrical characteristic.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 유전율이 높은 TaON을 이용한 커패시터 제조 공정시 Ta 화합물의 반응 가스로서 O2대신에 반응성이 뛰어난 O3를 이용함으로써 누설 전류에 영향을 주는 탄소를 제거하고 산소 공핍을 감소시켜 전기적 특성을 개선할 수 있는 TaON박막을 갖는 커패시터 제조방법을 제공하는데 있다.An object of the present invention to affect the leakage current by using a highly reactive O 3 instead of O 2 as the reaction gas of the Ta compound in the capacitor manufacturing process using a high dielectric constant TaON to solve the problems of the prior art as described above. Disclosed is a method of manufacturing a capacitor having a TaON thin film capable of removing carbon and reducing oxygen depletion to improve electrical characteristics.
상기 목적을 달성하기 위하여 본 발명은 반도체기판의 활성영역과 접촉하는 하부 전극과 그 위의 상부전극 및 상기 전극들 사이에 내재된 고유전체 박막으로 이루어진 커패시터의 제조 공정에 있어서, 반도체 소자를 구비한 반도체기판 상부에 소자간 절연을 위한 층간절연막의 콘택홀을 통해서 반도체 소자와 접하며 도전층으로 이루어진 하부전극을 형성하는 단계와, 하부전극 상부면에 Ta 화학증기와 반응 가스 O3및 NH3를 공급해서 고유전체 TaON박막을 형성하는 단계와, 고유전체 TaON박막 상부면에 도전층으로 이루어진 상부전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a capacitor comprising a lower electrode in contact with an active region of a semiconductor substrate, an upper electrode thereon, and a high dielectric thin film embedded between the electrodes. Forming a lower electrode made of a conductive layer in contact with the semiconductor device through a contact hole of an interlayer insulating film for inter-device insulation on the semiconductor substrate, and supplying Ta chemical vapor and reactive gases O 3 and NH 3 to the upper surface of the lower electrode; Forming a high dielectric TaON thin film, and forming an upper electrode made of a conductive layer on an upper surface of the high dielectric TaON thin film.
본 발명에 따르면, TaON 박막은 유전상수가 20∼25이므로 고유전율을 가지며 화학적 결합구조도 Ta2O5박막(ε=25)보다 안정하여 하부전극과의 산화반응성도 작아서 NO 유전체 및 Ta2O5를 갖는 커패시터보다 등가 산화막 두께(Tox)를 더 낮출 수 있어 높은 용량을 확보할 수 있다.According to the invention, TaON thin film has a high dielectric constant because the dielectric constant is 20 to 25 chemically bonded structure is Ta 2 O 5 thin film (ε = 25) be less stable than the oxidation reactivity of the lower electrode and the dielectric NO Ta 2 O The equivalent oxide film thickness Tox can be lowered than that of the capacitor having 5 , thereby ensuring a high capacity.
또한, 본 발명은 Ta2O5의 소스로서 사용되었던 Ta(OC2H5)5을 동일하게 사용하고 여기에 NH3와 O3반응 가스를 첨가하여 TaON 박막을 형성하기 때문에 반응가스 O3가 O2에 비해 반응성이 좋아서 Ta(OC2H5)5와 반응할 때 이 물질에 들어 있는 탄소와 보다 빨리 반응하여 이산화탄소로 만들어 탄소를 제거할 뿐만 아니라 산소 결핍을 막아준다.In addition, since the present invention uses Ta (OC 2 H 5 ) 5 which was used as a source of Ta 2 O 5 in the same manner, and the reaction gas O 3 is formed by adding NH 3 and O 3 reaction gas thereto to form a TaON thin film. It is more reactive than O 2 , and when reacted with Ta (OC 2 H 5 ) 5 , it reacts more quickly with the carbon in the material, making it carbon dioxide, removing carbon and preventing oxygen deficiency.
도 1 내지 도 4는 본 발명에 따른 고유전체 TaON을 갖는 반도체장치의 커패시터 제조방법을 순서적으로 설명하기 위한 공정 순서도.1 to 4 are process flowcharts for sequentially explaining a capacitor manufacturing method of a semiconductor device having a high dielectric TaON according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 실리콘기판 20: 층간절연막10: silicon substrate 20: interlayer insulating film
30: 하부 전극 32: 질화처리막30: lower electrode 32: nitrided film
34: 고유전체 TaON박막 36: 상부전극34: high dielectric TaON thin film 36: upper electrode
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 고유전체 TaON을 갖는 반도체장치의 커패시터 제조방법을 순서적으로 설명하기 위한 공정 순서도이다.1 to 4 are process flowcharts for sequentially explaining a capacitor manufacturing method of a semiconductor device having a high dielectric TaON according to the present invention.
도 1에 도시된 바와 같이, 반도체기판으로서 실리콘기판(10)의 활성 영역 상부면에 게이트 전극, 소스/드레인 등을 갖는 반도체소자(도시하지 않음)를 형성하고, 그 기판(10) 전면에 USG(Undoped Silicate Glass), BPSG(Boro Phospho Silicate Glass) 및 SiON 중에서 선택한 물질을 증착하고 화학적기계적연마(Chemical Mechanical Polishing) 공정을 실시하여 평탄화된 층간절연막(20)을 형성한다. 기판(10)의 활성영역 즉, 드레인 영역과 접촉하는 커패시터의 단면적을 확보하기 위하여 사진 및 식각 공정으로 층간절연막(20)을 선택 식각하여 콘택홀(도시하지 않음)을 형성한다.As shown in FIG. 1, a semiconductor device (not shown) having a gate electrode, a source / drain, or the like is formed on an upper surface of an active region of a silicon substrate 10 as a semiconductor substrate, and USG is formed on the entire surface of the substrate 10. (Undoped Silicate Glass), BPSG (Boro Phospho Silicate Glass) and SiON material selected from the deposition and the chemical mechanical polishing (Chemical Mechanical Polishing) process is performed to form a planarized interlayer insulating film (20). In order to secure the cross-sectional area of the capacitor in contact with the active region of the substrate 10, that is, the drain region, the interlayer insulating layer 20 is selectively etched by photolithography and etching to form a contact hole (not shown).
그리고, 상기 콘택홀내에 폴리 실리콘 내지 비정질 실리콘을 증착하여 하부전극(30)을 형성한다. 이때, 커패시터의 하부전극 구조는 스택, 실린더, 핀, 스택실린더 중에서 어느 하나로 하며 특히 본 실시예에서는 실린더 형태로 형성하기로 한다. 한편, 도면에 도시하지는 않았지만, 하부전극의 평면적을 늘리기 위하여 상부면이 HSG(Hemi Sperical Grain) 형태를 갖는 하부전극을 형성할 수도 있다. 즉, 상기 콘택홀을 갖는 층간절연막(20) 전면에 도전물질로서 비정질의 도프트 실리콘을 매립하도록 증착하고 식각 공정을 이용하여 이 실리콘층을 실린더 구조 형태로 패터닝한 후에 결정화 온도 이하 상태에서 전극의 상부면에 비정질 상태의 시드(seed)를 반구형 요철형태로 성장시켜서 HSG 구조의 하부전극(30)을 형성한다. 그리고 나서, 하부전극(30)에 충분한 P(phosphorus)를 공급, 예를 들어 1×10E20/㎤ 이상의 농도를 가지도록 하기 위하여 PH3처리를 실시해준다.The lower electrode 30 is formed by depositing polysilicon or amorphous silicon in the contact hole. In this case, the lower electrode structure of the capacitor is any one of a stack, a cylinder, a pin, and a stack cylinder, and in particular, in the present embodiment, it is formed in the form of a cylinder. Although not shown in the drawing, in order to increase the planar area of the lower electrode, an upper surface may form a lower electrode having a HSG (Hemi Sperical Grain) shape. That is, depositing amorphous doped silicon as a conductive material on the entire surface of the interlayer insulating film 20 having the contact hole and patterning the silicon layer in a cylindrical structure by using an etching process. An amorphous seed is grown on the top surface in a hemispherical irregular shape to form the bottom electrode 30 of the HSG structure. Then, a sufficient P (phosphorus) is supplied to the lower electrode 30, for example, PH 3 treatment is performed to have a concentration of 1 × 10 E 20 / cm 3 or more.
이어서, 도 2에 도시된 바와 같이, 후속 TaON박막의 증착공정시 하부전극(30)의 산화를 방지하기 위해 저압화학기상증착(low pressure chemical vapor deposition)을 위한 반응 챔버에서 인시튜(in-situ) 공정으로 200℃∼600℃의 온도 조건과 플라즈마를 이용하여 NH3(또는 N2/H2, N2O) 분위기에서 하부전극(30)의 실리콘 표면을 질화시켜서 얇은 실리콘질화박막(Si3N4)(32)을 형성한다. 이때, 플라즈마를 이용하는 대신에 상압, NH3분위기 조건에서 800℃, 60초동안 급속 열처리공정(rapid thermal process)을 실시하거나 전기로(furnace)를 이용하여 600℃∼950℃의 온도 범위와 NH3분위기에서 1분에서 30분동안 질화처리 공정을 실시할 수도 있다.Subsequently, as shown in FIG. 2, in-situ in a reaction chamber for low pressure chemical vapor deposition to prevent oxidation of the lower electrode 30 during a subsequent TaON thin film deposition process. Thin silicon nitride thin film (Si 3 ) by nitriding the silicon surface of the lower electrode 30 in an NH 3 (or N 2 / H 2 , N 2 O) atmosphere using a temperature condition of 200 ° C. to 600 ° C. and plasma. N 4 ) 32. In this case, instead of using plasma, a rapid thermal process may be performed at 800 ° C. for 60 seconds at atmospheric pressure and NH 3 atmosphere, or a temperature range of 600 ° C. to 950 ° C. and NH 3 may be achieved by using an electric furnace. The nitriding process may be carried out in an atmosphere for 1 to 30 minutes.
그 다음, 도 3에 도시된 바와 같이, 상기 실리콘질화박막(32) 상부면에 TaON을 80Å∼200Å정도 증착하여 고유전체 TaON박막(34)을 형성한다. 이때의 공정은, 웨이퍼에서 일어나는 표면 화학반응(surface chemical reaction)을 통해 비정질 TaON박막을 형성하고, 보다 상세하게는 기상반응(gas phase reaction)을 억제시키면서 다음과 같은 화학증기를 사용하여 비정질 TaON박막을 증착시킨다.Next, as shown in FIG. 3, TaON is deposited on the upper surface of the silicon nitride thin film 32 by about 80 to 200 Å to form a high dielectric TaON thin film 34. In this process, the amorphous TaON thin film is formed by the surface chemical reaction occurring on the wafer, and more specifically, the amorphous TaON thin film using chemical vapor as follows while suppressing the gas phase reaction. Is deposited.
먼저, Ta성분의 화학증기는 Ta(OC2H5)5과 같은 Ta화합물을 질량 유량제어기(MFC, Mass Flow Controller)를 통해서 정량된 양을 증발기 또는 증발관으로 공급한 후에 일정량을 150℃∼200℃의 온도 범위에서 증발시켜서 얻는다. 이와 같은 방법을 통해 얻어진 Ta의 화학증기와 반응가스인 O3을 10000ppm∼200000ppm 정도 사용하고 300℃∼600℃의 저압 화학기상증착용 챔버내에서 표면반응시키면 비정질 TaON박막이 형성된다. 여기서, 반응 가스 O3은 기존 Ta2O5박막에서 사용되는 가스 O2에 비하여 반응성이 좋기 때문에 Ta(OC2H5)5와 반응해서 이산화탄소를 만들어서 탄소를 소모할 뿐만 아니라 산소 결핍을 막아주는 역할을 한다.First, the chemical vapor of Ta component supplies Ta compound such as Ta (OC 2 H 5 ) 5 to the evaporator or the evaporator after supplying the quantified amount through a mass flow controller (MFC). Obtained by evaporation in the temperature range of 200 degreeC. A TaO thin film is formed by using Ta chemical vapor and O 3 , which is a reactive gas, in a low pressure chemical vapor deposition chamber at 300 ° C to 600 ° C. Here, since the reactive gas O 3 is more reactive than the gas O 2 used in the existing Ta 2 O 5 thin film, the reaction gas O 3 reacts with Ta (OC 2 H 5 ) 5 to form carbon dioxide and thus prevents oxygen depletion. Play a role.
고유전체 TaON박막(34)의 고밀도화를 위해서, 비정질의 TaON박막(34) 상부에 인시튜 또는 엑스시튜(ex-situ)에서 플라즈마를 이용하여 200℃∼600℃, NH3분위기에서 표면을 질화시키거나 또는 N2O(O2) 분위기에서 질산화처리하여 계면의 마이크로 크랙 (micro crack)및 핀 홀(pin hloe)과 같은 구조 결함을 보강하고 균질(homogeniety)도 향상시킨다. 또한, 비정질 TaON박막을 증착한 후 급속열처리 공정 또는 전기로에서 700℃∼950℃, NH3분위기(또는 N2/H2, N2O, O2분위기)에서 30초에서 30분동안 질화시키거나 산화시켜서 결정화를 이룰 수도 있다.In order to increase the density of the high-k dielectric TaON thin film 34, the surface is nitrided at 200 ° C to 600 ° C and NH 3 atmosphere using plasma in-situ or ex-situ on the amorphous TaON thin film 34. Or nitrification in an N 2 O (O 2 ) atmosphere to reinforce structural defects such as micro cracks and pin hloe at the interface and to improve homogeneity. In addition, after the amorphous TaON thin film is deposited, it is nitrided at a temperature of 700 ° C. to 950 ° C., NH 3 (or N 2 / H 2 , N 2 O, O 2 ) in a rapid heat treatment process or an electric furnace for 30 seconds to 30 minutes, or It may be oxidized to achieve crystallization.
그 다음 도 4에 도시된 바와 같이, 고유전체 TaON박막(34) 상부에 도프트 폴리실리콘을 증착하여 상부전극(36)을 형성한다. 이때, 상부전극(36)과 고유전체 TaON박막(34)의 전도 장벽(conduction barrier)역할을 하는 금속을 추가할 수 있는데, 그 금속으로는 TiN, TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2, Pt 등이 있다.Next, as shown in FIG. 4, doped polysilicon is deposited on the high dielectric TaON thin film 34 to form the upper electrode 36. In this case, a metal serving as a conduction barrier of the upper electrode 36 and the high-k dielectric TaON thin film 34 may be added. Examples of the metal include TiN, TaN, W, WN, WSi, Ru, and RuO 2. , Ir, IrO 2 , Pt and the like.
상기한 바와 같이, 본 발명은 고유전체막으로서 TaON을 사용하기 때문에 유전율이 다른 유전체에 비하여 높고 구조적으로도 안정된 Ta-O-N 결합 구조를 갖고 있어 Ta2O5박막보다 안정하여 하부전극과의 산화반응성도 작아서 등가 산화막 두께를 더 낮출 수 있어 높은 용량을 확보할 수 있다.As described above, since the present invention uses TaON as the high-k dielectric film, the dielectric constant is higher than that of other dielectrics and has a structurally stable Ta-ON bonding structure, which is more stable than the Ta 2 O 5 thin film, thereby oxidizing and reacting with the lower electrode. The smaller the thickness of the equivalent oxide film can be further lowered, thereby ensuring a high capacity.
그리고, TaON박막은 불안정한 화학양론비를 갖는 Ta2O5박막보다 구조적으로 안정된 결합 구조를 갖고 있기 때문에 NO 또는 Ta2O5유전체에 비해서 외부로부터 인가되는 전기적 충격에도 강할 뿐만 아니라 절연파괴전압인 항복전압이 높고 누설전류도 낮다.In addition, since TaON thin film has a more structurally stable bonding structure than Ta 2 O 5 thin film having an unstable stoichiometric ratio, it is not only resistant to electric shock applied from the outside but also breakdown voltage that is dielectric breakdown voltage compared to NO or Ta 2 O 5 dielectric. High voltage and low leakage current.
한편, 본 발명은 TaON 증착 공정시 Ta2O5의 소스로서 사용되었던 Ta(OC2H5)5을 동일하게 사용하고 여기에 NH3와 O3반응 가스를 첨가하여 TaON 박막을 형성하기 때문에 반응가스 O3가 O2에 비해 반응성이 좋아서 Ta(OC2H5)5와 반응하여 이 물질에 들어 있는 탄소와 보다 빨리 반응하여 이산화탄소로 만들어 탄소를 제거할 뿐만 아니라 산소 결핍을 막아주어 누설 전류 특성을 개선한다.Meanwhile, the present invention uses Ta (OC 2 H 5 ) 5 , which was used as a source of Ta 2 O 5 in the TaON deposition process, and reacts with NH 3 and O 3 to form a TaON thin film. Because gas O 3 is more reactive than O 2 , it reacts with Ta (OC 2 H 5 ) 5 to react more quickly with carbon in this material to make carbon dioxide, which not only removes carbon, but also prevents oxygen depletion, which leads to leakage current characteristics. To improve.
또한, 본 발명은 Ta2O5박막을 이용하는 커패시터에서 이중 또는 삼중의 저온 열처리 공정을 사용하지 않기 때문에 공정을 단순화하는 이점이 있다.In addition, the present invention has the advantage of simplifying the process because it does not use a double or triple low temperature heat treatment process in a capacitor using a Ta 2 O 5 thin film.
Claims (6)
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| KR1019990026379A KR20010008503A (en) | 1999-07-01 | 1999-07-01 | Method of forming capacitor provied with TaON dielectric layer |
| TW089113010A TW471097B (en) | 1999-07-01 | 2000-06-30 | Method of manufacturing a capacitor for semiconductor memory devices |
| JP2000199542A JP2001053256A (en) | 1999-07-01 | 2000-06-30 | Formation method of capacitor of semiconductor memory element |
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| KR100415538B1 (en) * | 2001-09-14 | 2004-01-24 | 주식회사 하이닉스반도체 | Capacitor with double dielectric layer and method for fabricating the same |
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