JP2001053256A - Formation method of capacitor of semiconductor memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a forming method for a capacitor of a semiconductor memory element, which lessens generation of a leakage current in the capacitor and can ensure high capacitance of the capacitor. SOLUTION: A lower electrode 40 is formed on a semiconductor substrate 30. After that, a surface treatment for preventing generation of a natural oxide film is performed on the surface of the electrode 40. Subsequently, a TaON film is formed on the electrode 40 through chemical vapor reaction of Ta chemical vapor to O3 gas and NH3 gas, and the TaON film is crystallized. After that, an upper electrode 45 is formed on the TaON film 43a. At this time, the film 43a is formed in an LPCVD(low pressure chemical vapor deposition) chamber, which maintains a temperature of 300 to 600 deg.C and a pressure of 0.1 to 1.2 Torr.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for forming a capacitor of a semiconductor memory device, and more particularly, to a TaON method.
The present invention relates to a method for forming a capacitor of a semiconductor memory device using a film as a dielectric film.

[0002]

2. Description of the Related Art Recently, with the increase in the number of memory cells constituting a DRAM semiconductor device, the area occupied by each memory cell has been increasingly reduced. On the other hand, a capacitor formed in each memory cell needs a sufficient capacity to read out stored data accurately. As a result, the current DRAM semiconductor device requires a memory cell in which a capacitor having a large area but a large capacity is formed. The capacitance of the capacitor is increased by using an insulator having a high dielectric constant or by increasing the surface area of the lower electrode. Current highly integrated DRAM semiconductor devices include N
By using a tantalum oxide film (Ta ₂ O ₅ ) having a higher dielectric constant than an O (nitride-oxide) film as a dielectric, the lower electrode is formed tertiarily.

However, since a tantalum oxide film used as a dielectric film has an unstable stoichiometry, an oxidation step for stabilization after deposition must be performed. At this time, during the oxidation process, the tantalum oxide film easily reacts with the lower electrode to increase the thickness of the dielectric film, but rather to decrease the capacitance. In addition, since the tantalum oxide film is formed using an organic tantalum metal material as a precursor, a large amount of carbon and a carbon compound remain in the film, and a leak current is likely to occur.

On the other hand, in order to solve the problem of the tantalum oxide film, the present applicant has filed and disclosed a capacitor technology using a TaON film as a dielectric material as Japanese Patent Application No. 99-24218. Such a capacitor using a TaON film as a dielectric is shown in FIG.

Referring to FIG. 1, a gate insulating film 12 is
Is formed on the semiconductor substrate 10 on which the field oxide film 11 is formed at a predetermined portion by a known method. The junction region 14 is formed on the semiconductor substrate 10 on both sides of the gate electrode 13 to form a MOS transistor. First interlayer insulating film 16 and second interlayer insulating film 18
Is formed on a semiconductor substrate 10 on which MOS transistors are formed. The storage node contact hole h
It is formed in the first and second interlayer insulating films 16 and 18 so that the bonding region 14 is exposed. A cylindrical lower electrode 20 is formed in the storage node contact hole h by a known method so as to be in contact with the exposed bonding region 14. HSG (HemiSpherical Grai
n) The film 21 is formed on the surface of the lower electrode 20 to further increase the surface area of the lower electrode 20. HSG film 21
The surface of the lower electrode 20 including the silicon oxide is subjected to a cleaning process to prevent a natural oxide film from being generated. After that, the TaON film 23 is deposited on the lower electrode 20 and the second interlayer insulating film 18. Ta
The ON 23 is formed by a surface chemical reaction of NH ₃ gas and O ₂ gas with tantalum chemical vapor obtained by evaporating a precursor such as Ta (OC ₂ H ₅ ) ₅ . Subsequently, after the TaON film 23 is crystallized, the upper electrode 25 is
3 is formed. Such a TaON film 23 has a very high dielectric constant (ε = 20-25) and is composed of a stable bond of Ta—O—N, so that an oxidation step for stabilization after vapor deposition becomes unnecessary. The oxidation reactivity is very low and the thickness of the dielectric film does not increase.

[0006]

However, at the time of depositing a TaON film, by using O ₂ gas as a reaction gas,
The following problems occur. That is, the activation rate of the O ₂ gas is much lower than that of other gases containing oxygen.
Therefore, the reaction with the tantalum chemical vapor is also slow, and TaO
A large amount of carbon and oxygen depletion occurs in the N film. This causes a leakage current of the dielectric film.

Accordingly, an object of the present invention is to provide a method of forming a capacitor of a semiconductor memory device, which can generate a small amount of leakage current and ensure a high capacitance.

[0008]

According to the present invention, there is provided a method for forming a lower electrode on a semiconductor substrate, comprising the steps of: forming a Ta chemical vapor, an O ₃ gas and an NH ₃ gas on the lower electrode; Forming a TaON film by a phase reaction; and forming an upper electrode on the TaON film.

The present invention also includes a step of forming a lower electrode on a semiconductor substrate; a step of performing a surface treatment for preventing the formation of a natural oxide film on the surface of the lower electrode; Forming a TaON film by a chemical vapor reaction of 03 gas and NH ₃ gas; crystallizing the TaON film; and forming an upper electrode on the TaON film, wherein the TaON film is 300 to 60.
It is formed in an LPCVD chamber that maintains 0 ° C. and 0.1 to 1.2 Torr.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Referring to FIG. 2, field oxide film 31 is formed on a predetermined portion of semiconductor substrate 30 having a predetermined conductivity by a known method. A gate electrode 33 including a gate insulating film 32 at the bottom is formed at a predetermined portion on the semiconductor substrate 30, and spacers 34 are formed on both side walls of the gate electrode 33 by a known method. The junction region 35 is formed on the semiconductor substrate 30 on both sides of the gate electrode 33 and
An S transistor is formed. The first interlayer insulating film 36 and the second interlayer insulating film 38 are formed on the semiconductor substrate 30 on which the MOS transistors are formed. After that, the second and first interlayer insulating films 38 and 36 are patterned so that one of the bonding regions 35 is exposed, and a storage node contact hole H is formed. Lower electrode 40 is formed so as to be in contact with exposed bonding region 35. At this time, the lower electrode is formed in any one of a stack, a cylinder, a pin, and a stack-cylinder form, and the lower electrode 40 in the present embodiment is formed in, for example, a cylinder form.
The HSG film 41 is formed on the surface of the lower electrode 40 by a known method in order to increase the surface area of the lower electrode 40.

Thereafter, the lower electrode 40 including the HSG film 41 is formed.
The lower electrode 40 including the HSG film 41 and the second interlayer insulating film 38 are provided on the interface between the lower electrode 40 and the second interlayer insulating film 38 to prevent the formation of a low dielectric natural oxide film at an interface between the lower electrode 40 and a dielectric film (not shown) formed later. It is processed. Here, the surface treatment is performed in situ by LPCVD (low pr) having an NH ₃ gas or N ₂ / H ₂ gas atmosphere.
essure chemical vapor deposition) In a chamber, a method of performing heat treatment at a temperature of 200 to 600 ° C. using plasma, or an RTN treatment in an NH ₃ gas atmosphere and a temperature of 650 to 950 ° C., or a heat treatment in an electric furnace under the same conditions Done by the method. At this time, a silicon nitride film 42 is naturally formed on the lower electrode 40 including the HSG film 41 and the second interlayer insulating film 38 by the surface treatment.

Referring to FIG. 3, TaON as a dielectric material
The film 43 is made of Ta (OC ₂ H ₅ ) ₅ (tantalum ethylate)
Ta chemical vapor obtained by evaporating a precursor such as
_An O ₃ (ozone) gas and a NH ₃ gas, which are faster than the _two gases, are formed on the silicon nitride film 42 by a reaction. Preferably, the TaON film is deposited by a gas phase reaction.
The action is suppressed only on the wafer surface while the action is suppressed. At this time, the TaON film 43 is formed by a chemical vapor deposition method, for example, an LPCVD method (low pressure chemical
It is desirable to be formed by a vapor deposition method.
It is formed under the conditions of about 300 to 600 ° C. and 0.1 to 1.2 Torr. Here, since the precursor such as Ta (OC ₂ H ₅ ) ₅ is in a liquid state, it is converted into a vapor state and then converted into a LPCV.
Should be fed into the D chamber. At this time, the precursor is converted into Ta chemical vapor by the following method. That is, the precursor is supplied to an evaporator tube or an evaporator after adjusting the flow rate with a flow controller such as an MFC (MassFlow Controller). Thereafter, the precursor supplied to the evaporator tube or evaporator is evaporated at a temperature of 150 to 200 ° C.
It becomes a chemical vapor state. Next, Ta chemical vapor is supplied into an LPCVD chamber that maintains 300-600 ° C. The Ta chemical vapor, O ₃ gas, and NH ₃ gas thus formed react with each other in the chamber to form the TaON film 43 in an amorphous state. Here, NH ₃ gas is supplied at about 10 to 1000 sccm, and O ₃ gas is supplied at about 10 sccm.
2,000 to 200,000 ppm is supplied. Since the O ₃ gas in this embodiment has a very high reactivity compared to the conventional O ₂ gas, it reacts quickly with the carbon contained in the Ta chemical vapor. Therefore, the O ₃ gas completely consumes carbon in the Ta chemical vapor in a CO ₂ gas state, thereby preventing oxygen deficiency.

Thereafter, as shown in FIG. 4, the TaON film 43 in the amorphous state is formed in a gas atmosphere containing nitrogen or oxygen,
For example, rapid heat treatment or electric furnace heat treatment is performed in an NH ₃ gas, N ₂ / H ₂ gas, N ₂ O or O ₂ atmosphere and a temperature of 700 to 950 ° C. for 30 seconds to 30 minutes. By such a heat treatment step, the TaON film 43 in an amorphous state becomes a crystalline state 43a in which the bonding structure is more dense.

Alternatively, instead of the high-temperature heat treatment step, in
At -situ or ex-situ, NH ₃ gas atmosphere or N ₂ O
Plasma heat treatment can be performed in a gas atmosphere and at 200 to 600 ° C. By such low-temperature heat treatment, TaO
Structural defects such as microcracks and pinholes at the interface of the N film 43 are optimized, and homogeneity is also improved.

Thereafter, as shown in FIG. 5, the upper electrode 45 is formed on the TaON film 43a. The upper electrode 45 is made of a doped polysilicon film or TiN, TaN, W, W
N, WSi, Ru, RuO ₂ , Ir, IrO ₂ or Pt
Is formed of a metal layer such as When a doped polysilicon film is used for the upper electrode 45, the doped polysilicon film is preferably deposited to a thickness of about 1000 to 1500 degrees. When a metal layer is used for the upper electrode 45, the metal layer is preferably formed to a thickness of about 100 to 600 degrees. In addition, the polysilicon film can be formed by the CVD method, and the metal layer can be formed by LPCVD, PECVD, R
It can be formed by any one of the F magnetic padding method.

[0016]

As described in detail above, in this embodiment,
TaON dielectric film has excellent reaction characteristics as a reaction gas
O_ThreeUse gas. Thereby, TaON film formation
Time, O_ThreeOxygen in the gas quickly reacts with the carbon contained in the precursor
To convert all the carbon components into CO _TwoEvaporate to a state.
At the same time, supply sufficient oxygen into the membrane to prevent oxygen deficiency.
To stop. Thereby, the leakage current characteristics are improved.

The TaON film is composed of a stable Ta—O—N film, maintains a structurally stable state, and has low oxidation reactivity with the upper and lower electrodes, so that the thickness of the dielectric film increases. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a capacitor of a conventional semiconductor device.

FIG. 2 is a cross-sectional view illustrating a capacitor of a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a capacitor of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view illustrating a capacitor of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view illustrating a capacitor of the semiconductor device according to the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 30 semiconductor substrate 31 field oxide film 33 gate electrode 35 bonding region 36 first interlayer insulating film 38 second interlayer insulating film 40 lower electrode 41 HSG film 42 silicon nitride film 43 amorphous TaON film 43a crystalline TaON film 45 Upper electrode

Claims (20)

[Claims] A step of forming a lower electrode on the semiconductor substrate; a step of forming a Ta chemical vapor, an O ₃ gas, and a NH on the lower electrode;
Forming a TaON film by a chemical vapor reaction of _three gases; and forming an upper electrode on the TaON film. 2. The method as claimed in claim 1, wherein the Ta chemical vapor is obtained by evaporating a precursor containing tantalum at a temperature of 150 to 200 ° C. 3. The method as claimed in claim _2, wherein the precursor is Ta (OC ₂ H ₅ ) ₅ . 4. The method as claimed in claim 1, wherein the TaON film is formed in an LPCVD chamber maintained at 300 to 600 ° C. and 0.1 to 1.2 Torr. 5. The method according to claim 1, wherein the NH ₃ gas is 10 to 1000
2. The method of claim 1, wherein only the sccm is supplied. 6. The O ₃ gas of 10,000 to 2,000.
2. The method according to claim 1, wherein the supply is performed by only 00 ppm. 7. The step of forming the lower electrode, and the step of forming the TaO.
2. The method according to claim 1, further comprising performing a surface treatment for preventing a natural oxide film from being formed on the surface of the lower electrode during the step of forming the N film. 8. The surface treatment is performed using NH ₃ gas or N ₂ /
LPCVD using plasma having H ₂ gas atmosphere (low
8. The method of claim 7, wherein the heat treatment is performed at 200 to 600 [deg.] C. in a pressure chemical vapor deposition chamber. 9. The method of claim 7, wherein the surface treatment is performed by performing an RTN process at 650 to 950 ° C. in an NH ₃ gas atmosphere. 10. The method according to claim 7, wherein the surface treatment is performed at 650 to 950 ° C. in an electric furnace having an NH ₃ gas atmosphere. . 11. The semiconductor memory device according to claim 8, wherein a step of crystallizing the inside of the TaON film is further performed between the step of forming the TaON film and the step of forming the upper electrode. Capacitor forming method. 12. The step of crystallizing the TaON film is performed at 700 to 950 ° C. and at NH ₃ , N ₂ / H ₂ , N ₂ O,
O ₂ in the RTP chamber or electric furnace with any of the gas atmosphere of the gas, characterized in that it is heat-treated 30 seconds to 30 minutes, a capacitor forming method of a semiconductor memory device according to claim 11, wherein. 13. A step of forming a lower electrode on a semiconductor substrate; a step of performing a surface treatment for preventing generation of a native oxide film on a surface of the lower electrode; a step of forming a Ta chemical vapor, an O ₃ gas and a Ta gas on the lower electrode. Ta by chemical vapor reaction of NH ₃ gas
Forming an ON film; crystallizing the TaON film; and forming an upper electrode on the TaON film, wherein the TaON film has a temperature of 300 to 600 ° C. and 0.1 to 1.
A method for forming a capacitor of a semiconductor memory device, wherein the capacitor is formed in an LPCVD chamber maintaining 2 Torr. 14. The method according to claim 13, wherein the Ta chemical vapor is obtained by evaporating a precursor containing tantalum at a temperature of 150 to 200 ° C. 15. The method as claimed in claim 13, wherein the precursor is Ta (OC ₂ H ₅ ) ₅ . 16. The NH ₃ gas may be 10 to 100 each.
0 sccm, and the O ₃ gas is 10,000 to 2
14. The method as claimed in claim 13, wherein the amount is supplied at 00000 ppm. 17. The surface treatment may be performed using NH ₃ gas or N
LPCVD using plasma with a ₂ / H ₂ gas atmosphere (l
14. The method of claim 13, wherein the heat treatment is performed at 200 to 600 [deg.] C. in a chamber. 18. The method according to claim 13, wherein the surface treatment is performed by performing an RTN process at 650 to 950 ° C. in an NH ₃ gas atmosphere. 19. The method according to claim 13, wherein the surface treatment is performed at 650 to 950 ° C. in an electric furnace having an NH ₃ gas atmosphere. . 20. The step of crystallizing the TaON film is performed at 700 to 950 ° C. and NH ₃ , N ₂ / H ₂ , N ₂
O, with O ₂ RTP chamber or electric furnace with any of the gas atmosphere of the gas, characterized in that it is heat-treated 30 seconds to 30 minutes, a capacitor forming method of a semiconductor memory device according to claim 13, wherein.