JP2001053255A - Manufacture of capacitor of semiconductor memory element - Google Patents

Manufacture of capacitor of semiconductor memory element

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Publication number
JP2001053255A
JP2001053255A JP2000199534A JP2000199534A JP2001053255A JP 2001053255 A JP2001053255 A JP 2001053255A JP 2000199534 A JP2000199534 A JP 2000199534A JP 2000199534 A JP2000199534 A JP 2000199534A JP 2001053255 A JP2001053255 A JP 2001053255A
Authority
JP
Japan
Prior art keywords
film
gas
forming
taon
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000199534A
Other languages
Japanese (ja)
Inventor
Toshu Boku
東 洙 朴
Semin Ri
世 民 李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JP2001053255A publication Critical patent/JP2001053255A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02249—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by combined oxidation and nitridation performed simultaneously
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of the capacitor of a semiconductor memory element, which eliminates a high-temperature heat-treating process for eliminating a natural oxide film to prevent deterioration of a lower transistor. SOLUTION: This manufacturing method of a capacitor of a semiconductor memory element comprises a stage to form a lower electrode 40, using a doped silicon material on a semiconductor substrate 30, a stage to form a silicon oxinitride film 42 on the surface of the electrode 40, a stage to form a TaON film on the film 42 by the reaction of Ta chemical vapor to O3 gas and NH3 gas and a stage to form an upper electrode 50 on the TaON film. The film 42 is formed in a temperature range of 200 to 600 deg.C.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体メモリ素子の
キャパシタの製造方法に関し、より詳しくは、ＴａＯＮ
膜をキャパシタの誘電体膜とする半導体メモリ素子のキ
ャパシタの形成方法に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a capacitor of a semiconductor memory device, and more particularly, to a TaON method.
The present invention relates to a method for forming a capacitor of a semiconductor memory device using the film as a dielectric film of the capacitor.

【０００２】[0002]

【従来の技術】最近、ＤＲＡＭ半導体素子を構成するメ
モリセルの数の増加に伴い、各メモリセルの占有面積は
益々低減しつつある。一方、各メモリセル内に形成され
るキャパシタは、正確な貯蔵データを読み出す為に充分
な容量が必要である。これにより、現在のＤＲＡＭ半導
体素子は、小面積ながら大容量を有するキャパシタが形
成されたメモリセルを要求とする。キャパシタの静電容
量（capacitance）は、高誘電率を持つ絶縁体を用いる
か、或いは下部電極の表面積を拡大させることにより増
大する。現在の高集積化したＤＲＡＭ半導体素子には、
ＮＯ（nitride-oxide）膜よりも高誘電率のタンタル酸
化膜（Ｔａ2Ｏ5 ）が誘電体として用いられることで、
下部電極が３次的に形成される。2. Description of the Related Art Recently, with the increase in the number of memory cells constituting a DRAM semiconductor device, the area occupied by each memory cell has been increasingly reduced. On the other hand, a capacitor formed in each memory cell needs a sufficient capacity to read out stored data accurately. Accordingly, the current DRAM semiconductor device requires a memory cell in which a capacitor having a large area but a large capacity is formed. The capacitance of a capacitor is increased by using an insulator having a high dielectric constant or by increasing the surface area of the lower electrode. Current highly integrated DRAM semiconductor devices include:
By using a tantalum oxide film (Ta 2 O 5 ) having a higher dielectric constant than a NO (nitride-oxide) film as a dielectric,
A lower electrode is tertiarily formed.

【０００３】しかし、誘電体膜として用いるタンタル酸
化膜は、不安な化学量論比（stoichiometry）を持つの
で、蒸着後に安定化するための酸化工程を必ず行うべき
である。このとき、タンタル酸化膜は、下部電極と容易
に反応して誘電体膜の厚さを増加させることで、むしろ
キャパシタンスを減少させる。合わせて、タンタル酸化
膜は、有機タンタル金属物質を前駆体として用いて形成
されるため、膜内に多量の炭素及び炭素化合物を残留さ
せて、リーク電流が発生しやすい。However, since a tantalum oxide film used as a dielectric film has an unstable stoichiometry, an oxidation step for stabilization after deposition must be performed. At this time, the tantalum oxide film easily reacts with the lower electrode to increase the thickness of the dielectric film, thereby decreasing the capacitance. In addition, since the tantalum oxide film is formed using an organic tantalum metal substance as a precursor, a large amount of carbon and carbon compounds remain in the film, and a leak current is likely to occur.

【０００４】これに対して本出願人は、タンタル酸化膜
の問題点を解決する為に、ＴａＯＮ膜を誘電体として用
いるキャパシタの技術を、９９−２４２１８号として出
願、開示している。この様なＴａＯＮ膜を誘電体とする
キャパシタは、図１に示している。On the other hand, in order to solve the problem of the tantalum oxide film, the present applicant has filed and disclosed a technology of a capacitor using a TaON film as a dielectric material as Japanese Patent Application No. 99-24218. Such a capacitor using a TaON film as a dielectric is shown in FIG.

【０００５】図１を参照して、下部にゲート絶縁膜１２
を含むゲート電極１３は、フィールド酸化膜１１が所定
部分に形成された半導体基板１０上に公知の方式によっ
て形成される。接合領域１４はゲート電極１３の両側の
半導体基板１０に形成されてＭＯＳトランジスタが形成
される。第１層間絶縁膜１６及び第２層間絶縁膜１８
は、ＭＯＳトランジスタが形成された半導体基板１０上
に形成される。ストレージノードコンタクトホールｈ
は、接合領域１４が露出するように、第１及び第２層間
絶縁膜１６、１８内に形成される。シリンダー形態の下
部電極２０が公知の方式により、露出した接合領域１４
とコンタクトされるように、ストレージノードコンタク
トホールｈ内に形成される。ＨＳＧ（HemiSpherical G
rain）膜２１は、下部電極２０の表面積を一層増大させ
る為に、下部電極２０の表面に形成される。ＨＳＧ膜２
１を含む下部電極２０の表面は自然酸化膜の発生を防止
する為に、ＮＨ3プラズマ雰囲気及び８５０乃至９５０
の範囲で前処理工程が行われる。この様な前処理工程に
より、ＨＳＧ膜２１を含む下部電極２０上及び第２層間
絶縁膜１８上に酸化反応を抑制させるシリコン窒酸化膜
ＳｉｘＮｙ２２が形成される。ＴａＯＮ膜２３はシリコ
ン窒酸化膜２２上にタンタル化学蒸気、ＮＨ3ガス及び
Ｏ2 ガスの表面化学反応によって形成される。続いて、
ＴａＯＮ膜２３は、熱処理工程により結晶化した後、上
部電極２５が結晶化したＴａＯＮ膜２３上に形成され
る。この様なＴａＯＮ膜２３は、非常に高誘電率（ε＝
２０-２５）を持ち、Ｔａ-Ｏ-Ｎの安定した結合から構
成されるので、蒸着後に安定化するための酸化工程が不
要となり、酸化反応性が非常に低くて誘電体膜の厚さが
増大しない。Referring to FIG. 1, a gate insulating film 12 is
Is formed by a known method on the semiconductor substrate 10 on which the field oxide film 11 is formed at a predetermined portion. The junction region 14 is formed on the semiconductor substrate 10 on both sides of the gate electrode 13 to form a MOS transistor. First interlayer insulating film 16 and second interlayer insulating film 18
Are formed on a semiconductor substrate 10 on which MOS transistors are formed. Storage node contact hole h
Is formed in the first and second interlayer insulating films 16 and 18 such that the bonding region 14 is exposed. The lower electrode 20 in the form of a cylinder is exposed to the exposed bonding region 14 in a known manner.
Is formed in the storage node contact hole h so as to be in contact with the storage node. HSG (HemiSpherical G
rain) The film 21 is formed on the surface of the lower electrode 20 in order to further increase the surface area of the lower electrode 20. HSG film 2
For the surface of the lower electrode 20 to prevent the occurrence of a natural oxide film containing 1, NH 3 plasma atmosphere and 850 to 950
The pre-processing step is performed within the range. By such a pretreatment process, a silicon oxynitride film SixNy22 for suppressing an oxidation reaction is formed on the lower electrode 20 including the HSG film 21 and on the second interlayer insulating film 18. The TaON film 23 is formed on the silicon oxynitride film 22 by a surface chemical reaction of tantalum chemical vapor, NH 3 gas and O 2 gas. continue,
The TaON film 23 is formed on the crystallized TaON film 23 of the upper electrode 25 after being crystallized by the heat treatment step. Such a TaON film 23 has a very high dielectric constant (ε =
20-25) and consists of a stable bond of Ta-ON, so that an oxidation step for stabilization after vapor deposition is not required, the oxidation reactivity is extremely low, and the thickness of the dielectric film is reduced. Does not increase.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、ＴａＯ
Ｎ膜の蒸着前、自然酸化膜の発生を防止する前処理工程
が８００℃以上で行われることで、融点が８００℃以下
の物質で構成される下部電極及びその他の電極が溶融さ
れる。このため、８００℃以上で熱処理工程を行なうこ
とは実際的には不可能である。SUMMARY OF THE INVENTION However, TaO
Before the N film is deposited, a lower electrode and other electrodes made of a substance having a melting point of 800 ° C. or less are melted by performing a pretreatment process at 800 ° C. or more for preventing generation of a natural oxide film. Therefore, it is practically impossible to perform the heat treatment at 800 ° C. or higher.

【０００７】また、前処理工程によって形成されたシリ
コン窒酸化膜２２は、低誘電率を有するという長所はあ
るが、下部電極の材料として用いられるポリシリコン膜
と仕事関数の差が小さいため、リーク電流が発生する。The silicon oxynitride film 22 formed by the pretreatment process has the advantage of having a low dielectric constant, but has a small difference in work function from the polysilicon film used as the material of the lower electrode, so that the leakage current is low. An electric current is generated.

【０００８】従って、本発明の目的は、自然酸化膜の排
除のための高温の熱処理工程を排除して、下部トランジ
スタの劣化を防止できる半導体メモリ素子のキャパシタ
の製造方法を提供することにある。Accordingly, it is an object of the present invention to provide a method of manufacturing a capacitor of a semiconductor memory device, which can prevent a lower transistor from being deteriorated by eliminating a high-temperature heat treatment step for eliminating a native oxide film.

【０００９】また、本発明の他の目的は、キャパシタの
リーク電流を防止できる半導体メモリ素子のキャパシタ
の製造方法を提供することにある。It is another object of the present invention to provide a method of manufacturing a capacitor of a semiconductor memory device, which can prevent a leakage current of the capacitor.

【００１０】[0010]

【課題を解決するための手段】前記目的を達成する為
に、本発明は、半導体基板上にドープトシリコン物質で
下部電極を形成する段階；前記下部電極表面にシリコン
窒酸化膜を形成する段階；前記シリコン窒酸化膜上にＴ
ａ化学蒸気、Ｏ3ガス及びＮＨ3 ガスの反応によりＴａ
ＯＮ膜を形成する段階；及び前記ＴａＯＮ膜上に上部電
極を形成する段階を含み、前記シリコン窒酸化膜は２０
０乃至６００℃の温度範囲で形成することを特徴とす
る。To achieve the above object, the present invention provides a method for forming a lower electrode on a semiconductor substrate using a doped silicon material; and forming a silicon oxynitride film on a surface of the lower electrode. T on the silicon oxynitride film
aTa by reaction of chemical vapor, O 3 gas and NH 3 gas
Forming an ON film; and forming an upper electrode on the TaON film.
It is characterized by being formed in a temperature range of 0 to 600 ° C.

【００１１】また、本発明は、半導体基板上にドープト
シリコン物質で下部電極を形成する段階；前記下部電極
表面にシリコン窒酸化膜をin-situにて形成する段階；
前記シリコン窒酸化膜上にＴａ化学蒸気、Ｏ3ガス及び
ＮＨ3 ガスの反応によりＴａＯＮ膜を形成する段階；前
記ＴａＯＮ膜を熱処理する段階；及び前記ＴａＯＮ膜上
に上部電極を形成する段階を含み、前記シリコン窒酸化
膜の形成段階はＴａＯＮ膜の形成段階とin-situにて行
われ、前記シリコン窒酸化膜は、２００乃至６００℃及
びプラズマ雰囲気で、ＮＨ3ガス供給後にＯ2 ガスまた
はＮ2 Ｏガスを供給して形成することを特徴とする。The present invention also provides a step of forming a lower electrode of a doped silicon material on a semiconductor substrate; a step of forming a silicon oxynitride film on the surface of the lower electrode in-situ;
Forming a TaON film on the silicon oxynitride film by a reaction of Ta chemical vapor, O 3 gas and NH 3 gas; heat treating the TaON film; and forming an upper electrode on the TaON film. The step of forming the silicon oxynitride film is performed in-situ with the step of forming the TaON film. The silicon oxynitride film is formed at 200 to 600 ° C. and in a plasma atmosphere after supplying NH 3 gas and O 2 gas or N 2 gas. It is characterized by being formed by supplying 2 O gas.

【００１２】さらにまた、本発明は、半導体基板上にド
ープトシリコン物質で下部電極を形成する段階；前記下
部電極表面にシリコン窒酸化膜をin-situにて形成する
段階；前記シリコン窒酸化膜上にＴａ化学蒸気、Ｏ3ガ
ス及びＮＨ3 ガスの反応によりＴａＯＮ膜を形成する段
階；前記ＴａＯＮ膜を熱処理する段階；及び前記ＴａＯ
Ｎ膜上に上部電極を形成する段階を含み、前記シリコン
窒酸化膜の形成段階はＴａＯＮ膜の形成段階とin-situ
にて行われ、前記シリコン窒酸化膜は２００乃至６００
℃で形成され、前記シリコン窒酸化膜の形成段階は、Ｎ
Ｈ3プラズマガス雰囲気で下部電極の表面を窒化させる
段階と、前記下部電極の表面を高真空酸化させる段階と
を含むことを特徴とする。Further, the present invention provides a method of forming a lower electrode of a doped silicon material on a semiconductor substrate; forming an in-situ silicon oxynitride film on the surface of the lower electrode; Forming a TaON film thereon by a reaction of Ta chemical vapor, O 3 gas, and NH 3 gas; heat treating the TaON film; and the TaO film
Forming an upper electrode on the N film; forming the silicon oxynitride film includes forming a TaON film and forming the silicon nitride oxide film in-situ;
And the silicon oxynitride film has a thickness of 200 to 600
C., and the step of forming the silicon oxynitride film comprises N
The method includes nitriding the surface of the lower electrode in an H 3 plasma gas atmosphere, and oxidizing the surface of the lower electrode with high vacuum.

【００１３】[0013]

【発明の実施の形態】以下、添付図面に基づき、本発明
の好適実施例を詳細に説明する。 （実施例１）図２を参照して、フィールド酸化膜３１は
公知の方式にて所定の電導性を持つ半導体基板３０の所
定部分に形成される。底部にゲート絶縁膜３２を含むゲ
ート電極３３が半導体基板３０上の所定部分に形成さ
れ、スペーサ３４はゲート電極３３の両側壁に公知の方
式にて形成される。接合領域３５はゲート電極３３の両
側の半導体基板３０に形成されてＭＯＳトランジスタが
形成される。第１層間絶縁膜３６及び第２層間絶縁膜３
８はＭＯＳトランジスタの形成された半導体基板３０に
形成される。その後、接合領域３５のうちの何れかが露
出するように第２及び第１層間絶縁膜３８、３６がパタ
ーニングされ、ストリージノードコンタクトホールＨが
形成される。露出した接合領域３５とコンタクトされる
ように下部電極４０が形成される。このとき、下部電極
はスタック、シリンダー、ピン、スタック−シリンダー
形態の何れかで形成される。本実施例での下部電極４０
は、例えばシリンダー形態で形成される。このとき、下
部電極４０はドープトポリシリコン膜またはドープト非
晶質シリコン膜で形成されることができる。また、ＨＳ
Ｇ膜（不図示）は、下部電極４０の表面的を増大させる
為に、下部電極４０の表面に形成されることができ、Ｈ
ＳＧ膜が形成される場合、下部電極４０は非晶質シリコ
ン膜で形成されることが望ましい。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. (Embodiment 1) Referring to FIG. 2, field oxide film 31 is formed on a predetermined portion of semiconductor substrate 30 having a predetermined conductivity by a known method. A gate electrode 33 including a gate insulating film 32 at the bottom is formed at a predetermined portion on the semiconductor substrate 30, and spacers 34 are formed on both side walls of the gate electrode 33 by a known method. The junction region 35 is formed on the semiconductor substrate 30 on both sides of the gate electrode 33 to form a MOS transistor. First interlayer insulating film 36 and second interlayer insulating film 3
8 is formed on a semiconductor substrate 30 on which MOS transistors are formed. After that, the second and first interlayer insulating films 38 and 36 are patterned so that one of the bonding regions 35 is exposed, and a storage node contact hole H is formed. Lower electrode 40 is formed so as to be in contact with exposed bonding region 35. At this time, the lower electrode may be formed in a stack, cylinder, pin, or stack-cylinder configuration. Lower electrode 40 in this embodiment
Is formed, for example, in the form of a cylinder. At this time, the lower electrode 40 may be formed of a doped polysilicon film or a doped amorphous silicon film. Also, HS
A G film (not shown) can be formed on the surface of the lower electrode 40 in order to increase the surface of the lower electrode 40.
When the SG film is formed, it is preferable that the lower electrode 40 be formed of an amorphous silicon film.

【００１４】その後、下部電極４０と以後形成される誘
電体膜（不図示）との間の界面に、低誘電自然酸化膜の
発生を阻止する為に、シリコン窒酸化膜ＳｉＯＮ４２が
下部電極表面に形成される。このようなシリコン窒酸化
膜４２は下部トランジスタの劣化を最小化する為に、２
００乃至６００℃の範囲で形成される。このとき、シリ
コン窒酸化膜４２は、下部電極４０がプラズマ雰囲気で
窒酸化処理によって形成される。窒酸化処理は、ＬＰＣ
ＶＤチャンバ内にＮＨ3ガスとＯ2 ガスまたはＮ2 Ｏガ
スが各々１０乃至１０００sccmだけ供給されて行われ
る。この様な窒酸化処理時、ＮＨ3ガスがＯ2 ガスまた
はＮ2 Ｏガスより先に注入されて、Ｏ2ガスまたはＮ2
Ｏガスと下部電極４０との間の追加的な反応が抑制され
る。Thereafter, at the interface between the lower electrode 40 and a dielectric film (not shown) formed thereafter, a silicon oxynitride film SiON 42 is formed on the surface of the lower electrode in order to prevent the formation of a low dielectric natural oxide film. It is formed. Such a silicon oxynitride film 42 is used to minimize the deterioration of the lower transistor.
It is formed in the range of 00 to 600 ° C. At this time, the silicon oxynitride film 42 is formed by performing a nitridation process on the lower electrode 40 in a plasma atmosphere. Nitrogen oxidation treatment is LPC
The VD chamber is supplied with NH 3 gas and O 2 gas or N 2 O gas at 10 to 1000 sccm each. During such a nitridation treatment, NH 3 gas is injected before O 2 gas or N 2 O gas, and O 2 gas or N 2 O
An additional reaction between the O gas and the lower electrode 40 is suppressed.

【００１５】この様なシリコン窒酸化膜４２は、下部電
極４０との仕事関数差が顕著なので、リーク電流の発生
危険が少なく、２００乃至６００℃で蒸着されるため、
既に形成されているトランジスタの素子の電気的特性に
影響を及ぼさない。Since such a silicon nitride oxide film 42 has a remarkable work function difference from the lower electrode 40, there is little danger of generating a leak current, and it is deposited at 200 to 600 ° C.
It does not affect the electrical characteristics of the already formed transistor elements.

【００１６】図３を参照して、誘電体としてのＴａＯＮ
膜４４は、Ｔａ（ＯＣ2Ｈ5 ）５（tantalum ethylate）
の様なタンタル有機金属物質の前駆体から得られたＴａ
化学蒸気、Ｏ2ガス及びＮＨ3 ガスの反応によってシリ
コン窒酸化膜４２上に形成される。望ましくはＴａ化学
蒸気、Ｏ2ガス及びＮＨ3 ガスは、気相反応が抑制され
た状態でウェーハ表面のみで反応するようにする。合わ
せて、８０乃至２００Å厚さで蒸着されるのが望まし
い。このとき、ＴａＯＮ膜４４は、化学気相蒸着法、例
えば、ＬＰＣＶＤ方式にて形成されのが望ましく、約３
００乃至６００℃及び０.１乃至１.２Torrの条件で形成
される。ここで、Ｔａ（ＯＣ2 Ｈ5 ）5 の様な前駆体は
液状であるから、蒸気状態に変換させた後、ＬＰＣＶＤ
チャンバ内に供給すべきである。このとき、前駆体は次
の様な方法によりＴａ化学蒸気に変換される。すなわ
ち、前駆体は、ＭＦＣ（Mass Flow Controller）の様
な流量調節器で流量を調節した後、蒸発管または蒸発器
に供給される。その後、蒸発管または蒸発器に供給され
た前駆体は、１５０乃至２００℃の温度で蒸発されてＴ
ａ化学蒸気状態となる。その後、Ｔａ化学蒸気はＬＰＣ
ＶＤチャンバ内に供給され、Ｔａ化学蒸気、Ｏ 3ガス及
びＮＨ3 ガスはチャンバ内で互いに表面反応されて、非
晶質状態のＴａＯＮ膜４４が形成される。ここで、Ｏ2
ガス及びＮＨ3 ガスは、１０乃至１０００sccｍだけ供
給される。また、ＴａＯＮ膜４４はシリコン窒酸化膜４
２を形成する工程とin-situにて行われる。Referring to FIG. 3, TaON as a dielectric material
The film 44 is made of Ta (OCTwoHFive ) 5 (tantalum ethylate)
Obtained from a precursor of a tantalum organometallic substance such as
Chemical vapor, OTwoGas and NHThree Gas reaction
It is formed on the oxynitride film 42. Preferably Ta chemistry
Steam, OTwoGas and NHThree Gas is suppressed gas phase reaction
In this state, the reaction occurs only on the wafer surface. Match
Therefore, it is desirable that the film be deposited at a thickness of 80 to 200 mm.
No. At this time, the TaON film 44 is formed by a chemical vapor deposition method, for example,
For example, it is desirable to form by the LPCVD method.
Formed under conditions of 00 to 600 ° C and 0.1 to 1.2 Torr
Is done. Here, Ta (OCTwo HFive )Five Precursors like
After being converted to a vapor state because it is liquid, LPCVD
Should be fed into the chamber. At this time, the precursor is
Is converted into Ta chemical vapor by a method such as Sand
The precursor is like MFC (Mass Flow Controller)
After adjusting the flow rate with a suitable flow controller,
Supplied to Then it is supplied to the evaporator tube or evaporator
The precursor is evaporated at a temperature of 150 to 200 ° C.
a) It becomes a chemical vapor state. After that, Ta chemical vapor is LPC
Supplied into the VD chamber, Ta chemical vapor, O ThreeGas
And NHThree The gases are surface reacted with each other in the chamber,
A TaON film 44 in a crystalline state is formed. Where OTwo
Gas and NHThree The gas is supplied only for 10 to 1000 sccm.
Paid. The TaON film 44 is formed of the silicon oxynitride film 4.
2 and in-situ.

【００１７】次に、図４に示す様に、非晶質状態のＴａ
ＯＮ膜４４は、窒素または酸素を含むガス雰囲気、例え
ばＮＨ3ガス、Ｎ2 /Ｈ2 ガス、Ｎ2 ＯまたはＯ2雰囲気
及び６５０乃至８００℃の温度で、３０秒乃至３０分間
急速熱処理または電気炉熱処理される。この様な熱処理
工程により、非晶質状態のＴａＯＮ膜４３は結合構造が
一層緻密な結晶質状態４４ａとなる。Next, as shown in FIG.
The ON film 44 is formed by a rapid thermal process or an electrical process in a gas atmosphere containing nitrogen or oxygen, for example, NH 3 gas, N 2 / H 2 gas, N 2 O or O 2 atmosphere and a temperature of 650 to 800 ° C. for 30 seconds to 30 minutes. Furnace heat treatment. By such a heat treatment step, the TaON film 43 in an amorphous state becomes a crystalline state 44a having a more dense bonding structure.

【００１８】このとき、図には示さないが、非晶質状態
のＴａＯＮ膜４４は、結晶化させるための高温工程なし
に界面特性を確保する為に、in-situまたはex-situに
て、ＮＨ3ガス雰囲気及び２００乃至６００℃でプラズ
マ熱処理するか、あるいはＮ2Ｏガス雰囲気で窒酸化処
理する。これにより、ＴａＯＮ膜４３界面のマイクロク
ラック及びピンホールなどの様な構造欠陥が最善され、
均質度（homogeneity）も改善される。ここで、誘電体
としてのＴａＯＮ膜は非晶質状態でも結晶質状態でも高
誘電率を確保できるため、どの状態でも本発明のキャパ
シタに適用可能である。尚、本実施例では結晶質状態の
ＴａＯＮ膜４４ａが誘電体膜として用いられる。At this time, although not shown in the figure, the TaON film 44 in an amorphous state is formed in-situ or ex-situ in order to secure interface characteristics without a high temperature process for crystallization. Plasma heat treatment is performed in an NH 3 gas atmosphere at 200 to 600 ° C., or nitridation is performed in an N 2 O gas atmosphere. Thereby, structural defects such as microcracks and pinholes at the interface of the TaON film 43 are optimized,
The homogeneity is also improved. Here, since the TaON film as a dielectric can secure a high dielectric constant in an amorphous state or a crystalline state, the TaON film can be applied to the capacitor of the present invention in any state. In this embodiment, the crystalline TaON film 44a is used as a dielectric film.

【００１９】次に、図５に示す様に、上部電極５０は、
ＴａＯＮ膜４４ａ上に形成される。上部電極５０は、ド
ープトポリシリコン膜またはＴｉＮ、ＴａＮ、Ｗ、Ｗ
Ｎ、ＷＳｉ、Ｒｕ、ＲｕＯ2、Ｉｒ、ＩｒＯ2 またはＰ
ｔの様な金属層で形成される。ドープトポリシリコン膜
が上部電極５０で用いる場合、ドープトポリシリコン膜
は約１０００乃至１５００Å厚さで蒸着されるのが望ま
しい。また、金属層が上部電極５０で用いる場合、金属
層は約１００乃至６００Å厚さで形成されるのが望まし
い。合わせて、ポリシリコン膜はＣＶＤ方式にて形成さ
れることができ、金属層はＬＰＣＶＤ、ＰＥＣＶＤ、Ｒ
Ｆマグネチックスパッダリング法の何れかの一方法にて
形成されることができる。Next, as shown in FIG. 5, the upper electrode 50
It is formed on the TaON film 44a. The upper electrode 50 is made of a doped polysilicon film or TiN, TaN, W, W
N, WSi, Ru, RuO 2 , Ir, IrO 2 or P
It is formed of a metal layer such as t. When a doped polysilicon film is used for the upper electrode 50, the doped polysilicon film is preferably deposited to a thickness of about 1000 to 1500 degrees. When a metal layer is used for the upper electrode 50, the metal layer is preferably formed to a thickness of about 100 to 600 degrees. In addition, the polysilicon film can be formed by the CVD method, and the metal layer can be formed by LPCVD, PECVD, R
It can be formed by any one of the F magnetic padding method.

【００２０】（実施例２）また、本実施例は別のＳｉＯ
Ｎ膜の形成方法に関するもので、ＳｉＯＮ膜の形成方法
の以外は実施例１と同様である。(Embodiment 2) In this embodiment, another SiO 2
The present embodiment relates to a method for forming an N film, and is the same as Example 1 except for the method for forming an SiON film.

【００２１】本実施例におけるＳｉＯＮ膜は、次の様な
方法にて形成される。まず、下部電極の表面はＮＨ3 プ
ラズマガス雰囲気で窒化処理される。その後、窒化処理
された下部電極の表面は高真空状態で酸化される。そう
すると、窒化処理された表面は酸化と結合して、下部電
極表面にＳｉＯＮ膜が形成される。ここで、高真空状態
で酸化工程はチャンバで行われる酸化速度よりも遅いた
め、ＳｉＯＮ膜の酸素含量が少なくなる。これにより、
ＳｉＯＮ膜の誘電特性が改善されて、キャパシタンスが
増加する。The SiON film in this embodiment is formed by the following method. First, the surface of the lower electrode is nitrided in an NH 3 plasma gas atmosphere. Thereafter, the surface of the lower electrode subjected to the nitriding treatment is oxidized in a high vacuum state. Then, the nitrified surface is combined with the oxidation, and a SiON film is formed on the lower electrode surface. Here, in the high vacuum state, the oxidation process is slower than the oxidation speed performed in the chamber, so that the oxygen content of the SiON film is reduced. This allows
The dielectric characteristics of the SiON film are improved, and the capacitance is increased.

【００２２】[0022]

【発明の効果】本実施例によれば、下部電極の形成段階
と、ＴａＯＮ誘電体膜の形成段階との間に、ＴａＯＮ膜
と下部電極との間の酸化反応を抑制する為に、シリコン
窒酸化膜が形成される。このようなシリコン窒酸化膜
は、下部電極との仕事関数差がシリコン窒酸化膜に比べ
て顕著に大きいため、リーク電流を効果的に防止でき
る。合わせて、低温で形成されるため、既に形成されて
いるトランジスタの電気的特性に影響を及ぼさない。According to the present embodiment, between the step of forming the lower electrode and the step of forming the TaON dielectric film, silicon nitride is used to suppress an oxidation reaction between the TaON film and the lower electrode. An oxide film is formed. Such a silicon oxynitride film has a significantly larger work function difference from the lower electrode than the silicon oxynitride film, so that a leak current can be effectively prevented. In addition, since the transistor is formed at a low temperature, it does not affect the electrical characteristics of the transistor which is already formed.

【００２３】また、シリコン窒酸化膜の形成工程は、下
部電極の形成工程とin-situにて形成されるため、製造
工程が単純になる。Further, the step of forming the silicon oxynitride film is performed in-situ with the step of forming the lower electrode, so that the manufacturing process is simplified.

【００２４】さらに、ＴａＯＮ膜は安定したＴａ-Ｏ-Ｎ
膜で構成され、構造的に安定した状態を維持して、上部
及び下部電極と酸化反応性が小さいため、誘電体膜の厚
さが増加するのを防止できる。Further, the TaON film has a stable Ta—O—N
Since it is composed of a film and maintains a structurally stable state and has low oxidation reactivity with the upper and lower electrodes, an increase in the thickness of the dielectric film can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図１】従来の半導体素子のキャパシタを示す断面図で
ある。FIG. 1 is a sectional view showing a capacitor of a conventional semiconductor device.

【図２】本発明の実施例１による半導体素子のキャパシ
タを説明するための断面図である。FIG. 2 is a cross-sectional view illustrating a capacitor of a semiconductor device according to a first embodiment of the present invention.

【図３】本発明の実施例１による半導体素子のキャパシ
タを説明するための断面図である。FIG. 3 is a cross-sectional view illustrating a capacitor of the semiconductor device according to the first embodiment of the present invention.

【図４】本発明の実施例１による半導体素子のキャパシ
タを説明するための断面図である。FIG. 4 is a sectional view illustrating a capacitor of the semiconductor device according to the first embodiment of the present invention.

【図５】本発明の実施例１による半導体素子のキャパシ
タを説明するための断面図である。FIG. 5 is a sectional view illustrating a capacitor of the semiconductor device according to the first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

３０ 半導体基板 ３３ ゲート電極 ３５ 接合領域 ４０ 下部電極 ４２ シリコン窒酸化膜 ４４ 非晶質状態のＴａＯＮ膜 ４４ａ 結晶質状態のＴａＯＮ膜 ５０ 上部電極 Reference Signs List 30 semiconductor substrate 33 gate electrode 35 bonding region 40 lower electrode 42 silicon oxynitride film 44 amorphous TaON film 44a crystalline TaON film 50 upper electrode

Claims (23)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上にドープトシリコン物質で
下部電極を形成する段階；前記下部電極表面にシリコン
窒酸化膜を形成する段階；前記シリコン窒酸化膜上にＴ
ａ化学蒸気、Ｏ2 ガス及びＮＨ3ガスの反応によりＴａ
ＯＮ膜を形成する段階；及び、 前記ＴａＯＮ膜上に上部電極を形成する段階を含み、 前記シリコン窒酸化膜は２００乃至６００℃の温度範囲
で形成することを特徴とする、半導体メモリ素子のキャ
パシタの製造方法。Forming a lower electrode of a doped silicon material on a semiconductor substrate; forming a silicon oxynitride film on the surface of the lower electrode;
aTa by reaction of chemical vapor, O 2 gas and NH 3 gas
Forming an ON film; and forming an upper electrode on the TaON film, wherein the silicon oxynitride film is formed in a temperature range of 200 to 600 ° C. Manufacturing method. 【請求項２】 前記シリコン窒酸化膜は、ＮＨ3 ガス及
びＯ2ガスまたはＮ2Ｏガスを供給してプラズマ処理によ
って形成されることを特徴とする、請求項１記載の半導
体メモリ素子のキャパシタの製造方法。2. The capacitor of claim 1, wherein the silicon oxynitride film is formed by plasma processing by supplying NH 3 gas, O 2 gas, or N 2 O gas. Manufacturing method. 【請求項３】 前記シリコン窒酸化膜の形成段階におい
て、ＮＨ3ガスを先に注入し、その後、Ｏ2 ガスまたは
Ｎ2 Ｏガスを注入することを特徴とする、請求項２記載
の半導体メモリ素子のキャパシタの製造方法。3. The semiconductor memory according to claim 2, wherein in the step of forming the silicon oxynitride film, NH 3 gas is injected first, and then O 2 gas or N 2 O gas is injected. A method for manufacturing an element capacitor. 【請求項４】 前記シリコン窒酸化膜の形成段階は、Ｎ
Ｈ3プラズマガス雰囲気で下部電極の表面を窒化させる
段階と、前記下部電極の表面を高真空酸化させる段階と
を含むことを特徴とする、請求項１記載の半導体メモリ
素子のキャパシタの製造方法。4. The method according to claim 1, wherein the step of forming the silicon oxynitride film comprises:
A step of nitriding the surface of the lower electrode in H 3 plasma gas atmosphere, characterized in that the surface of the lower electrode and a step of high vacuum oxide, method for manufacturing a capacitor of a semiconductor memory device according to claim 1, wherein. 【請求項５】 前記シリコン窒酸化膜の形成段階と前記
ＴａＯＮ膜の形成段階は、in-situにて行われることを
特徴とする、請求項１記載の半導体メモリ素子のキャパ
シタの製造方法。5. The method of claim 1, wherein the step of forming the silicon oxynitride film and the step of forming the TaON film are performed in-situ. 【請求項６】 前記ＴａＯＮ膜は、３００乃至６００℃
及び０.１乃至１.２Torrを維持するＬＰＣＶＤチャンバ
内で形成されることを特徴とする、請求項１記載の半導
体メモリ素子のキャパシタの製造方法。6. The TaON film has a temperature of 300 to 600 ° C.
2. The method as claimed in claim 1, wherein the capacitor is formed in an LPCVD chamber maintaining 0.1 to 1.2 Torr. 【請求項７】 前記Ｔａ化学蒸気は、タンタルを含む前
駆体が１５０乃至２００℃で蒸発されて得られることを
特徴とする、請求項１記載の半導体メモリ素子のキャパ
シタの製造方法。7. The method of claim 1, wherein the Ta chemical vapor is obtained by evaporating a precursor containing tantalum at 150 to 200 ° C. 【請求項８】 前記シリコン窒酸化膜及びＴａＯＮ膜の
形成段階時に注入されるＯ2ガス及びＮＨ3 ガスは、各
々１０乃至１０００sccmだけであることを特徴とする、
請求項２記載の半導体メモリ素子のキャパシタの製造方
法。8. The O 2 gas and the NH 3 gas injected during the step of forming the silicon oxynitride film and the TaON film are only 10 to 1000 sccm, respectively.
A method for manufacturing a capacitor of a semiconductor memory device according to claim 2. 【請求項９】 前記ＴａＯＮ膜の形成段階と、前記上部
電極の形成段階との間に、前記ＴａＯＮ膜の熱処理段階
をさらに行うことを特徴とする、請求項１記載の半導体
メモリ素子のキャパシタの製造方法。9. The method according to claim 1, further comprising performing a heat treatment step on the TaON film between the step of forming the TaON film and the step of forming the upper electrode. Production method. 【請求項１０】 前記ＴａＯＮ膜の熱処理段階は、ＮＨ
3 ガスまたはＮ2/Ｈ 2 プラズマガス雰囲気のＬＰＣＶＤ
チャンバ内で、２００乃至６００℃で熱処理されること
を特徴とする、請求項９記載の半導体メモリ素子のキャ
パシタの製造方法。10. The heat treatment of the TaON film is performed using NH3.
Three Gas or NTwo/ H Two LPCVD in plasma gas atmosphere
Heat treatment at 200 to 600 ° C. in a chamber
The semiconductor memory device according to claim 9, wherein:
Manufacturing method of pasita. 【請求項１１】 前記ＴａＯＮ膜の熱処理段階は、ＮＨ
3 、Ｎ2/Ｈ2 、Ｎ2Ｏ、Ｏ2 ガスの何れかのガス雰囲気
及び６５０乃至８００℃を維持するＲＴＰチャンバまた
は電気炉内で、３０秒乃至３０分間熱処理されることを
特徴とする、請求項９記載の半導体メモリ素子のキャパ
シタの製造方法。11. The heat treatment step of the TaON film is performed by NH 3
3 , heat-treated for 30 seconds to 30 minutes in an RTP chamber or an electric furnace maintaining a gas atmosphere of any of N 2 / H 2 , N 2 O and O 2 gas and 650 to 800 ° C. 10. A method for manufacturing a capacitor of a semiconductor memory device according to claim 9. 【請求項１２】 半導体基板上にドープトシリコン物質
で下部電極を形成する段階；前記下部電極表面にシリコ
ン窒酸化膜をin-situにて形成する段階；前記シリコン
窒酸化膜上にＴａ化学蒸気、Ｏ3 ガス及びＮＨ3ガスの
反応によりＴａＯＮ膜を形成する段階；前記ＴａＯＮ膜
を熱処理する段階；及び、 前記ＴａＯＮ膜上に上部電極を形成する段階を含み、 前記シリコン窒酸化膜の形成段階はＴａＯＮ膜の形成段
階とin-situにて行われ、 前記シリコン窒酸化膜は、２００乃至６００℃及びプラ
ズマ雰囲気で、ＮＨ3ガス供給後にＯ2 ガスまたはＮ2
Ｏガスを供給して形成することを特徴とする、半導体メ
モリ素子のキャパシタの製造方法。12. A step of forming a lower electrode using a doped silicon material on a semiconductor substrate; a step of forming a silicon oxynitride film on the lower electrode surface in-situ; and a step of forming a Ta chemical vapor on the silicon oxynitride film. Forming a TaON film by a reaction of O 3 gas and NH 3 gas; heat treating the TaON film; and forming an upper electrode on the TaON film, forming the silicon nitride oxide film. Is performed in-situ with the step of forming a TaON film. The silicon oxynitride film is formed at 200 to 600 ° C. and in a plasma atmosphere after supplying NH 3 gas and O 2 gas or N 2 gas.
A method for manufacturing a capacitor of a semiconductor memory device, characterized by forming by supplying O gas. 【請求項１３】 前記ＴａＯＮ膜は、３００乃至６００
℃及び０.１乃至１.２Torrを維持するＬＰＣＶＤチャン
バ内で形成されることを特徴とする、請求項１２記載の
半導体メモリ素子のキャパシタの製造方法。13. The TaON film may have a thickness of 300 to 600.
13. The method of claim 12, wherein the capacitor is formed in an LPCVD chamber maintained at a temperature of 0.1 to 1.2 Torr. 【請求項１４】 前記Ｔａ化学蒸気は、タンタルを含む
前駆体が１５０乃至２００℃で蒸発されて得られること
を特徴とする、請求項１３記載の半導体メモリ素子のキ
ャパシタの製造方法。14. The method of claim 13, wherein the Ta chemical vapor is obtained by evaporating a precursor containing tantalum at 150 to 200 ° C. 【請求項１５】 前記シリコン窒酸化膜及びＴａＯＮ膜
の形成段階時に注入されるＯ2ガス及びＮＨ3 ガスは、
各々１０乃至１０００sccmだけであることを特徴とす
る、請求項１４記載の半導体メモリ素子のキャパシタの
製造方法。15. The O 2 gas and the NH 3 gas injected during the step of forming the silicon oxynitride film and the TaON film,
15. The method according to claim 14, wherein each of the capacitors is only 10 to 1000 sccm. 【請求項１６】 前記ＴａＯＮ膜の熱処理段階は、ＮＨ
3 ガスまたはＮ2/Ｈ 2 プラズマガス雰囲気のＬＰＣＶＤ
チャンバ内で、２００乃至６００℃で熱処理されること
を特徴とする、請求項１５記載の半導体メモリ素子のキ
ャパシタの製造方法。16. The heat treatment of the TaON film may include NH 3
Three Gas or NTwo/ H Two LPCVD in plasma gas atmosphere
Heat treatment at 200 to 600 ° C. in a chamber
16. The key of the semiconductor memory device according to claim 15, wherein
Manufacturing method of Japan. 【請求項１７】 前記ＴａＯＮ膜の熱処理段階は、ＮＨ
3 、Ｎ2/Ｈ2 、Ｎ2Ｏ、Ｏ2 ガスの何れかのガス雰囲気
及び６５０乃至８００℃を維持するＲＴＰチャンバまた
は電気炉内で、３０秒乃至３０分間熱処理されることを
特徴とする、請求項１５記載の半導体メモリ素子のキャ
パシタの製造方法。17. The heat treatment of the TaON film may include NH 3
3 , heat-treated for 30 seconds to 30 minutes in an RTP chamber or an electric furnace maintaining a gas atmosphere of any of N 2 / H 2 , N 2 O and O 2 gas and 650 to 800 ° C. A method for manufacturing a capacitor of a semiconductor memory device according to claim 15. 【請求項１８】 半導体基板上にドープトシリコン物質
で下部電極を形成する段階；前記下部電極表面にシリコ
ン窒酸化膜をin-situにて形成する段階；前記シリコン
窒酸化膜上にＴａ化学蒸気、Ｏ3 ガス及びＮＨ2ガスの
反応によりＴａＯＮ膜を形成する段階；前記ＴａＯＮ膜
を熱処理する段階；及び、 前記ＴａＯＮ膜上に上部電極を形成する段階を含み、 前記シリコン窒酸化膜の形成段階はＴａＯＮ膜の形成段
階とin-situにて行われ、 前記シリコン窒酸化膜は２００乃至６００℃で形成さ
れ、 前記シリコン窒酸化膜の形成段階は、ＮＨ3 プラズマガ
ス雰囲気で下部電極の表面を窒化させる段階と、前記下
部電極の表面を高真空酸化させる段階とを含むことを特
徴とする、半導体メモリ素子のキャパシタの製造方法。18. A step of forming a lower electrode using a doped silicon material on a semiconductor substrate; a step of forming a silicon oxynitride film on the surface of the lower electrode in-situ; and a step of forming a Ta chemical vapor on the silicon oxynitride film. Forming a TaON film by a reaction of O 3 gas and NH 2 gas; heat treating the TaON film; and forming an upper electrode on the TaON film, forming the silicon nitride oxide film. Is performed in-situ with a step of forming a TaON film, the silicon oxynitride film is formed at a temperature of 200 to 600 ° C., and the step of forming the silicon oxynitride film is performed in a NH 3 plasma gas atmosphere. A method of manufacturing a capacitor of a semiconductor memory device, comprising a step of nitriding and a step of oxidizing a surface of the lower electrode with high vacuum. 【請求項１９】 前記ＴａＯＮ膜は、３００乃至６００
℃及び０.１乃至１.２Torrを維持するＬＰＣＶＤチャン
バ内で形成されることを特徴とする、請求項１８記載の
半導体メモリ素子のキャパシタの製造方法。19. The TaON film may have a thickness of 300 to 600.
20. The method according to claim 18, wherein the capacitor is formed in an LPCVD chamber maintained at a temperature of 0.1 to 1.2 Torr. 【請求項２０】 前記Ｔａ化学蒸気は、タンタルを含む
前駆体が１５０乃至２００℃で蒸発されて得られること
を特徴とする、請求項１９記載の半導体メモリ素子のキ
ャパシタの製造方法。20. The method of claim 19, wherein the Ta chemical vapor is obtained by evaporating a precursor containing tantalum at 150 to 200 ° C. 【請求項２１】 前記ＴａＯＮ膜の形成段階時に注入さ
れるＯ2ガス及びＮＨ3 ガスは、各々１０乃至１０００s
ccmだけであることを特徴とする、請求項１８記載の半
導体メモリ素子のキャパシタの製造方法。21. The O 2 gas and the NH 3 gas injected during the step of forming the TaON film are each 10 to 1000 seconds.
19. The method of claim 18, wherein the capacitance is only ccm. 【請求項２２】 前記ＴａＯＮ膜の熱処理段階は、ＮＨ
3 ガスまたはＮ2/Ｈ 2 プラズマガス雰囲気のＬＰＣＶＤ
チャンバ内で、２００乃至６００℃で熱処理されること
を特徴とする、請求項１８記載の半導体メモリ素子のキ
ャパシタの製造方法。22. The heat treatment step of the TaON film is performed by NH 3
Three Gas or NTwo/ H Two LPCVD in plasma gas atmosphere
Heat treatment at 200 to 600 ° C. in a chamber
The key of the semiconductor memory device according to claim 18, characterized in that:
Manufacturing method of Japan. 【請求項２３】 前記ＴａＯＮ膜の熱処理段階は、ＮＨ
3 、Ｎ2/Ｈ2 、Ｎ2Ｏ、Ｏ2 ガスの何れかのガス雰囲気
及び６５０乃至８００℃を維持するＲＴＰチャンバまた
は電気炉内で、３０秒乃至３０分間熱処理されることを
特徴とする、請求項１８記載の半導体メモリ素子のキャ
パシタの製造方法。23. The heat treatment of the TaON film is performed using NH 3
3 , heat-treated for 30 seconds to 30 minutes in an RTP chamber or an electric furnace maintaining a gas atmosphere of any of N 2 / H 2 , N 2 O and O 2 gas and 650 to 800 ° C. The method for manufacturing a capacitor of a semiconductor memory device according to claim 18, wherein:
JP2000199534A 1999-07-02 2000-06-30 Manufacture of capacitor of semiconductor memory element Pending JP2001053255A (en)

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KR10-1999-0026503A KR100519514B1 (en) 1999-07-02 1999-07-02 Method of forming capacitor provied with TaON dielectric layer
KR1999/P26503 1999-07-02

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001257208A (en) * 1999-12-29 2001-09-21 Hynix Semiconductor Inc Method for forming gate insulating film of semiconductor device
CN112086441A (en) * 2020-08-26 2020-12-15 中国电子科技集团公司第十三研究所 Passive device preparation method and passive device

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