TW474000B - Method of manufacturing capacitor for semiconductor device - Google Patents

Method of manufacturing capacitor for semiconductor device Download PDF

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Publication number
TW474000B
TW474000B TW089113015A TW89113015A TW474000B TW 474000 B TW474000 B TW 474000B TW 089113015 A TW089113015 A TW 089113015A TW 89113015 A TW89113015 A TW 89113015A TW 474000 B TW474000 B TW 474000B
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Taiwan
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layer
oxynitride
gas
oxygen
patent application
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TW089113015A
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Chinese (zh)
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Dong-Su Park
Se-Min Lee
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Hyundai Electronics Ind
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02249—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by combined oxidation and nitridation performed simultaneously
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

This invention provides method of manufacturing capacitor for semiconductor device. According to the present invention, the method includes following steps: a bottom electrode formed on a semiconductor substrate using doped silicon material; forming silicon oxynitride layer on the substrate; forming tantalum oxynitride through chemical reaction among silicon oxynitride, tantalum chemical vapor, oxygen and ammonium; and finally forming an upper electrode on the tantalum oxynitride layer, in which the silicon oxynitride is formed at the temperature range between 200 and 600 DEG C.

Description

474nnn474nnn

五、發明說明（1) <發明之領域> 本發明係有關一種在半 方法’而且更特別的是_種 氮化钽（TaON )層當作其介 <發明之背景> ' 導體記憶體元件中電容之製造 在半導體記憶體元件中使用氧 電層的電容之製造方法。 近 體元件 有的面 料，構 此，目 大的電 所以可 是擴大 容的電 元件中 五氧化 構的下 取記憶體（DRAM )半導 單一個記憶體細胞所伯 準的讀出所儲存的資 要足夠大的電容值。g 導體元件需要由擁有輕 所構成的記憶體核心。 的絕緣體當作介電層遠 e)的表面積來增加電 ^，存取記憶體半導骨 較高於氧化氮（NO ) & 並在附近形成立體矣V. Description of the invention (1) < Field of invention > The present invention relates to a semi-method 'and more particularly _ a kind of tantalum nitride (TaON) layer as its intermediary < Background of the invention > Manufacturing of Capacitor in Memory Element A manufacturing method of a capacitor using an oxygen electric layer in a semiconductor memory element. There are fabrics for near-body components. For this reason, the large-capacity electricity can expand the capacity of the pentoxide structure of the electrical component. The DRAM semi-conductor reads the stored information in a single memory cell. Be sufficiently large. g The conductive element requires a memory core made up of light. The insulator is used as a dielectric layer far away from the surface area of e) to increase electricity, access to memory semiconducting bone is higher than nitrogen oxide (NO) & and forms a three-dimensional

的記憶體細胞數目的增加， 積逐漸減小。此外，為了精 成這些記憶體細胞的電容需 前的動態隨機存取記憶體$ 容值同時佔有小面積的Ϊ容 以藉由使用具有高介電係數 下端電極（L〇Wer EUct'r〇d 容值。而在高度整合的動能 ，目前是使用呈有八+〆心 /、虿介電係數 二钽（Ta205 )層做為介 端電極。 貝As the number of memory cells increases, the volume decreases. In addition, in order to refine the capacitance of these memory cells, the value of the dynamic random access memory (SDRAM) is required while occupying a small area of capacitance, by using a low-end electrode with a high dielectric constant (L0Wer EUct'r〇d). Capacitance value. At the time of highly integrated kinetic energy, a layer of tantalum (Ta205) with a dielectric constant of 〆 + 〆 // 虿 is used as the terminal electrode.

然而，因為使用五氧化二紐層人 計量學（Stoichioine1;ry )上為〗丨電層具有在化學 穩定的狀態，必須在沈積完五^不德—定性，所以為了達到 過程。同時，五氧化二鉅層彳艮^ :，層之後再進行氧化 學作用而增加了介電層的厚声^ 口為與下端電極產生化 外，因為五氧化二起層是使=減少了電容值。此 (precursor)所形成的， ♦金屬物質為前導物 所以仍然會有大量的碳及破化However, because the use of pentoxide pentoxide measurement (Stoichioine1; ry) is as follows: the electrical layer is in a chemically stable state, and it must be completed in five years. It is not qualitative, so in order to achieve the process. At the same time, the giant pentoxide layer is thickened. After the layer is oxidized, the thick sound of the dielectric layer is increased. ^ This is to reduce the capacitance with the lower electrode, because the pentoxide layer is used to reduce the capacitance. value. This (precursor) is formed. The metal substance is the lead, so there will still be a lot of carbon and decomposition.

第4頁 4740(1() 五、發明說明（2) m，因而很容易產生漏電流 口此，為了解决五氧化二鈕層這些 經在韓國專利申請案第99_2421 8號中提出：：,前我們已 (TaON )層做為介電材料的電容。在乳虱化鈕 氧氮化钽層為介電質的電容的橫剖面圖/所顯示是以 請參照们圖，一個 絕緣層12的間極電極1 3根據已知的方法(如e ) (substrate) 1()上，而場氧化===體基板 f在被選擇的部分裡。☆半導體基扪。上，_ = ” regl0n ) 14形成在閘極電極接面區域 SI一固金屬氧化半導體（廳）電晶體，而第一= 緣層18亦形成在半導體基板1〇上二及 开接觸洞（St〇rage — node contact hole) h則是 露ii:;層絕緣層16和第二層絕緣層18之間，因此：顯 術护点^域U。一個圓柱狀的下端電極20根據已知的技 祕=成在儲存點接觸洞h内，以接觸到顯露於外的接面區 " 為了增加下端電極2 〇的表面積，在其上面形成一個 乂為了避免在下端電極2〇及半球面顆粒狀層21的表面上 ^成天然的氧化層，必須在溫度範圍由8 5 0到9 5 0 °C的氨 王NH3)電漿氣體中進行一些前置處理。由於這個前置處 理’形成了第二層絕緣層18，而其中一個氮化矽（SixNy ) a 2 2則松演著阻止下端電極2 0及半球面顆粒狀層2 1產生氧 化反應的角色。一個氧氮化鈕層2 3經由钽化學蒸汽、氨氣 m 第5頁 474 η η η 五、發明說明（3) ' " '一· 及氧氣的表面化學作用形成在氮化矽層22之上，緊接著此 氧氮化鈕層2 3在經由熱處理後於其上形成結晶化，而上端 電極（upper electrode) 25亦結晶化在此。這個氧氮化 钽層23具有非常高的介電係數（£ = 2〇〜25 )和穩定的 钽-氧-氮鍵結結構。因此，氧氮化鈒層23在沈積完不需要 額外的處理就可以達到穩定的狀態，而且其很低的氧化反 應’使得不會增加介電層的厚度。 然而，在沈積氧氮化鈕層23之前，為了避免形成天然 的氧化層，必須先在溫度超過80(rCT進行一些處理。因 此，由於這樣會熔化掉下端電極及其他由熔點低於8〇Qt 的物質所構成的電極，所以在實、西^ 過8〇(TC的熱處理。 π小“執仃/皿度起 數的ΐ:置f?:所形成的氮化石夕層22雖然具由低介電係 罢功函數上跟以多晶石夕層為材料的下端電 才。㈢的爰異部偏低，因此會產生漏電流。 <發明之總論> ,因此，本發明之目的是提供一 中能藉由不使用高溫熱處理來排記憶體元件 處電晶體劣化的電容製造方丨。除天然乳化層以避免較低 此外，本發明之另一目的是提供一 元件中能避免漏電流的電容製造方法。 體纪憶體 依據為了達到本發明目的的一 在半導體記憶體元件中電容的製造方法；^ =實施例，一種 驟：以摻雜（doped )的矽為材~料形成^含了下列的步 风低而电極於半導體 474nrm 五、發明說明（4) 低端電極的表面上形成氧氮化矽（Si0N)層； 廿开彡占气> 崧汽、氧氣和氨氣產生化學反瘅 ΠϊΓ) 上；最後在氧氮化鈕層形成上端i 而其中氧氮化石夕層是形成在溫度範圍由2。。到6 0 0 γ 材料nf他具體實施例的方法步驟如下：以掺雜的石夕為 m、r形成氧氮化石夕層；藉由氧氮化石夕層與叙 其：:u::: m匕學反應並形成氧氮化组層於 上端恭搞ii 處理；最後在氧氮化鈕層形成 的形：步驟；一：成)步驟包含了氧氮化㈣ -^ II ® ^2〇〇 ,J6〇〇 〇c τ ；； ^ ^ 氣後再通入氧氣或一氧化二氮所形成…精由先通入氮 步驟的電d:提供：種在半導體記憶體中包含下列Page 4740 (1 () V. Description of the invention (2) m, so it is easy to generate leakage current. Therefore, in order to solve the second pentoxide layer, these problems have been proposed in Korean Patent Application No. 99_2421 8 :, before We have (TaON) layer as the capacitor of the dielectric material. The cross section of the capacitor with tantalum oxynitride layer on the papillae button as a dielectric / shown is shown in the figure. The electrode 1 3 is on a known method (such as e) (substrate) 1 (), and the field oxidation === the body substrate f is in the selected part. ☆ Semiconductor substrate. On, _ = ”regl0n) 14 A solid metal oxide semiconductor (hall) transistor is formed in the gate electrode contact area SI, and the first = edge layer 18 is also formed on the semiconductor substrate 10 and the contact hole (St〇rage — node contact hole) h is formed. Then it is exposed ii: between the layer of insulating layer 16 and the second layer of insulating layer 18, so: the apparent protection point ^ field U. A cylindrical lower electrode 20 according to known techniques = into contact holes at the storage point Within h, in order to contact the exposed interface area " In order to increase the surface area of the lower electrode 20, a乂 In order to avoid the formation of a natural oxide layer on the surface of the lower electrode 20 and the hemispherical granular layer 21, it is necessary to perform some in the plasma gas of ammonia king NH3) in the temperature range from 850 to 950 ° C. Pre-treatment. Due to this pre-treatment, a second insulating layer 18 is formed, and one of the silicon nitride (SixNy) a 2 2 loosely prevents the lower electrode 20 and the hemispherical granular layer 21 from oxidizing. The role of an oxynitride button layer 2 3 is formed by tantalum chemical vapor and ammonia m Page 5 474 η η η 5. Description of the invention (3) '"' One and the surface chemical action of oxygen is formed on silicon nitride Above the layer 22, the oxynitride button layer 23 is crystallized immediately after the heat treatment, and the upper electrode 25 is also crystallized there. This tantalum oxynitride layer 23 has a very high Dielectric constant (£ = 20 ~ 25) and stable tantalum-oxygen-nitrogen bonding structure. Therefore, the hafnium oxynitride layer 23 can reach a stable state without additional treatment after deposition, and it is very stable. The low oxidation reaction 'does not increase the thickness of the dielectric layer. However, in Before depositing the oxynitride button layer 23, in order to avoid the formation of a natural oxide layer, some treatment must be performed at a temperature exceeding 80 ° C. Therefore, this will melt off the lower electrode and other materials with a melting point lower than 80Qt. The electrode is formed, so the heat treatment is performed at a temperature of 80 ° C. The π is smaller than the minimum value of 起 / 皿 degree: set f ?: Although the nitrided layer 22 is formed by a low dielectric system The work function is followed by the lower end of the polycrystalline stone layer as the material. The difference of is low, so leakage current is generated. < Summary of the invention > Therefore, an object of the present invention is to provide a capacitor manufacturing method capable of eliminating transistor deterioration at a memory element by not using high temperature heat treatment. In addition to the natural emulsified layer to avoid lowering, another object of the present invention is to provide a capacitor manufacturing method capable of avoiding leakage current in a device. In order to achieve the purpose of the present invention, the body is based on a method for manufacturing a capacitor in a semiconductor memory device; ^ = embodiment, a step: doped silicon is used as a material to form the material ^ contains the following steps The wind is low and the electrode is on the semiconductor 474nrm. 5. Description of the invention (4) A silicon oxynitride (Si0N) layer is formed on the surface of the low-end electrode; ) Above; finally, the upper end i is formed on the oxynitride button layer, and the oxynitride layer is formed in the temperature range from 2. . The method steps from 6 to 0 0 γ material nf in his specific embodiment are as follows: the doped stone is used as m and r to form an oxynitride layer; and the oxynitride layer is used to describe the u ::: m The reaction and the formation of the oxynitride group layer are performed on the upper end of the ii treatment; the final shape formed on the oxynitride button layer: steps; one: into) the step includes rhenium oxynitride-^ II ® ^ 2〇〇, J6〇〇〇c τ ;; ^ ^ gas and then pass oxygen or nitrous oxide formed ... refined by the first nitrogen pass electricity d: provided: a semiconductor memory contains the following

:導體基板上；在低端電極的表面夕=:开“：低端電極於 虱化矽層；藉由氧氮化，U)， 氧產生化學反應並形成氧氮化 盆η、氧乳和I 化”；ΐ氣：紐層形成上端電極，其中氧氮 化石夕層是形i在、ϋ^(ιη situ)形成的。而氧氮 含了下列：到6 0 0 °CT，其形成步驟包 吉… 在乱甩聚乳體下氮化下端電極的主 、^ /、二狀態下氧化下端電極的表面。 、、面；並在南 第7頁 474nnn 五、發明說明（5) <較佳具體實施例之詳細描述> [具體實施例1 ] 請參照第2A圖，場氧化層31根據已知的方法形 有經挑選過的電導性的半導體基板3〇中經挑選過的 /、 i已含著閘極絕緣層32的閘極输 據已知的方法形成在半導體基板3〇上，而間隔 i3酋4:據已知的方法形成在閘極電極33的兩端邊壁上。Τ 而口此形成了 一個金屬氧化半導體（MOS )電f雕。望 一層絕緣層3 6和第二層絕緣声3 8亦开彡成/ 曰月且 上。之後，*篡制策： +導體基板30 t. 山再摹衣弟—層絕緣層36和第二層絕緣層38，因 妾著ΪΓΓ分的接面區域35形成了储存點接觸洞Η。 ΐί 端電極4〇並接觸顯露出的接面區域35。 此特，下端電極40是以堆疊狀（stack)、 (cylinder)、韓狀（fin)或堆疊_圓柱 狀 :二式形成。以本具體實 時，下端恭柱狀的形式形成的。此 晶矽層形】ϋ =由經摻雜的多晶矽層或是經摻雜的非 曰/成。而且為了增加下端電極4〇 . ^ ^ 個半球面顆粒㈣（沒有顯示：匕在= 粒狀層'’下端電極4°通常由經換雜的非晶- (沒ΪΪ亍ί 2免在下端電極40和稍後形成的介電層 有,‘.、員不在圖中）之間的介面上形成低介電值的天然氧: On the conductor substrate; on the surface of the low-end electrode =: on ": the low-end electrode on the silicon layer; by oxynitriding, U), oxygen produces a chemical reaction and forms an oxynitride basin η, oxygen milk, and Ionization "; radon gas: the button layer forms the upper electrode, where the oxynitride layer is formed in the shape of i, situ. Oxygen and nitrogen contain the following: to 600 ° CT, its formation steps include ... Nitriding the surface of the lower electrode in the main, ^ /, and two states of the lower electrode under random polyemulsion. , 面; and page 474nnn on the south page 5. Explanation of the invention (5) < Detailed description of the preferred embodiment > [Detailed embodiment 1] Please refer to FIG. 2A, the field oxide layer 31 according to the known Methods A gate electrode selected from a selected conductive semiconductor substrate 30, i, which has a gate insulating layer 32 formed thereon is formed on the semiconductor substrate 30 by a known method, and an interval i3 is formed. Emirates 4: It is formed on the both side walls of the gate electrode 33 according to a known method. As a result, a metal oxide semiconductor (MOS) electrode is formed. It is expected that one layer of insulation 36 and the second layer of insulation sound 3 8 will be opened and closed. After that, the * tampering policy: + Conductor substrate 30 t. Yamazaki Yoshiki-layer insulation layer 36 and second layer insulation layer 38, the storage point contact hole 因 is formed due to the contact area 35 of ΪΓΓ points. The terminal electrode 40 is in contact with the exposed interface area 35. Here, the lower electrode 40 is formed in a stack, a cylinder, a fin, or a stack-cylindrical shape. It is formed in a columnar form at the lower end in this concrete case. This crystalline silicon layer shape] ϋ = consists of a doped polycrystalline silicon layer or a doped non-crystalline silicon layer. And in order to increase the lower end electrode 40. ^ ^ hemispherical particles 没有 (not shown: dagger at = granular layer `` lower end electrode 4 ° is usually made of amorphous by replacement-(无 ΪΪ 亍 ί 2 free at the lower end electrode 40 and the dielectric layer to be formed later, a low dielectric value of natural oxygen is formed on the interface between the '., The member is not shown in the figure)

第8頁 474ηηηPage 8 474ηηη

化層’必須在低端電極的表面上形成氧氮化矽層42，而為 了使低端電極的劣化情形降到最小，此氧氮化矽層42必須 在服度範圍由2 〇 〇到6 〇 〇 °C下形成。此時，氧氮化;5夕層4 2是 將低端電極4〇在電漿氣體下經由氮化處理所形成的。而氮 化處理過程是在低壓化學汽相沈積（LPCVD )的腔體 (C^hamber )裡通入1〇到lOOOsccm的氨氣和氧氣或一氧化 二氮氣體進行。在此氮化處理中，氨氣是在氧氣或一氧化 二氮氣體之前通入，因此可以阻止氧氣或一氧化二氮氣體 與下端電極4 0額外的化學反應。 此氧氮化矽層4 2在功函數上與下端電極4 〇差異很大， 所以八g產生很小的漏電流，而且是形成在溫度範圍由 2 0 0到6 0 Q °C下。因此，此氧氮化矽層42對於之前形成的電 晶體在電性上沒有任何影響。 如第2B圖所示，做為介電層的氧氮化鈕層44是藉由以 鈕有機金屬物質如Ta(0C2H5)5 (乙醇化鈕）為前導物再與 鈕化學洛汽、氧氣和氨氣產生化學作用形成在氧氮化矽層 42上。而组化學蒸汽、氧氣和氨氣最好跟晶圓片（㈣卜厂 ^，在氣相反應的限制狀態下產生化學反應。此外，沈積 氧氮化钽層4 4的厚度最好在8 〇到2 〇 〇 a之間。此時，氧氮 化組層44最好使用化學汽相沈積方法如在溫度大約由3 〇 〇 到60(TC及壓力由0.1到ι·2陶爾（Torr)下的低壓化學汽 相沈積方法來形成。其中，前導物例如乙醇化钽是液態 的，因此在轉換成氣態後才通入低壓化學汽相沈積的腔體 中。此前導物是根據已知的方法轉換成鈕化學蒸汽，此方The siliconization layer must form a silicon oxynitride layer 42 on the surface of the low-end electrode, and in order to minimize the degradation of the low-end electrode, the silicon oxynitride layer 42 must be in a range of 2000 to 6 Formed at 00 ° C. At this time, the oxynitriding layer 52 is formed by subjecting the low-end electrode 40 to a nitriding process under a plasma gas. The nitriding process is carried out by passing in a low pressure chemical vapor deposition (LPCVD) chamber (C ^ hamber) with ammonia gas and oxygen gas or nitrous oxide gas at 10 to 1000 sccm. In this nitriding treatment, ammonia gas is introduced before the oxygen or nitrous oxide gas, so it can prevent the oxygen or the nitrous oxide gas from additional chemical reaction with the lower electrode 40. This silicon oxynitride layer 42 has a large difference in work function from the lower electrode 4 0, so a small leakage current of 8 g is generated, and it is formed at a temperature range from 200 to 60 Q ° C. Therefore, the silicon oxynitride layer 42 has no influence on the electrical properties of the previously formed transistor. As shown in FIG. 2B, the oxynitride button layer 44 as a dielectric layer is prepared by using a button organometallic material such as Ta (0C2H5) 5 (ethanolated button) as a precursor, and then combined with button chemical vapor, oxygen, and Ammonia is chemically formed on the silicon oxynitride layer 42. The chemical vapor, oxygen, and ammonia gas are preferably reacted with the wafer (the factory), and the chemical reaction is limited under the gas-phase reaction. In addition, the thickness of the deposited tantalum oxynitride layer 4 is preferably 80. Between 2000a. At this time, the oxynitride group layer 44 is preferably formed by a chemical vapor deposition method such as at a temperature of from about 300 to 60 (TC and pressure from 0.1 to ι · 2 Torr). It is formed by the low-pressure chemical vapor deposition method. Among them, the lead such as tantalum ethanolate is liquid, so it only passes into the cavity of the low-pressure chemical vapor deposition after being converted into a gaseous state. The previous guide is based on known Method to convert button chemical vapor to this side

第9頁 474ηηη 五、發明說明（7) 法是將適量的前導物流經流量控制器如全部流量控制器 (Mass Flow Controller，簡稱MFC)再通入蒸發器 (Evaporizeir)或是蒸發管（Evap〇rati on tube )中。之 後’通入蒸發器或是蒸發管中前導物會在溫度範圍由1 5 〇 到2 0 0 °C下被蒸發形成鈕的化學蒸汽狀態。接著，通入低 壓化學汽相沈積腔體中鈕化學蒸汽和氧氣及氨氣互相產生 表面化學作用，因此形成了非晶狀態的氧氮化鈕層44。其 中’通入的氧氣及氣氣為1Q到lQQQsccm，而氧I化叙層Μ 是事中（in si tu )和藉由氧氮化矽層42的形成過程所形 成的。 之後，如第2C圖所示 ^ 將非晶狀態下的氧氮化钽層44 進行快速的熱處理或是置於溫度範圍由6 5 〇到8 〇 〇 ^下包含 著氮或氧的氣體如氨氣、氮和氫的混和氣體、一氧化二氮 或氧氣的爐管中30秒至30分鐘。由於此熱處理使得氧氮^ 钽層44變成具有較密鍵結結構的單晶狀氧氮化鈕層44^。 雖然在圖中沒有顯示，& 了得到在不使用高溫處理下 結晶化的介面特性，會對氧氮化鈕層44在溫度範圍由 到60(TC的氨氣下藉由電漿進行事中（in sUu)或事前 j ex situ )熱處理，或是在一氧化二氮氣體下進行氮化 处理。因此，修補了在氧氮化鈕層44介面上一歧結構上Page 9 474ηηη 5. Description of the invention (7) The method is to pass an appropriate amount of the lead stream through a flow controller, such as all flow controllers (Mass Flow Controller, MFC), and then into the evaporator (Evaporizeir) or the evaporation tube (Evap). rati on tube). After that, the lead is introduced into the evaporator or the evaporation tube, and the lead will be evaporated to form a chemical vapor state of the button at a temperature ranging from 150 to 200 ° C. Next, the chemical vapor of the button, oxygen and ammonia gas are introduced into the low pressure chemical vapor deposition chamber to cause surface chemical interaction with each other, so that an oxynitride button layer 44 in an amorphous state is formed. The oxygen and gas that are passed through are 1Q to 1QQQsccm, and the oxygen ionization layer M is formed in the process and formed by the formation process of the silicon oxynitride layer 42. Afterwards, as shown in FIG. 2C ^, the tantalum oxynitride layer 44 in an amorphous state is subjected to rapid heat treatment or placed in a temperature range from 650 to 800, such as a gas containing nitrogen or oxygen such as ammonia Gas, nitrogen and hydrogen mixed gas, nitrous oxide or oxygen in the furnace tube for 30 seconds to 30 minutes. Due to this heat treatment, the oxynitride tantalum layer 44 becomes a single crystal oxynitride button layer 44 ^ having a denser bonding structure. Although it is not shown in the figure, & obtained the interface characteristics of crystallization without using high temperature treatment, the oxynitride button layer 44 in the temperature range from 60 to 60 (TC ammonia in the plasma to do the work (In sUu) or prior j ex situ) heat treatment, or nitriding treatment under a nitrous oxide gas. Therefore, a heterogeneous structure is repaired on the interface of the oxynitride button layer 44

Ulcro cracks) (pin h〇-s)#^ 且，:了其同貝性（hom〇geneity )。其中，做為介電質 的虱II化钽層不論是在非晶狀態或、 高的介電係數，因此其任何狀態也許都可以使用Ulcro cracks) (pin h〇-s) # ^ And, its homogeneity (homomogeneity). Among them, the tantalum II tantalum layer as a dielectric is in an amorphous state or a high dielectric constant, so any state may be used.

五、發明說明（8) ^的電纟。此夕卜，在本具體實施例中，是以單晶狀態的氧 氮化组層44a做為介電層。5. Description of the invention (8) ^ 's electricity. Furthermore, in this embodiment, a single crystal oxynitride group layer 44a is used as the dielectric layer.

之後，士口第2D圖所示，在氧氮化纽層…上形成上端 電極50，而此上端電極可以藉由摻雜的多晶矽層或是金屬 層如氮化欽（TiN )、氮化叙（TaN )、鎢（w )、氮化鎢 (WN)、石夕化鶴（WSl)、舒（Ru)、二氧化釕（Ru〇2 )、銥（Ir)、二氧化銥（Ir〇2)或是鉑（pt )所構成。 如果是使用摻雜的多晶矽層做為上端電極5〇時，最好沈積 在厚度大約由1 0 0 0到1 50 0人之間，而如果是使用金屬潘做 為上知屯極50時，最好沈積在厚度大約由1〇〇到6〇〇人之 間、。此外，摻雜的多晶矽層可以根據已知的化學汽相沈積 方法形成，而金屬層可以根據低壓化學汽相沈積、電漿增 強化學汽相沈積（PECVD)或是射頻磁性濺鍍（RF magnetlc sputtering)其中之_的方法形成。 [具體貫施例2 ] 本具體實施例係有關一種形成另一個氧氣化石夕層的方 /二而且除了形成氧象化石夕層的方法之外，#餘的部分皆 契弟一項具體實施例相同。 在本具體貫施例中的氧氮化矽層是根據下列的方法所 形成的。 理Ιί，在氨電漿氣體下對下端電極的表面進行氮化處 於接者將氮化的表面在高真空狀態下氧化。氮化的表面 由於、、Ό合了氧化過程，因而在下端電極的表面上形 化矽層。其中，因為氧化過程是在高真空狀態下進行的二Then, as shown in Figure 2D of Shikou, an upper electrode 50 is formed on the oxynitride layer ... The upper electrode can be doped with a polycrystalline silicon layer or a metal layer such as Nitride (TiN) or Nitride. (TaN), tungsten (w), tungsten nitride (WN), Shixi Chemical Crane (WS1), Shu (Ru), ruthenium dioxide (Ru〇2), iridium (Ir), iridium dioxide (Ir〇2 ) Or platinum (pt). If a doped polycrystalline silicon layer is used as the upper electrode 50, it is better to deposit it in a thickness of about 100 to 1500 people, and if a metal pan is used as the upper electrode 50, It is best to deposit between about 100 and 600 people in thickness. In addition, the doped polycrystalline silicon layer may be formed according to a known chemical vapor deposition method, and the metal layer may be formed according to a low pressure chemical vapor deposition, a plasma enhanced chemical vapor deposition (PECVD), or a radio frequency magnetic sputtering. ) One of the methods formed. [Specific Implementation Example 2] This specific embodiment is related to a method of forming another oxygen fossil layer and in addition to the method of forming an oxygen-like fossil layer, the remaining parts are all specific examples. the same. The silicon oxynitride layer in this embodiment is formed by the following method. The reason is that the surface of the lower electrode is nitrided under an ammonia plasma gas. The nitrided surface is oxidized under a high vacuum state. Nitrided surface A silicon layer is formed on the surface of the lower electrode due to the oxidation process. Among them, because the oxidation process is performed under high vacuum

474Π〇η 五、發明說明（9) 所以比起在 使氧氮化矽 介電性質， 根據本 氧氮化鈕介 组層和低端 化石夕層在功 避免漏電流 因此對於之 而且氧氮化 的，因此簡 另外， 在匕具有穩定 電極產生化 藉由熟 且可以立即 及精神時，474Π〇η V. Description of the invention (9) Therefore, compared with the dielectric properties of silicon oxynitride, according to the present oxynitride button dielectric layer and the low-end fossil layer, the leakage current is avoided in the work. Therefore, in addition, when the dagger has a stable electrode that can be transformed and cooked immediately and mentally,

腔體中的氧化過程 層的氧含量較少。 即增加了電容量。 層是形成在低端電極與 主要是為了限制氧氮化 相對於氮化矽層，氧氮 报大，因此可以有效的 是在低溫之下形成的， 特性上沒有任何影響。 中（in situ )形成 ’其氧化速率較低，而且也 因此，增加了氧氮化矽層的 具體實施例，氧氮化矽 電層的形成步驟之間， 電極之間的氧化反應。 函數上與低端電極差異 。此外，此氧氮化矽層 前形成的電晶體在介電 矽層和下端電極皆是事 化了製造過程。 年L 化姐層是以 — 一 的結構。而且氧氮化鈕層不容易:::下： 學作用，因此可以避免增加介電層的厚产 練的技巧’其他各式各樣的修正形：明 被實現出來，但是此種修正若未本發明的範； 摩在本發明的申請專利範圍之内，謹先陳明。 474nrm 圖式簡單說明 弟1圖為傳統半導體記憶體元件中電容的橫剖面圖。 第2Α到2D圖是為了描述依據本發明第一項具體實施例 的半導體記憶體電容的橫剖面圖。 圖式中元件名稱與符號 1 0 :半導體基板 11 :場氧化層 12 :絕緣層 13 :閘極電極 14 :接面區域 16 :第一層絕緣層 18 :第二層絕緣層 2 0 :下端電極 2 1 :半球面顆粒狀層 2 2 :氮化矽層 2 3 :氧氮化钽層 2 5 :上端電極 3 0 :半導體基板 31 ··場氧化層 3 2 :間極絕緣 3 3 ·閘極電緣 3 4 :間隔物 3 5 :接面區域 3 6 :第一層絕緣層 3 8 _·第二層絕緣層The oxidation process layer in the cavity has less oxygen content. That is, the capacitance is increased. The layer is formed on the low-end electrode and is mainly used to limit the oxynitride. Compared with the silicon nitride layer, the oxynitride is large, so it can be effectively formed at low temperatures without any impact on the characteristics. In-situ formation has a lower oxidation rate, and therefore, a specific embodiment of a silicon oxynitride layer is added, and an oxidation reaction between electrodes is formed between steps of forming a silicon oxynitride electrical layer. Functionally different from the low-end electrode. In addition, the transistor formed before this silicon oxynitride layer is a manufacturing process for both the dielectric silicon layer and the lower electrode. The L-level sister layer is a one-year structure. And the oxynitride button layer is not easy ::: Next: Learn the function, so you can avoid the thick production skills of increasing the dielectric layer. 'Other various modifications: Apparently implemented, but this kind of correction The scope of the present invention is within the scope of the patent application of the present invention. 474nrm diagram brief description Di Figure 1 is a cross-sectional view of a capacitor in a conventional semiconductor memory device. 2A to 2D are cross-sectional views for describing a semiconductor memory capacitor according to a first embodiment of the present invention. Element names and symbols in the drawing 1 0: semiconductor substrate 11: field oxide layer 12: insulating layer 13: gate electrode 14: junction area 16: first insulating layer 18: second insulating layer 2 0: lower electrode 2 1: Hemispherical granular layer 2 2: Silicon nitride layer 2 3: Tantalum oxynitride layer 2 5: Upper electrode 3 0: Semiconductor substrate 31 · Field oxide layer 3 2: Inter-electrode insulation 3 3 · Gate Electric edge 3 4: Spacer 3 5: Junction area 3 6: First insulating layer 3 8 _ · Second insulating layer

第13頁 474nnnPage 13 474nnn

第14頁Page 14

Claims (1)

47400() 六、申請專利範圍 1. 一種在半導體基板上製造電容的方法，其中包含下 列步驟： 以摻雜的矽物質形成下端電極於半導體基板上； 在下端電極的表面上形成氧氮化矽層； 藉由與钽化學蒸汽、氧氣和氨氣的化學作用，在氧氮 化矽層上形成氧氮化鈕層；且 在氧氮化组層上形成上端電極， 其中氧氮化矽層是在溫度範圍由2 0 0到6 0 0 °C下所形成 的。 2. 如申請專利範圍第1項之方法，其中氧氮化矽層是 藉由通入氨氣和氧氣或氮氣之電漿處理所形成的。 3. 如申請專利範圍第2項之方法，其中在氧氮化矽層 的形成步驟裡是先通入氨氣之後再通入氧氣或氮氣的。 4. 如申請專利範圍第1項之方法，其中氧氮化矽層的 形成步驟包含了下列步驟：在氨電漿氣體下氮化下端電極 的表面；並且在高真空狀態下氧化下端電極的表面。 5. 如申請專利範圍第1項之方法，其中氧氮化矽層和 氧氮化组層的形成步驟都是事中（i n s i t u )進行的。 6. 如申請專利範圍第1項之方法，其中氧氮化钽層是 在維持溫度範圍由3 0 0到6 0 0 °C，壓力範圍由0 . 1到1. 2陶爾 下的低壓化學汽相沈積腔體中所形成的。 7. 如申請專利範圍第1項之方法，其中鈕化學蒸汽是 經由在溫度範圍由1 5 0到2 0 0 °C下蒸發含有鈕金屬的前導物 所得到的。47400 (6) Application scope 1. A method for manufacturing a capacitor on a semiconductor substrate, comprising the following steps: forming a lower electrode on the semiconductor substrate with a doped silicon substance; forming silicon oxynitride on the surface of the lower electrode An oxynitride button layer is formed on the silicon oxynitride layer through chemical interaction with tantalum chemical vapor, oxygen, and ammonia; and an upper electrode is formed on the oxynitride group layer, wherein the silicon oxynitride layer is Formed in a temperature range from 200 to 600 ° C. 2. The method according to item 1 of the patent application, wherein the silicon oxynitride layer is formed by plasma treatment with ammonia and oxygen or nitrogen gas. 3. The method according to item 2 of the scope of patent application, wherein in the step of forming the silicon oxynitride layer, ammonia gas is first passed through and then oxygen or nitrogen gas is passed through. 4. The method according to item 1 of the patent application, wherein the step of forming a silicon oxynitride layer includes the following steps: nitriding the surface of the lower electrode under an ammonia plasma gas; and oxidizing the surface of the lower electrode under a high vacuum state . 5. The method according to item 1 of the scope of patent application, wherein the steps of forming the silicon oxynitride layer and the oxynitride group layer are performed in-process (i n s i t u). 6. The method according to item 1 of the patent application, wherein the tantalum oxynitride layer is a low-pressure chemical under a maintenance temperature range from 300 to 600 ° C and a pressure range from 0.1 to 1.2 Formed in a vapor deposition chamber. 7. The method of claim 1 in which the button chemical vapor is obtained by evaporating a precursor containing a button metal at a temperature ranging from 150 to 200 ° C. 第15頁 474nnn 六、申請專利範圍 8. 如申請專利範圍第2項之方法，其中在氧氮化矽層 和氧氮化组層的形成步驟裡，氧氣和氨氣分別注入1 0到 1 0 0 0 seem。 9. 如申請專利範圍第1項之方法，其中在氧氮化鈕層 與上端電極的形成步驟之間加入氧氮化鈕層的熱處理步 驟。 1 0.如申請專利範圍第9項之方法，其中氧氮化鈕層的 熱處理步驟是在溫度範圍由2 0 0到6 0 0 t下充滿氨氣或是氮 氣與氫氣的混和電漿氣體的低壓化學汽相沈積腔體中所進 行的。 11. 如申請專利範圍第9項之方法，其中氧氮化钽層的 熱處理步驟是進行在氨氣、氮和氫的混和氣體、一氧化二 氮或氧氣其中之一的氣體環境下，置於快速熱處理（RTP )腔體中維持溫度範圍由6 5 0到8 0 0 t或是置於爐管中3 0秒 至3 0分鐘。 12. —種在半導體基板上製造電容的方法，其中包含 下列步驟： ， 以摻雜的矽物質形成下端電極於半導體基板上； 在下端電極的表面上事中（in situ)形成氧氮化石夕 層； 藉由與鈕化學蒸汽、氧氣和氨氣的化學作用，在氧氮 化矽層上形成氧氮化钽層； 對氧氮化钽層進行熱處理；且 在氧氮化组層上形成上端電極，Page 15 474nnn VI. Application scope of patent 8. The method of the second scope of patent application, wherein in the step of forming the silicon oxynitride layer and the oxynitride group layer, oxygen and ammonia are injected into the range of 10 to 10, respectively. 0 0 seem. 9. The method according to item 1 of the patent application scope, wherein a heat treatment step of the oxynitride button layer is added between the step of forming the oxynitride button layer and the upper electrode. 10. The method according to item 9 of the scope of patent application, wherein the heat treatment step of the oxynitride button layer is filled with ammonia gas or a mixed plasma gas of nitrogen and hydrogen at a temperature ranging from 200 to 600 t. Low pressure chemical vapor deposition in a cavity. 11. The method according to item 9 of the patent application, wherein the heat treatment step of the tantalum oxynitride layer is performed under a gas environment of one of ammonia gas, nitrogen and hydrogen mixed gas, nitrous oxide or oxygen gas, and The rapid heat treatment (RTP) cavity maintains a temperature range from 650 to 800 t or is placed in a furnace tube for 30 seconds to 30 minutes. 12. A method for manufacturing a capacitor on a semiconductor substrate, comprising the following steps: forming a lower electrode on the semiconductor substrate with a doped silicon substance; forming an oxynitride on the surface of the lower electrode in situ A tantalum oxynitride layer is formed on the silicon oxynitride layer by chemical interaction with the button chemical vapor, oxygen and ammonia gas; the tantalum oxynitride layer is heat-treated; and an upper end is formed on the oxynitride group layer electrode, 第16頁 六、申請專利範 圍 其中氧氮化矽層的形成步驟包含了氧氮化钽層的形成 ^驟以及事中（i n s i t u )過程，而氧氮化矽，層是在溫度 纯圍由200到600 °C的電漿氣體下先通入氨氣後再通入氧氣 或一氧化二氮所形成的。 ^ 1 3 ·如申請專利範圍第1 2項之方法，其中氧氮化钽層 疋在維持溫度範圍由3 0 0到6 0 0 °C，壓力範圍由〇 . 1到1 · 2陶 爾下的低壓化學汽相沈積腔體中所形成的。 θ 14 ·如申請專利範圍第1 3項之方法，其中鈕化學蒸汽 ^經由在溫度範圍由150到2 0 0。〇下蒸發含有钽金的前 物所得到的。 甸q刖VSixteenth, the scope of the patent application where the step of forming a silicon oxynitride layer includes the steps of forming the tantalum oxynitride layer and the insitu process, and the layer of silicon oxynitride is purely at 200 ° C in temperature. When the plasma gas reaches 600 ° C, ammonia gas is introduced first, and then oxygen or nitrous oxide is passed. ^ 1 3 · The method according to item 12 of the patent application range, in which the tantalum oxynitride layer is maintained at a temperature range from 300 to 600 ° C and a pressure range from 0.1 to 1.2 Formed in a low-pressure chemical vapor deposition chamber. θ 14 · The method according to item 13 of the patent application range, wherein the chemical vapor is passed through the temperature range from 150 to 200. It was obtained by evaporating the precursor containing tantalum at 0 ° C. Dianq 刖 V 15·如申請專利範圍第14項之方法，其中在 層和氧氮化鈕層的形成步驟裡，氧氣和氨氣分別注^入， lOOOsccm。 u 1 6·如申請專利範圍第丨5項之方法，其中氧氮化鈕 的，處理步驟是在溫度範圍由20 0到6 0 0 °C下充滿氨氣一或曰， 二氣2氫氣的混和電漿氣體的低壓化學汽相沈積腔=^ j15. The method according to item 14 of the scope of patent application, wherein in the step of forming the layer and the oxynitride button layer, oxygen gas and ammonia gas are injected separately, 1000 sccm. u 1 6 · The method according to item 5 of the patent application range, in which the oxynitride button is processed at a temperature range of 20 to 60 ° C, filled with ammonia gas one or two, two gas and two hydrogen gas. Low-pressure chemical vapor deposition chamber mixed with plasma gas = ^ j 17·如申請專利範圍第15項之方法，其中氧氮 的熱處，步驟是進行在氨氣、氮和氫的混和氣體、層 一亂或氧氣其中之_的氣體環境下，置於快速熱處理羊 (RTP )腔體中維持溫度範圍由65〇到8〇(rc 中30秒至30分鐘。 i %爐官 18· —種在半導體基板上製造電容的方法，复 下列步驟： ，、甲包含17. The method according to item 15 of the scope of patent application, wherein the heat treatment of oxygen and nitrogen is carried out in a rapid heat treatment under the environment of ammonia, a mixed gas of nitrogen and hydrogen, a layer of disorder, or one of oxygen. Sheep (RTP) cavity maintains a temperature range from 65 to 80 (30 seconds to 30 minutes in rc. I% furnace officer 18 ·-a method of manufacturing a capacitor on a semiconductor substrate, repeating the following steps: 第17頁 六、申請專利範園 以摻难Μ 在下端带Ζ物質形成下端電極於半導體基板上； 形成氧氮化石夕 層； 包極的表面上事中（insitu 切層;ϊ = ϋ層氧氣和氨氣的化學作用，在氧氮 ，乳氮化叙層進行熱處理；且 $氧组層上形成上端電極， SitM、I氧f：化石夕f和氧氮化组層的形成步驟是事中（in 下所形成=、且而氧氮化矽層是在溫度範圍由2 〇 〇到6 0 G °C 體下：：:匕石夕層的形成步驟包含了下列步驟：纟氨電聚氣 電極“表：端電極的表面；&且在高真空狀態下氧化下端 19如申請專利範圍第18項之方法，纟中氧氮化组層 、准持溫度範圍由3 0 0到6 0 0 T：，壓力範圍由〇·丄到丨.2陶 下的低屋化學汽相沈積腔體中所形成的。 曰2 0 ·命申睛專利範圍第1 g項之方法，其中钽化學蒸汽 是經由在溫度範圍由15〇a20(rc下蒸發含有钽金屬的前導 物所得到的。 2 1 ·如申請專利範圍第1 8項之方法，其中在氧氮化矽 層和氧氮化组層的形成步驟裡，氧氣和氨氣分別注入丨0到 1 0 0 0 sccm。 22·如申請專利範圍第18項之方法，其中氧氮化鈕層 的熱處理步驟是在溫度範圍由2 〇 〇到6 0 0 °C下充滿氨氣或是Page 17 VI. Applying for a patent Fan Yuan uses doped M to form a lower electrode on the semiconductor substrate with a Z material at the lower end; forms an oxynitride layer; on the surface of the clad electrode (insitu cutting layer; ϊ = ϋ layer of oxygen With the chemical action of ammonia, heat treatment is performed on the oxygen, nitrogen, and oxynitriding layers; and the upper electrode is formed on the oxygen group layer, SitM, I oxygen f: the formation steps of the fossil evening f and oxynitride layer are in the process (The formation of in ==, and the silicon oxynitride layer is in the temperature range from 2000 to 60 G ° C body :: The step of forming the dagger layer includes the following steps: ammonia gas polymerization Electrode "table: the surface of the terminal electrode; & and oxidize the lower end 19 in a high vacuum state as described in the method of patent application No. 18, the oxynitride group layer, the quasi-hold temperature range from 3 0 to 6 0 0 T: The pressure range is from 0 · 丄 to 丨 .2 formed in the low-house chemical vapor deposition chamber. The method of item 1g of Ming Shenjing's patent scope, where tantalum chemical vapor is Obtained by evaporating a lead containing tantalum metal at a temperature in the range of 150a20 (rc. 2 1 For example, the method of claim 18 in the scope of patent application, wherein in the step of forming the silicon oxynitride layer and the oxynitride group layer, oxygen and ammonia gas are injected respectively from 0 to 100 0 sccm. The method of item 18, wherein the heat treatment step of the oxynitride button layer is filled with ammonia gas at a temperature ranging from 2000 to 600 ° C or 第18頁 474nnn 六、申請專利範圍 氮氣與氫氣的混和電漿氣體的低壓化學汽相沈積腔體中所 進行的。 2 3.如申請專利範圍第1 8項之方法，其中氧氮化钽層 的熱處理步驟是進行在氨氣、氮和氫的混和氣體、一氧化 二氮或氧氣其中之一的氣體環境下，置於快速熱處理 (RTP )腔體中維持溫度範圍由6 5 0到8 0 0 〇C或是置於爐管 中3 0秒至3 0分鐘。Page 18 474nnn VI. Scope of patent application It is performed in a low-pressure chemical vapor deposition chamber of a plasma gas mixture of nitrogen and hydrogen. 2 3. The method according to item 18 of the scope of patent application, wherein the heat treatment step of the tantalum oxynitride layer is performed under a gas environment of one of ammonia gas, nitrogen and hydrogen mixed gas, nitrous oxide or oxygen, Placed in a rapid thermal processing (RTP) cavity to maintain a temperature range from 650 to 800 ° C or placed in a furnace tube for 30 seconds to 30 minutes. 第19頁Page 19
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