KR100882090B1 - Method for fabricating capacitor of semiconductor device - Google Patents
Method for fabricating capacitor of semiconductor device Download PDFInfo
- Publication number
- KR100882090B1 KR100882090B1 KR1020020087207A KR20020087207A KR100882090B1 KR 100882090 B1 KR100882090 B1 KR 100882090B1 KR 1020020087207 A KR1020020087207 A KR 1020020087207A KR 20020087207 A KR20020087207 A KR 20020087207A KR 100882090 B1 KR100882090 B1 KR 100882090B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- hfo
- capacitor
- heat treatment
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000003990 capacitor Substances 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 238000003860 storage Methods 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 239000007789 gas Substances 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 claims description 25
- 229910052760 oxygen Inorganic materials 0.000 claims description 17
- 239000012298 atmosphere Substances 0.000 claims description 11
- 239000000243 solution Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims description 3
- 230000008016 vaporization Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 150000002736 metal compounds Chemical class 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 74
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000010410 layer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- -1 for example Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002902 organometallic compounds Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- VUZPPFZMUPKLLV-UHFFFAOYSA-N methane;hydrate Chemical compound C.O VUZPPFZMUPKLLV-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로서, 캐패시터의 유전막을 HfSiON막과 HfO2막의 적층 구조로 형성하되, 상기 HfSiON막은 질화막과 HfO2막을 열처리하여 변환시켜 형성하였으므로, 유전율이 24∼40 인 고유전율의 HfO2 막을 유전막으로 사용하여 등가산화막의 두께를 감소시켜 정전용량을 증가시키고, HfSiON막을 HfO2 막과 전하저장전극 사이에 개재시켜 누설전류를 양산 수준인 셀당 0.5fA 이하로 유지하고, 항복전압을 7MV/㎝ 이상으로 유지하여, 정전용량 확보에 용이하고, 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a dielectric film of a capacitor is formed in a stacked structure of an HfSiON film and an HfO 2 film, and the HfSiON film is formed by heat-treating a nitride film and an HfO 2 film, and thus has a dielectric constant of 24 to 40. Using a high dielectric constant HfO 2 film as a dielectric film, the thickness of the equivalent oxide film is reduced to increase the capacitance, and the HfSiON film is interposed between the HfO 2 film and the charge storage electrode to maintain a leakage current of 0.5 fA or less, which is a mass production level. By maintaining the breakdown voltage at 7 MV / cm or more, it is easy to secure the capacitance, and the process yield and the reliability of device operation can be improved.
Description
도 1은 종래 기술에 따른 반도체소자의 캐패시터의 단면도. 1 is a cross-sectional view of a capacitor of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자 캐패시터의 제조공정도. 2a to 2d is a manufacturing process diagram of a semiconductor device capacitor according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 층간절연막 12 : 전하저장전극 10: interlayer insulating film 12: charge storage electrode
14 : 콘택플러그 16, 30 : 전하저장전극14:
18 : 유전막 20, 40 : 플레이트전극18:
32 : 질화막 34 : 제1HfO2막32: nitride film 34: first HfO 2 film
36 : HfSiON막 38 : 제2HfO2막36: HfSiON film 38: 2nd HfO 2 film
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로서, 특히 고유전막을 안정적으로 형성하여 유전막의 두께를 감소시키고, 누설전류 및 항복전압 특성을 향상시켜 소자의 고집적화에 유리하고 공정 수율 및 소자 동작의 신뢰성을 향상 시킬 수 있는 반도체소자의 캐패시터 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, the high dielectric film is stably formed to reduce the thickness of the dielectric film, and the leakage current and breakdown voltage characteristics are improved, which is advantageous for the high integration of the device, and the process yield and the reliability of the device operation. It relates to a method for manufacturing a capacitor of a semiconductor device that can improve the.
일반적으로 DRAM의 기억 소자에서 캐패시터는 정보를 기억하고 판독하기 위해 일정량의 전하를 저장하는 기능을 수행한다. 따라서 캐패시터는 충분한 정전용량을 확보하여야하고, 누설전류가 적은 유전체막의 절연 특성을 가져야하며, 장시간 반복사용되는데 대한 신뢰성도 함께 지니고 있어야한다. Generally, capacitors in DRAMs store a certain amount of charge to store and read information. Therefore, the capacitor should have sufficient capacitance, have the insulating property of the dielectric film with low leakage current, and have the reliability for repeated use for a long time.
캐패시터의 정전용량은 표면적에 비례하고, 유전막의 두께에 반비례하는데, 소자가 고집적화되어감에 따라 단위 소자의 할당 면적이 감소되므로 캐패시터의 정전용량 확보가 점차 어려워지고 있으며, 이를 위하여 캐패시터의 높이는 증가되고, 인접 셀과의 공정 마진도 감소되고 있는 상황에서, 소프트 에러의 발생과 리플레쉬 시간의 감소를 방지하기 위하여 셀당 25pF 이상의 충전용량을 요구하고 있다. The capacitance of the capacitor is proportional to the surface area and inversely proportional to the thickness of the dielectric film. As the device becomes more integrated, the allocation area of the unit device decreases, making it difficult to secure the capacitance of the capacitor. In a situation where process margins with adjacent cells are also decreasing, a charge capacity of 25 pF or more is required per cell to prevent the occurrence of soft errors and a reduction in refresh time.
종래 기술에 따른 실리콘 반도체소자의 캐패시터는 실리콘-유전막-실리콘(이하 SIS라 칭함) 구조의 캐패시터로서 전하저장전극과 플레이트전극을 도핑된 실리콘을 사용하고, 유전막으로는 산화막-질화막-산화막(이하 ONO라 칭함)구조를 사용하고 있다. The capacitor of a silicon semiconductor device according to the prior art is a capacitor of silicon-dielectric film-silicon (hereinafter referred to as SIS) structure using silicon doped with charge storage electrode and plate electrode, and an oxide film-nitride film-oxide film (hereinafter ONO). Structure).
상기의 질화막은 유전율 7로서 DCS(Di-chloro-silane) 가스를 사용하여 형성되는데, 등가산화 두께를 40Å 이하로 감소시킬 수 없어, 전하저장전극의 표면적 증가를 위하여 반구형 실리콘을 사용하고, 종횡비도 증가되고 있다. The nitride film is formed using a DCS (Di-chloro-silane) gas as the dielectric constant 7, the equivalent oxidation thickness can not be reduced to less than 40Å, hemispherical silicon is used to increase the surface area of the charge storage electrode, the aspect ratio It is increasing.
이러한 질화막을 유전막으로 사용하는 캐패시터는 소자가 고집적화됨에 따라 그 높이가 증가되어 식각 공정에 어려움이 있고, 셀영역과 주변회로영역간의 단차가 증가되어 후속 노광 공정시 초점심도의 확보가 어려워 배선공정에서의 패턴불량 을 유발하는 문제점이 있어 256MDRAM 이상의 소자에서는 사용하기 어렵다.Capacitors using such nitride films as dielectric films have difficulty in etching process because their height increases as the device is highly integrated, and it is difficult to secure the depth of focus during the subsequent exposure process because the step difference between cell area and peripheral circuit area is increased. It is difficult to use in devices with more than 256MDRAM because there is a problem that causes pattern defects.
따라서 유전율이 7정도 비교적 낮은 질화막 대신에 유전율이 25 정도로 매우 큰 유전물질인 Ta2O5 박막을 사용하게 되었다. Therefore, instead of a nitride film having a relatively low dielectric constant of about 7, a Ta 2 O 5 thin film having a very high dielectric constant of about 25 was used.
도 1은 종래 기술에 따른 반도체소자 캐패시터의 단면도로서, 반구형 실리콘을 형성한 예이다. 1 is a cross-sectional view of a semiconductor device capacitor according to the prior art, in which hemispherical silicon is formed.
먼저, 반도체기판(10) 상에 전하저장전극용 콘택플러그(14)를 구비하는 층간절연막(12)을 형성하고, 상기 콘택플러그(14)와 접촉되는 실린더형 전하저장전극(16)을 다결정실리콘으로 형성하되, 표면에 반구형 실리콘층을 가지도록 형성한 후, 상기 전하저장전극(16)의 표면에 Ta2O5 재질의 유전막(18)과 플레이트전극(20)을 형성한다. First, an
그러나 상기의 Ta2O5 박막은 불안정한 화학양론비(stoichiometry)를 가지므로 Ta와 O의 조성비 차이에 의한 치환형 Ta 원자가 박막내에 존재하게 되며, 전구체인 Ta(OC2H5)5의 유기물과 O2 또는 N2O 가스의 반응으로 인하여 불순물인 C, CH4 또는 C2H4 등의 탄소원자와 탄소화합물 및 물등이 막내에 존재하게 된다. However, since the Ta 2 O 5 thin film has an unstable stoichiometry, substitutional Ta atoms exist in the thin film due to the difference in the composition ratio of Ta and O, and the organic material of the precursor Ta (OC 2 H 5 ) 5 and Due to the reaction of O 2 or N 2 O gas, carbon atoms such as C, CH 4 or C 2 H 4 , impurities, carbon compounds, and water are present in the film.
따라서 Ta2O5 막내에 존재하는 탄소, 이온 및 라디칼 등으로 인하여 캐패시터의 누설전류가 증가하고, 유전특성이 열화된다. Therefore, the leakage current of the capacitor increases and dielectric properties deteriorate due to carbon, ions, radicals, etc. present in the Ta 2 O 5 film.
더욱이 Ta2O5 막 자체의 결함으로 인하여 다결정실리콘으로된 전하저장전극과 계면에 유전율 3.85 정도의 저유전 계면 산화막이 형성되어 등가산화막 두께를 30Å 이하로 낮출 수 없어 정전용량이 제한되는 등의 문제점이 있다. Moreover, due to defects in the Ta 2 O 5 film itself, a low dielectric interfacial oxide film having a dielectric constant of about 3.85 is formed at the interface with the charge storage electrode made of polycrystalline silicon, so that the equivalent oxide film thickness cannot be lowered to 30 kΩ or less, and thus the capacitance is limited. There is this.
상술한 바와 같이 종래 기술에 따른 반도체소자의 캐패시터 제조방법은 디자인 룰의 감소로 셀 면적이 감소되어 충분한 정전용량을 확보하기 어려워지고 있어 유전막의 등가산화 두께를 감소시키는 방법으로 정전용량을 확보하여 왔으나, 질화막은 산화저항성이 40Å 이하의 두께에서 급속하게 감소되어 후속 공정시 전하저장전극이나 비트라인이 산화되고, 50Å 이하의 두께에서는 누설전류가 증가되고 절연파괴전압이 감소되어 45Å 이하의 두께로는 형성할 수 없으며, Ta2O5 막은 계면 산화막이 형성되어 등가산화막 두께를 30Å 이하로 감소시킬 수 없는 문제점이 있다. As described above, the capacitor manufacturing method of the semiconductor device according to the prior art has secured the capacitance by reducing the equivalent oxidation thickness of the dielectric film because it is difficult to secure sufficient capacitance because the cell area is reduced due to the reduction of design rules. In this case, the nitride film rapidly reduces its oxidation resistance at a thickness of 40 mA or less, so that the charge storage electrode or bit line is oxidized in a subsequent process. At a thickness of 50 mA or less, the leakage current increases and the insulation breakdown voltage decreases to a thickness of 45 mA or less. It cannot be formed, and Ta 2 O 5 has a problem in that an interfacial oxide film is formed so that the equivalent oxide film thickness cannot be reduced to 30 kPa or less.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 고유전율의 HfO2 막을 사용하여 등가산화막의 두께를 감소시켜 정전용량을 증가시키고, HfSiON막을 개재시켜 누설전류 특성이 안정되고, 항복전압을 일정수준 이상으로 유지하여, 정전용량 확보에 용이하고, 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 캐패시터 제조방법을 제공함에 있다. The present invention is to solve the above problems, an object of the present invention is to reduce the thickness of the equivalent oxide film using a high dielectric constant HfO 2 film to increase the capacitance, and to stabilize the leakage current characteristics through the HfSiON film, The present invention provides a method of manufacturing a capacitor of a semiconductor device that maintains a breakdown voltage at a predetermined level or more, and is easy to secure capacitance, and improves process yield and reliability of device operation.
본발명은 상기와 같은 목적을 달성하기 위한 것으로서, 본발명에 따른 반도체소자의 캐패시터 제조방법의 특징은, The present invention is to achieve the above object, the characteristics of the capacitor manufacturing method of a semiconductor device according to the present invention,
반도체소자의 캐패시터 제조방법에 있어서, In the method of manufacturing a capacitor of a semiconductor device,
소정의 하부 구조물을 구비하는 반도체기판상에 층간절연막을 형성하는 공정 과, Forming an interlayer insulating film on a semiconductor substrate having a predetermined lower structure;
상기 층간절연막상에 전하저장전극을 형성하는 공정과, Forming a charge storage electrode on the interlayer insulating film;
상기 전하저장전극의 표면에 DCS 가스나 액상 BTBAS 용액을 기화시킨 소스가스를 이용한 저압 화학기상증착 방법으로 질화막을 형성하는 공정과, Forming a nitride film by a low pressure chemical vapor deposition method using a source gas vaporizing a DCS gas or a liquid BTBAS solution on the surface of the charge storage electrode;
상기 질화막상에 제1HfO2막을 형성하는 공정과, Forming a first HfO 2 film on the nitride film;
상기 반도체기판을 열처리하여 상기 질화막과 제1HfO2막을 변환시켜 HfSiON막을 형성하는 공정과, Heat-treating the semiconductor substrate to convert the nitride film and the first HfO 2 film to form an HfSiON film;
상기 HfSiON막상에 제2HfO2막을 형성하는 공정과, Forming a second HfO 2 film on the HfSiON film,
상기 제2HfO2막 상에 플레이트전극을 형성하는 공정을 구비함에 있다. And forming a plate electrode on the second HfO 2 film.
또한 본 발명의 다른 특징은, 상기 질화막 형성전에 전하저장전극 표면의 자연산화막 제거 공정을 추가로 구비하고, 상기의 세정 공정은 인시튜 또는 익시튜 방법으로 HF 기상 또는 HF, NH4OH 또는 H2SO4 용액에 H2O2 와 순수가 혼합된 혼합 용액을 사용하여 실시함에 있다. In addition, another feature of the present invention, further comprising the step of removing the natural oxide film on the surface of the charge storage electrode prior to forming the nitride film, wherein the cleaning process is HF gas phase or HF, NH 4 OH or H 2 by an in situ or Isitu method This is done by using a mixed solution of H 2 O 2 and pure water mixed in a SO 4 solution.
또한 또 다른 특징은, 상기 질화막은 5∼15Å 두께로, 550∼700℃의 온도에서, 매엽식 챔버 또는 회분식 전기로를 사용하여 형성하고, 상기 액상 BTBAS를 이용한 질화막 증착 방법은 유량조절기를 통해 증발기에 공급된 BTBAS 용액을 160∼200℃ 정도로 가열하여 기상화시킨 후, 550∼700℃에서 0.1∼5torrdml 압력에서 NH3/BTBAS 1∼10 정도의 비율로 유지하면서 형성하며, 상기 제1HfO2막은 5∼20Å 두께로 화학기상증착이나 원자층증착 방법으로 200∼600℃의 범위에서 0.1∼100torr 압력에서, 소스 가스로는 C16H36HfO4 나 Hf를 포함하는 유기금속화합물를 전구체로 사용하고, 반응가스로서 O2 또는 O3를 이용하여 형성하고, 상기 HfSiON막은 10∼30Å 두께로, O2, O3, N2O 및 O2+N2 로 이루어지는 군에서 임의로 선택되는 하나 이상의 가스 분위기에서 열처리하여 형성하며, 상기 열처리 공정을 300∼500℃의 온도에서, 플라즈마 방전시킨 매엽식 챔버에서, 1∼10분 정도 0.1∼100torr 압력으로 열처리하는 저온 플라즈마 아닐링법이거나, 전기로에서 600∼800℃, 5∼120분 실시하거나, 급속열처리로서 600∼900℃, 30∼120초간 실시하며, 상기 제2HfO2막은 20∼100Å 두께로 형성하고, 상기 제2HfO2막 형성 후에 열처리를 실시하여 결정을 안정시키고, 유전율을 상승시키는 공정을 구비하며, 상기 열처리 공정은 전기로에서 600∼800℃ 에서, 5∼120분 정도를 O2, O3, N2O 또는 O2+N2 등의 가스 분위기에서 실시하거나, 급속열처리 장치를 이용하여 동일한 가스 분위기에서 600∼900℃ 온도에서 10∼100초 정도 실시하는 것을 특징으로 한다. In still another feature, the nitride film is 5 to 15 kW thick, formed at a temperature of 550 to 700 ° C. using a single chamber or a batch electric furnace, and the nitride film deposition method using the liquid BTBAS is provided to the evaporator through a flow controller. After the supplied BTBAS solution was heated to about 160 to 200 ° C. for vaporization, the BTBAS solution was formed while maintaining the ratio of NH 3 / BTBAS 1 to 10 at a pressure of 0.1 to 5 tord ml at 550 to 700 ° C., and the first HfO 2 membrane was 5 to 5 ° C. At a pressure of 0.1 to 100 torr in the range of 200 to 600 ° C by chemical vapor deposition or atomic layer deposition to a thickness of 20 kPa, an organometallic compound containing C 16 H 36 HfO 4 or Hf is used as a precursor as a reaction gas. It is formed using O 2 or O 3 , the HfSiON film is formed by heat treatment in one or more gas atmosphere arbitrarily selected from the group consisting of O 2 , O 3 , N 2 O and O 2 + N 2 to a thickness of 10 ~ 30 Å , In the low temperature plasma annealing method in which the heat treatment process is heat-treated at 0.1 to 100 torr for 1 to 10 minutes in a single chamber with plasma discharge at a temperature of 300 to 500 ° C., or 600 to 800 ° C. for 5 to 120 minutes in an electric furnace. Or a rapid heat treatment for 600 to 900 DEG C for 30 to 120 seconds, wherein the second HfO 2 film is formed to a thickness of 20 to 100 GPa, and after the formation of the second HfO 2 film, heat treatment is performed to stabilize the crystals and increase the dielectric constant. The heat treatment step is performed at 600 to 800 ° C. in an electric furnace for about 5 to 120 minutes in a gas atmosphere such as O 2 , O 3 , N 2 O or O 2 + N 2 , or using a rapid heat treatment device. It is carried out for about 10 to 100 second at 600-900 degreeC temperature in the same gas atmosphere, and is used.
이하, 본 발명에 따른 반도체소자의 캐패시터 제조방법에 관하여 첨부도면을 참조하여 상세히 설명하면 다음과 같다. Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자 캐패시터의 제조공정도이다. 2A to 2D are manufacturing process diagrams of a semiconductor device capacitor according to the present invention.
먼저, 도시되어 있지는 않으나 소정의 하부 구조물을 구비하는 반도체기판(도시되지 않음)상에 전하저장전극용 콘택플러그(도시되지 않음)를 구비하는 층간절 연막(도시되지 않음)을 도포하고, 상기 층간절연막상에 전하저장전극(30)을 실린더형이나 콘케이브형등으로 형상으로 형성한다. First, an interlayer insulation film (not shown) including a contact plug (not shown) for a charge storage electrode is coated on a semiconductor substrate (not shown), which is not shown but has a predetermined lower structure, and the interlayer The
여기서 상기 전하저장전극(30)은 도핑된 실리콘이나, 금속, 예를 들어 TiN, TaN, W, WN, Ru, RuO2, Ir, IrO2 또는 Pt 등으로 200∼1000Å의 두께로 형성된다.
The
그후, 상기 전하저장전극(30) 표면의 자연산화막을 제거하는 세정 공정을 실시할 수도 있는데, 상기의 세정 공정은 인시튜 또는 익시튜 방법으로 HF 기상 또는 HF, NH4OH 또는 H2SO4 용액에 H2O2와 순수가 혼합된 혼합 용액을 사용하여 실시한다. Thereafter, a cleaning process may be performed to remove the natural oxide layer on the surface of the
그다음 상기 전하저장전극(30)상에 5∼15Å 정도 두께의 질화막(32)과 5∼20Å 정도 두께의 제1HfO2막(34)을 순차적으로 형성한다. Next, a
여기서 상기 질화막(32)은 저압 화학기상증착 방법으로, 550∼700℃의 온도에서, 매엽식 챔버 또는 회분식 전기로를 사용하여, DCS 가스나 BTBAS[Bis(tertiary-butylamino-siline)] (SiH2[NH(C4H9)]2) 용액을 기화시킨 소스가스를 NH3 가스와 전극 표면에 반응시켜 증착한다. The
상기의 액상 BTBAS를 이용한 질화막 증착 방법은 유량조절기를 통해 증발기에 공금된 일정량의 BTBAS 용액을 160∼200℃ 정도로 가열하여 기상화시킨 후, 550∼700℃에서 0.1∼5torrdml 압력 범위, 바람직하게는 0.2∼0.5torr에서 NH3/BTBAS 1∼10 정도의 비율로 바람직하게는 NH3 200∼200cc/ BTBAS 20∼100cc를 유지하면서 5∼15Å 두께로 CVD 한다.
The nitride film deposition method using the liquid BTBAS is vaporized by heating a predetermined amount of the BTBAS solution deposited in the evaporator through a flow controller at about 160 to 200 ° C, and then at a pressure range of 0.1 to 5 torrml at 550 to 700 ° C, preferably 0.2 At a rate of about NH 3 / BTBAS 1 to 10 at -0.5 torr, CVD is performed at a thickness of 5 to 15 kPa while maintaining NH 3 200 to 200 cc /
또한 상기 제1HfO2막(34)은 화학기상증착이나 원자층증착 방법으로 200∼600℃의 범위에서 0.1∼100torr 압력하에서 형성한다. The first HfO 2 film 34 is formed under a pressure of 0.1 to 100 torr in the range of 200 to 600 ° C. by chemical vapor deposition or atomic layer deposition.
상기에서 Hf 성분의 소스 가스로는 C16H36HfO4 를 사용하거나, Hf를 포함하는 유기금속화합물를 전구체로 사용하고, 반응가스로서 O2 또는 O3를 이용한다. (도 2a 참조). As the source gas of the Hf component, C 16 H 36 HfO 4 is used, an organometallic compound containing Hf is used as a precursor, and O 2 or O 3 is used as the reaction gas. (See FIG. 2A).
그후, 상기 구조의 전표면에 기판을 저온 열처리하여 상기 질화막(32)과 제1HfO2막(34)을 10∼30Å 정도 두께의 HfSiON막(36)으로 변환시킨다. Subsequently, the substrate is subjected to low temperature heat treatment on the entire surface of the structure to convert the
이때 상기 열처리 공정은 O2, O3, N2O 또는 O2+N2 등의 가스 분위기에서 300∼500℃의 온도 범위에서 플라즈마 방전시킨 매엽식 챔버에서 1∼10분 정도 0.1∼100torr 압력으로 열처리하는 저온 플라즈마 아닐링법이나, 전기로에서 600∼800℃의 O2, O3, N2O 또는 O2+N2 등의 가스 분위기에서 5∼120분 정도 열처리하거나, 급속열처리로서 600∼900℃에서 30∼120초간 실시할 수도 있다. (도 2b 참조). At this time, the heat treatment process is 0.1 to 100 torr for about 1 to 10 minutes in the single wafer chamber plasma discharged in a temperature range of 300 to 500 ℃ in a gas atmosphere such as O 2 , O 3 , N 2 O or O 2 + N 2 Low temperature plasma annealing method for heat treatment or heat treatment at 600 to 800 ° C. for 5 to 120 minutes in a gas atmosphere such as O 2 , O 3 , N 2 O or O 2 + N 2 , or 600 to 900 ° C. as a rapid heat treatment. You can also do this for 30 to 120 seconds. (See FIG. 2B).
그다음 상기 HfSiON막(36) 상에 고유전율을 가지는 제2HfO2막(38)을 20∼100Å 정도 형성한 후, 열처리를 실시하여 상기 제2HfO2막(38)의 결정을 안정시키고, 유전율을 상승시킨다. Thereafter, a second HfO 2 film 38 having a high dielectric constant is formed on the
상기 열처리 공정은 전기로에서 600∼800℃ 온도에서, 5∼120분 정도를 O2, O3, N2O 또는 O2+N2 등의 가스 분위기에서 실시하거나, 급속열처리 장치를 이용하여 동일한 가스 분위기에서 600∼900℃ 온도에서 10∼100초 정도 실시하는데, 상기N2 분위기에서의 열처리에 의해 비정질 제2HfO2막(38)의 결정질화가 일어나고, 활성산소를 얻을 수 있는 가스 분위기에서 열처리하면 막 내부의 탄소 불순물 등이 제거되어 누설전류 특성이 향상된다. (도 2c 참조). The heat treatment step is performed at 600 to 800 ° C. in an electric furnace for about 5 to 120 minutes in a gas atmosphere such as O 2 , O 3 , N 2 O or O 2 + N 2 , or by using a rapid heat treatment apparatus. 10-100 seconds at a temperature of 600-900 DEG C in an atmosphere, wherein the crystallization of the amorphous 2HfO 2 film 38 occurs by heat treatment in the N 2 atmosphere, and the film is heat-treated in a gas atmosphere in which active oxygen can be obtained. Internal carbon impurities and the like are removed to improve leakage current characteristics. (See FIG. 2C).
그후, 상기 제2HfO2막(38) 상에 플레이트전극(40)을 형성하여 캐패시터를 완성한다. 상기 플레이트전극(40)은 도핑된 실리콘층이나, 금속, 예를 들어 TiN, TaN, W, WN, Ru, RuO2, Ir, IrO2 또는 Pt 등으로 형성된다. (도 2d 참조). Thereafter, a
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 캐패시터 제조방법은, 캐패시터의 하부 전극을 형성하고, 유전막을 HfSiON막과 HfO2막의 적층 구조로 형성하되, 상기 HfSiON막은 질화막과 HfO2막을 열처리하여 변환시켜 형성하였으므로, 유전율이 24∼40 인 고유전율의 HfO2 막을 유전막으로 사용하여 등가산화막의 두께를 감소시켜 정전용량을 증가시키고, HfSiON막을 HfO2 막과 전하저장전극 사이에 개재시켜 누설전류를 양산 수준인 셀당 0.5fA 이하로 유지하고, 항복전압을 7MV/㎝ 이상으로 유지하여, 정전용량 확보에 용이하고, 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다. As described above, in the method of manufacturing a capacitor of a semiconductor device according to the present invention, the lower electrode of the capacitor is formed, and the dielectric film is formed in a stacked structure of an HfSiON film and an HfO 2 film, wherein the HfSiON film is heat-treated by a nitride film and an HfO 2 film. Since it was formed by converting, a high dielectric constant HfO 2 film having a dielectric constant of 24 to 40 was used as the dielectric film to reduce the thickness of the equivalent oxide film to increase capacitance, and an HfSiON film was interposed between the HfO 2 film and the charge storage electrode to reduce leakage current. Maintaining a production level of 0.5 fA or less per cell and maintaining a breakdown voltage of 7 MV / cm or more, it is easy to secure capacitance, and there is an advantage of improving process yield and device operation reliability.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020087207A KR100882090B1 (en) | 2002-12-30 | 2002-12-30 | Method for fabricating capacitor of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020087207A KR100882090B1 (en) | 2002-12-30 | 2002-12-30 | Method for fabricating capacitor of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040060416A KR20040060416A (en) | 2004-07-06 |
| KR100882090B1 true KR100882090B1 (en) | 2009-02-05 |
Family
ID=37352321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020087207A KR100882090B1 (en) | 2002-12-30 | 2002-12-30 | Method for fabricating capacitor of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100882090B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101026477B1 (en) | 2004-09-13 | 2011-04-01 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100687903B1 (en) * | 2004-12-30 | 2007-02-27 | 주식회사 하이닉스반도체 | Method For Forming Dielectric film For Semiconductor device |
| KR100593752B1 (en) * | 2005-01-18 | 2006-06-28 | 삼성전자주식회사 | Method of fabricating semiconductor device including silicon nitride layer free of impurities |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000008815A (en) * | 1998-07-16 | 2000-02-15 | 윤종용 | Capacitor of semiconductor device and manufacturing method thereof |
| KR20010009834A (en) * | 1999-07-14 | 2001-02-05 | 김영환 | A method of fabricating a capacitor |
| KR20010084597A (en) * | 2000-02-28 | 2001-09-06 | 윤종용 | method for fabricating capacitor of semiconductor device |
-
2002
- 2002-12-30 KR KR1020020087207A patent/KR100882090B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000008815A (en) * | 1998-07-16 | 2000-02-15 | 윤종용 | Capacitor of semiconductor device and manufacturing method thereof |
| KR20010009834A (en) * | 1999-07-14 | 2001-02-05 | 김영환 | A method of fabricating a capacitor |
| KR20010084597A (en) * | 2000-02-28 | 2001-09-06 | 윤종용 | method for fabricating capacitor of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101026477B1 (en) | 2004-09-13 | 2011-04-01 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040060416A (en) | 2004-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6340622B1 (en) | Method for fabricating capacitors of semiconductor device | |
| JP4247421B2 (en) | Method for manufacturing capacitor of semiconductor device | |
| KR20020094461A (en) | Method of forming a capacitor of a semiconductor device | |
| KR100417855B1 (en) | capacitor of semiconductor device and method for fabricating the same | |
| JP4486735B2 (en) | Manufacturing method of capacitor of semiconductor memory device | |
| KR100464650B1 (en) | Capacitor of semiconductor device having dual dielectric layer structure and method for fabricating the same | |
| KR100497142B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100321178B1 (en) | Method of forming capacitor with TaON dielectic layer | |
| KR100504435B1 (en) | Method of forming capacitor in semiconducotr device | |
| KR100327584B1 (en) | Method of forming high efficiency capacitor in semiconductor device | |
| KR100371143B1 (en) | Method of forming high efficiency capacitor in semiconductor device | |
| JP2001057414A (en) | Capacitor for semiconductor memory element and its manufacture | |
| KR100464649B1 (en) | Capacitor of semiconductor device having dual dielectric layer structure and method for fabricating the same | |
| KR100882090B1 (en) | Method for fabricating capacitor of semiconductor device | |
| KR100342873B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100557961B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100504434B1 (en) | Method of forming capacitor | |
| KR100618682B1 (en) | Method for manufacturing capacitor in semiconductor memory divice | |
| KR20020045750A (en) | Method for manufacturing capacitor in semiconductor device | |
| KR100574473B1 (en) | Capacitor Manufacturing Method of Semiconductor Device_ | |
| KR20040059783A (en) | Method of manufacturing capacitor for semiconductor device | |
| KR20010020024A (en) | Method For Treating The High Temperature Of Tantalium Oxide Capacitor | |
| KR20030039239A (en) | Method of manufacturing capacitor in semiconductor device | |
| KR20010003784A (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR20060033468A (en) | Method for forming capacitor of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |