KR100687903B1 - Method For Forming Dielectric film For Semiconductor device - Google Patents
Method For Forming Dielectric film For Semiconductor device Download PDFInfo
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- KR100687903B1 KR100687903B1 KR1020040117311A KR20040117311A KR100687903B1 KR 100687903 B1 KR100687903 B1 KR 100687903B1 KR 1020040117311 A KR1020040117311 A KR 1020040117311A KR 20040117311 A KR20040117311 A KR 20040117311A KR 100687903 B1 KR100687903 B1 KR 100687903B1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
본 발명은 모든 고집적 반도체의 게이트 유전막 형성공정에 적용할 수 있는 반도체 소자의 유전막 형성 방법에 관한 것이다.The present invention relates to a method of forming a dielectric film of a semiconductor device that can be applied to the gate dielectric film forming process of all highly integrated semiconductors.
이는 반도체 소자의 유전막을 형성하는 방법에 있어서, 반도체 소자의 유전막을 형성하는 방법에 있어서, 실리콘 기판 상에 산화막을 형성하는 제 1과정; 상기 산화막이 그 상면에 형성된 실리콘 기판 내에 이온 주입 공정에 의해 Hf를 주입시키는 제 2과정; 상기 Hf가 주입된 실리콘 기판상의 상기 산화막을 제거하는 제 3과정; 상기 산화막이 제거되고 Hf가 주입된 실리콘 기판 상에 N2 주입하여 상기 Hf를 질화시켜 HfSixNy막을 형성하는 제 4과정; 및 상기 질화된 HfSixNy가 형성된 실리콘 기판을 퍼니스 내에서 산화시켜 HfSixOyNz막을 형성시키는 제 5과정을 포함한다.A method of forming a dielectric film of a semiconductor device, the method comprising: a first process of forming an oxide film on a silicon substrate; A second step of injecting Hf into the silicon substrate on which the oxide film is formed by an ion implantation process; A third step of removing the oxide film on the silicon substrate implanted with the Hf; A fourth step of forming an HfSixNy film by nitriding the Hf by injecting N2 onto the silicon substrate on which the oxide film is removed and Hf is injected; And a fifth process of oxidizing the nitrided HfSixNy-formed silicon substrate in a furnace to form an HfSixOyNz film.
산화막, Hf, 산화, 질화처리, 하프늄옥시나이트라이드Oxide, Hf, Oxidation, Nitriding, Hafnium Oxynitride
Description
도 1은 산화막 형성전의 실리콘 기판의 단면도이다.1 is a cross-sectional view of a silicon substrate before oxide film formation.
도 2는 도 1의 실리콘 기판 상에 스크린 산화막이 형성된 단면도이다.FIG. 2 is a cross-sectional view of a screen oxide film formed on the silicon substrate of FIG. 1.
도 3은 도 2의 실리콘 기판 내에 Hf가 주입된 단면도이다.3 is a cross-sectional view of Hf injected into the silicon substrate of FIG. 2.
도 4는 도 3의 실리콘 기판 상의 스크린 산화막이 제거된 상태를 나타낸 단면도이다.4 is a cross-sectional view illustrating a state in which a screen oxide film on the silicon substrate of FIG. 3 is removed.
도 5는 도 4의 실리콘 기판이 플라즈마 처리에 의해 질화된 상태를 나타낸 단면도이다.5 is a cross-sectional view illustrating a state in which the silicon substrate of FIG. 4 is nitrided by plasma processing.
도 6은 도 5의 실리콘 기판이 퍼니스에서 산화처리된 상태를 나타낸 단면도이다.6 is a cross-sectional view illustrating a state in which the silicon substrate of FIG. 5 is oxidized in a furnace.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 실리콘 기판 12 : 스크린 산화막10
14 : Hf
14: Hf
본 발명은 반도체 소자의 유전막 형성 방법에 관한 것으로, 모든 고집적 반도체의 게이트 유전막 형성공정에 적용할 수 있는 반도체 소자의 유전막 형성 방법에 관한 것이다.BACKGROUND OF THE
최근 소자의 크기가 작아짐에 따라 소자의 속도 향상을 위하여 문턱전압(Threshold Voltage:Vt)을 낮추는 방향으로 소자의 개발이 진행되고 있다. 문턱전압을 낮추기 위해서는 게이트 유전막의 두께를 낮추거나 게이트 유전막의 유전상수를 높여야 하는 점에서 서로 트레이드 오프(trade off) 관계를 가진다. Recently, as the size of the device becomes smaller, the device is being developed in the direction of lowering the threshold voltage (Vt) to improve the speed of the device. In order to reduce the threshold voltage, the gate dielectric layer has a trade off relationship with the gate dielectric layer in order to decrease the thickness or increase the dielectric constant of the gate dielectric layer.
현재 사용하고 있는 SiO2에서 두께가 점점 낮아져 30Å이하의 경우 직접 터널링(direct tunneling)에 의하여 SiO2의 실질적 사용이 불가능하게 된다. 그래서 현재 차세대 고 유전상수(high-k) 유전물질인 HfO2가 많이 연구되고 있다.As the thickness of SiO 2 is gradually lowered, the use of SiO 2 is impossible due to direct tunneling in the case of 30 Å or less. Therefore, HfO 2 , a next generation high-k dielectric material, is being studied.
그러나, 고 유전상수 유전물질인 HfO2가 단독으로 사용될 경우 실리콘 기판과의 계면에서 상당히 불안정한 상태를 나타내며, 그와 동시에 고온의 후속공정에 의해 기판 실리콘과 HfO2사이의 계면에서 일어나는 반응에 의해 유전상수가 상당히 낮은 물질이 형성된다. 이러한 계면 반응에 의해 유전상수가 낮은 물질이 형성되어 차세대 게이트 유전막 물질인 HfO2의 게이트 유전막의 적용에 커다란 문제로 부각된다. However, when HfO 2 , a high dielectric constant dielectric material, is used alone, it exhibits a very unstable state at the interface with the silicon substrate, and at the same time, it is caused by a reaction occurring at the interface between the substrate silicon and HfO 2 by a high temperature subsequent process. Substances with significantly lower constants are formed. Due to the interfacial reaction, a material having a low dielectric constant is formed, which is a big problem in the application of the gate dielectric film of the next-generation gate dielectric film HfO 2 .
또한, 게이트 유전체로 HfO2단독 사용하게 되면, Si계면에서 저유전물질이 형성되어 이로 인해 낮은 유전율을 가지는 문제가 있을 뿐만 아니라, 높은 트랩 전하로 인해 문턱전압의 제어가 힘든 문제가 있다.In addition, when HfO 2 alone is used as the gate dielectric, a low dielectric material is formed at the Si interface, which causes a low dielectric constant and also has a problem that it is difficult to control the threshold voltage due to a high trap charge.
또한, 높은 누설 전류로 인해 확산 장벽(diffusion barrier)층이 필요한 문제가 있다.
In addition, there is a problem that a diffusion barrier layer is required due to the high leakage current.
본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여, Hf 소스를 이온 주입 방법으로 실리콘 기판 표면에 주입시킨 후 질화막 플라즈마를 이용하여 질화시키고 이후 퍼니스 공정에서 건식 산화를 통하여 HfSixOyNz를 형성시킴으로써 보다 안정적이고, SiO2보다 고유전율의 게이트 유전막을 형성할 수 있는 반도체 소자의 유전막 형성 방법을 제공하는데 있다.
In order to solve the above problems, the object of the present invention is more stable by injecting Hf source into the surface of silicon substrate by ion implantation method, nitriding it using nitride plasma, and then forming HfSixOyNz through dry oxidation in the furnace process. The present invention provides a method for forming a dielectric film of a semiconductor device capable of forming a gate dielectric film having a higher dielectric constant than that of SiO 2 .
상기한 바와 같은 목적을 달성하기 위해 본 발명은 반도체 소자의 유전막을 형성하는 방법에 있어서, 실리콘 기판 상에 산화막을 형성하는 제 1과정; 상기 산화막이 그 상면에 형성된 실리콘 기판 내에 이온 주입 공정에 의해 Hf를 주입시키는 제 2과정; 상기 Hf가 주입된 실리콘 기판상의 상기 산화막을 제거하는 제 3과정; 상기 산화막이 제거되고 Hf가 주입된 실리콘 기판 상에 N2 주입하여 상기 Hf를 질화시켜 HfSixNy막을 형성하는 제 4과정; 및 상기 질화된 HfSixNy가 형성된 실리콘 기판을 퍼니스 내에서 산화시켜 HfSixOyNz막을 형성시키는 제 5과정을 포함하는 반도체 소자의 유전막 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a method of forming a dielectric film of a semiconductor device, the method comprising: forming an oxide film on a silicon substrate; A second step of injecting Hf into the silicon substrate on which the oxide film is formed by an ion implantation process; A third step of removing the oxide film on the silicon substrate implanted with the Hf; A fourth step of forming an HfSixNy film by nitriding the Hf by injecting N 2 onto the silicon substrate on which the oxide film is removed and Hf is injected; And a fifth process of oxidizing the nitrided HfSixNy-formed silicon substrate in a furnace to form an HfSixOyNz film.
여기서, 상기 제 4 과정 또는 제 5 과정에 의해 형성된 막을 스택구조의 게이트 유전막을 형성할 때 확산 장벽막으로 사용하는 것이 바람직하다.Here, it is preferable to use the film formed by the fourth process or the fifth process as a diffusion barrier film when forming the gate dielectric film of the stacked structure.
또한, 상기 N2 주입은 플라즈마 처리 또는 이온 주입 방법을 사용하여 진행하는 것이 바람직하다.In addition, the N 2 implantation is preferably performed using a plasma treatment or an ion implantation method.
또한, 상기 제 4과정 이후에 O3를 사용하거나 O2 플라즈마 리액티브 방식을 사용하여 HfSixOyNz막을 형성시키는 과정을 더 포함하거나, 제 4과정 이후에 열처리 과정을 더 포함하는 것이 바람직하다.
In addition, the method further includes forming a HfSixOyNz film by using O 3 or using an O 2 plasma reactive method after the fourth process, or further including a heat treatment process after the fourth process.
이하 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 반도체 소자의 유전막 형성방법에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. Hereinafter, a method for forming a dielectric film of a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the present invention.
도면에서 여러 층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다.In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity.
도 1은 산화막 형성 전의 실리콘 기판의 단면도이고, 도 2는 도 1의 실리콘 기판 상에 스크린 산화막이 형성된 단면도이다.1 is a cross-sectional view of a silicon substrate before oxide film formation, and FIG. 2 is a cross-sectional view of a screen oxide film formed on the silicon substrate of FIG. 1.
이에 도시한 바와 같이, 실리콘 기판(10) 상에 산화막으로 스크린 산화막 (12)을 형성한다.As shown in the figure, a
도 3은 도 2의 실리콘 기판 내에 Hf가 주입된 단면도로, 스크린 산화막(12)이 형성된 실리콘 기판(10) 내에 이온 주입 공정에 의해 Hf(14)를 주입시킨다.FIG. 3 is a cross-sectional view in which Hf is injected into the silicon substrate of FIG. 2. The
도 4는 도 3의 실리콘 기판 상의 스크린 산화막이 제거된 상태를 나타낸 단면도로, Hf(14)가 주입된 실리콘 기판(10) 상에서 상기 스크린 산화막(12)을 제거한다.4 is a cross-sectional view illustrating a state in which a screen oxide film on the silicon substrate of FIG. 3 is removed, and the
도 5는 도 4의 실리콘 기판이 플라즈마 처리에 의해 질화된 상태를 나타낸 단면도로, 상기 스크린 산화막(12)이 제거되고 Hf(14)가 주입된 실리콘 기판(10) 상에 플라즈마 처리를 시행하여 상기 Hf(14)를 질화(Nitridation)시켜 HfSixNy를 형성한다.FIG. 5 is a cross-sectional view illustrating a state in which the silicon substrate of FIG. 4 is nitrided by plasma treatment, and plasma treatment is performed on the
도 6은 도 5의 실리콘 기판이 퍼니스에서 산화처리된 상태를 나타낸 단면도로, 상기 질화된 HfSixNy가 형성된 실리콘 기판(10)을 퍼니스에 산화시켜(Oxidation) HfSixOyNz를 형성한다.FIG. 6 is a cross-sectional view illustrating a state in which the silicon substrate of FIG. 5 is oxidized in the furnace. The
앞서 설명한 바와 같이, 상기 본 발명의 실시예에 따르면 Hf 주입한 후, 질화시킴으로써 HfSiON을 형성한 후 상분리를 제어할 수 있으며, 퍼니스에서 건식 산화를 통하여 치밀한 구조의 HfSixOyNz을 형성함으로써 고유전율과 낮은 누설전류특성을 가지는 게이트 유전막을 형성할 수 있다.As described above, according to the embodiment of the present invention, after Hf injection, it is possible to control the phase separation after forming HfSiON by nitriding and forming HfSixOyNz of dense structure through dry oxidation in the furnace. A gate dielectric film having a current characteristic can be formed.
이상에서 본 발명의 바람직한 실시예에 대하여 상세하게 설명하였지만 본 발명의 권리범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량 형태 또한 본 발명의 권리범위에 속하는 것이다.
Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of right.
상기 설명한 바와 같이, 본 발명에 따른 반도체 소자의 유전막 형성 방법에 의하면, HfSixOyNz를 사용함으로써 HfSixOyNz 막에서 전반적으로 균일한 O와 N을 가지고 있는 관계로 O2의 상호확산(interdiffusion)을 방지할 수 있으므로 계면층에서의 낮은 유전상수값을 가지는 물질의 생성을 억제할 수 있는 효과가 있다.As described above, according to the method of forming the dielectric film of the semiconductor device according to the present invention, since HfSixOyNz is used, interdiffusion of O 2 can be prevented since the overall HfSixOyNz film has uniform O and N. There is an effect that can suppress the production of a material having a low dielectric constant in the interface layer.
또한, 비슷한 HfO2 대비 HfSixOyNz가 실리콘(Si)에 대해 비슷한 격자상수를 가지므로 계면에서의 트랩 전하 또한 상대적으로 적으므로 문턱전압이 제어가 상대적으로 용이한 효과가 있다.In addition, since HfSixOyNz has a similar lattice constant with respect to silicon (Si) compared to similar HfO 2 , the trap charge at the interface is also relatively small, so that the threshold voltage is relatively easy to control.
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| JP2004186567A (en) | 2002-12-05 | 2004-07-02 | Toshiba Corp | Semiconductor device and manufacturing method of semiconductor device |
| KR20040060416A (en) * | 2002-12-30 | 2004-07-06 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR20040059878A (en) * | 2002-12-30 | 2004-07-06 | 주식회사 하이닉스반도체 | Method of forming insulating thin film for semiconductor device |
| JP2004193150A (en) | 2002-12-06 | 2004-07-08 | Toshiba Corp | Semiconductor device and its manufacturing method |
| JP2004241725A (en) | 2003-02-07 | 2004-08-26 | Toshiba Corp | Semiconductor device and its manufacturing method |
| US20050023625A1 (en) | 2002-08-28 | 2005-02-03 | Micron Technology, Inc. | Atomic layer deposited HfSiON dielectric films |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050023625A1 (en) | 2002-08-28 | 2005-02-03 | Micron Technology, Inc. | Atomic layer deposited HfSiON dielectric films |
| JP2004186567A (en) | 2002-12-05 | 2004-07-02 | Toshiba Corp | Semiconductor device and manufacturing method of semiconductor device |
| JP2004193150A (en) | 2002-12-06 | 2004-07-08 | Toshiba Corp | Semiconductor device and its manufacturing method |
| KR20040060416A (en) * | 2002-12-30 | 2004-07-06 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR20040059878A (en) * | 2002-12-30 | 2004-07-06 | 주식회사 하이닉스반도체 | Method of forming insulating thin film for semiconductor device |
| JP2004241725A (en) | 2003-02-07 | 2004-08-26 | Toshiba Corp | Semiconductor device and its manufacturing method |
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