KR19980060612A - Capacitor Manufacturing Method of Semiconductor - Google Patents
Capacitor Manufacturing Method of Semiconductor Download PDFInfo
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- KR19980060612A KR19980060612A KR1019960079974A KR19960079974A KR19980060612A KR 19980060612 A KR19980060612 A KR 19980060612A KR 1019960079974 A KR1019960079974 A KR 1019960079974A KR 19960079974 A KR19960079974 A KR 19960079974A KR 19980060612 A KR19980060612 A KR 19980060612A
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Abstract
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 반도체 기판의 콘택플러그 상부에 확산방지막으로 티타늄/티타늄질화막을 형성하고, 상기 티타늄질화막 TDMAT, TEMAT, TDEAT 등의 금속유기 전구체를 사용하여 MOCVD 방법으로 형성한 다음, 상기 티타늄질화막의 일부를 플라즈마 처리하여 반응물 형성에 따른 오동작을 방지하여 반도체 소자의 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a titanium / titanium nitride film is formed as a diffusion barrier on a contact plug of a semiconductor substrate, and a metal organic precursor such as titanium nitride film TDMAT, TEMAT, TDEAT, etc., is used as a MOCVD method. After forming, the present invention relates to a technique of improving a reliability of a semiconductor device by preventing a malfunction caused by reactant formation by plasma treatment of a part of the titanium nitride film.
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 보다 상세하게는 반도체 기판의 콘택플러그 상부에 확산방지막으로 티타늄/티타늄질화막을 형성하는데, 이때 티타늄질화막을 MOCVD법으로 형성하여 캐패시터를 형성함으로써 전기전도도를 안정적으로 유지하여 반도체 소자의 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to form a titanium / titanium nitride film as a diffusion barrier on the contact plug of a semiconductor substrate, wherein the titanium nitride film is formed by MOCVD to form a capacitor. The present invention relates to a technology for improving the reliability of a semiconductor device by keeping it stable.
일반적으로, 반도체 소자의 고집적화됨에 따라 캐패시터에 요구되는 정전용량이 증대되어 고유전상수의 캐패시터로서 SrTiO3및 (Ba,Sr)TiO3의 개발이 한창 진행되고 있다.In general, as semiconductor devices are highly integrated, capacitance required for capacitors is increased, and development of SrTiO 3 and (Ba, Sr) TiO 3 as capacitors having high dielectric constants is in full swing.
또한, 이와 병행하여 고유전율 박막의 하부구조에서 플러그다결정 실리콘과 하부전극 사이에 열 또는 응력방지용막으로 티타늄/티타늄질화막이 사용되는데 이는 캐패시터의 전기적특성을 좌우하게 된다.In addition, a titanium / titanium nitride film is used as a thermal or stress preventing film between the plug polycrystalline silicon and the lower electrode in the lower structure of the high dielectric constant thin film, which influences the electrical characteristics of the capacitor.
그런데, SrTiO3및 (Ba, Sr)TiO3등과 같은 고유전율 박막의 고밀도 반도체 소자에서 Pt, RuO2/Ru 같은 하부전극을 고유전체막의 전극으로 사용할 때 캐패시터의 제조 및 열처리 공정에 의해 콘택플러그의 다결정 실리콘과 하부전극과의 실리사이드막의 형성을 억제하기 위해 스퍼터법(sputter)으로 티타늄질화막을 형성하는데, 이때 티타늄질화막은 확산장벽의 특성이 저하되고 스텝커버리지(step coverage)가 우수하지 못하여 반도체 소자의 신뢰성이 저하되는 문제점이 있다.However, when a lower electrode such as Pt and RuO 2 / Ru is used as the electrode of the high dielectric film in a high-density semiconductor device of a high dielectric constant thin film such as SrTiO 3 and (Ba, Sr) TiO 3 , the contact plug may be In order to suppress the formation of the silicide film between the polycrystalline silicon and the lower electrode, a titanium nitride film is formed by a sputtering method. In this case, the titanium nitride film has a poor diffusion barrier property and poor step coverage. There is a problem that the reliability is lowered.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 반도체 기판의 콘택플러그 상부에 확산방지막으로 티타늄(Ti)/티타늄질화(TiN)막을 형성하고, 상기 티타늄질화막을 TDEAT(Tetra Kis Di Ethyl amino titanime; Ti[N(C2H5)2]4), TDMAT(Tetra Kis Di Methyl amino titanime; Ti[N(CH3)2]4), 또는 TEMAT(Tetra Kis Di Ethyl Methyl amino titanime) 등의 금속유기 전구체를 사용하여 MOCVD(Metal Organic Chemical Vapor Deposition) 방법으로 형성한 다음, 상기 티타늄질화막(TiN)의 일부를 플라즈마 처리함으로써 반응물 형성에 따른 소자의 오동작을 방지하여 반도체 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems to form a titanium (Ti) / titanium nitride (TiN) film as a diffusion barrier on the contact plug of the semiconductor substrate, the titanium nitride film TDEAT (Tetra Kis Di Ethyl amino titanime; Metal organic compounds such as Ti [N (C 2 H 5 ) 2 ] 4 ), TDMAT (Tetra Kis Di Methyl amino titanime; Ti [N (CH 3 ) 2 ] 4 ), or TEMAT (Tetra Kis Di Ethyl Methyl amino titanime) After forming a precursor by using a metal organic chemical vapor deposition (MOCVD) method using a precursor, plasma treatment of a part of the titanium nitride film (TiN) to prevent the malfunction of the device due to the formation of the reactant semiconductor to improve the reliability of the semiconductor device It is an object of the present invention to provide a method for manufacturing a capacitor of a device.
도 1은 본 발명에 따른 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10:반도체 기판 12:절연막10: semiconductor substrate 12: insulating film
14:콘택플러그 16:제1확산방지막14: contact plug 16: first diffusion barrier
18:제2확산방지막 20:도전층18: second diffusion barrier 20: conductive layer
22:유전체막 24:플레이트전극22: dielectric film 24: plate electrode
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 캐패시터 제조방법은Capacitor manufacturing method of a semiconductor device according to the present invention to achieve the above object
반도체 기판 상부에 저장전극 콘택홀을 구비하는 절연막을 형성하는 공정과,Forming an insulating film having a storage electrode contact hole on the semiconductor substrate;
상기 콘택홀을 메우는 콘택플러그를 형성하는 공정과,Forming a contact plug filling the contact hole;
상기 콘택플러그 상부에 Ti/TiN 적층 구조로된 확산방지막패턴을 형성하되, 상기 TiN층은 플라즈마 처리되어 있는 것을 특징으로 한다.A diffusion barrier layer pattern having a Ti / TiN layer structure is formed on the contact plug, and the TiN layer is plasma-processed.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 캐패시터 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 반도체 소자의 캐패시터 제조공정도이다.1 is a manufacturing process diagram of a capacitor of a semiconductor device according to the present invention.
먼저, 반도체 기판(10)에 소자분리 절연막(도시 않됨), 게이트산화막(도시 않됨), 게이트전극(도시 않됨) 및 비트라인(도시 않됨)등의 하부 구조물등이 형성되어 있는 전 표면에 절연막(12)을 형성한다.First, an insulating film (not shown), a gate oxide film (not shown), a gate electrode (not shown), and a lower structure such as a bit line (not shown) are formed on the semiconductor substrate 10. 12) form.
다음, 상기 절연막(12)을 콘택마스크를 이용하여 식각하여 콘택홀을 형성한다.Next, the insulating layer 12 is etched using a contact mask to form a contact hole.
그 다음, 상기 콘택홀구조의 전표면에 500~3000Å 두께의 다결정 실리콘막(도시 않됨)을 화학기상증착법으로 형성한 다음, 상기 다결정 실리콘막을 전면 식각하여 상기 콘택홀을 메우는 콘택플러그(14)를 형성한다.Next, a 500-3000 mm thick polycrystalline silicon film (not shown) is formed on the entire surface of the contact hole structure by chemical vapor deposition, and then the contact plug 14 for filling the contact hole is formed by etching the entire polycrystalline silicon film. Form.
다음, 상기 구조의 전표면에 100~1000Å 두께의 티타늄(Ti)으로 이루어진 제1확산방지막(16)을 형성한다.Next, a first diffusion barrier film 16 made of titanium (Ti) having a thickness of 100 ~ 1000Å is formed on the entire surface of the structure.
그 다음, 상기 제1확산방지막(16) 상부에 100~1000Å 두께의 티타늄질화막(TiN)으로 이루어진 제2확산방지막(18)을 형성한다.Next, a second diffusion barrier layer 18 formed of a titanium nitride layer (TiN) having a thickness of 100 ~ 1000Å over the first diffusion barrier layer 16 is formed.
여기서, 상기 제2확산막(18)의 TiN막은 TDMAT TEMAT, TDEAT의 금속유기(Metal-Organic) 전구체를 사용하여 MOCVD법으로 형성한다.Here, the TiN film of the second diffusion film 18 is formed by using a metal-organic precursor of TDMAT TEMAT and TDEAT by MOCVD.
또한, 전기전도도가 우수하며 확산장벽 및 내산화 특성이 우수한 막을 형성하기 위하여 용도에 따라 CVD-TiN막을 플라즈마 처리하여 형성할 수 있다.In addition, in order to form a film having excellent electrical conductivity and excellent diffusion barrier and oxidation resistance, the CVD-TiN film may be formed by plasma treatment depending on the application.
예를 들면, 상기 제2확산방지막(18)의 TiN막을 CVD-TiN/플라즈마 처리된 CVD-TiN막으로 형성할 수 있고, 플라즈마 처리된 CVD-TiN막/CVD-TiN/플라즈마 처리된 CVD-TiN막으로 형성할 수 있으며, CVD-TiN막/플라즈마 처리된 CVD-TiN/CVD-TiN막을 형성함으로써 대기 노출시에 산소 등의 흡기를 억제시켜 비저항을 증가되는 것을 방지할 수 있다.For example, the TiN film of the second diffusion barrier film 18 may be formed of a CVD-TiN / plasma-treated CVD-TiN film, and the plasma-treated CVD-TiN film / CVD-TiN / plasma-treated CVD-TiN It can be formed into a film, and by forming a CVD-TiN film / plasma-treated CVD-TiN / CVD-TiN film, it is possible to prevent intake of oxygen or the like at the time of exposure to the air and to prevent the increase in specific resistance.
이때, 상기 플라즈마 처리된 CVD-TiN막은 30Å~500Å 두께로 형성한다.At this time, the plasma-treated CVD-TiN film is formed to a thickness of 30 ~ 500Å.
다음, 노광마스크를 이용한 사진 식각공정으로 상기 절연막(12)의 상부표면이 노출될 때까지 식각하여 제2확산방지막(18)패턴 및 제1확산방지막(16)패턴을 형성한다.Next, in the photolithography process using an exposure mask, the second diffusion barrier 18 pattern and the first diffusion barrier 16 pattern are formed by etching until the upper surface of the insulating layer 12 is exposed.
그 다음, 상기 제2확산방지막(18) 및 제1확산방지막(16)을 제거한 후, 전표면에 플라티늄(Pt)으로 이루어진 도전층(20)을 형성하여 상기 콘택플러그(14)와 확산방지막(16,18)패턴 및 도전층(20)으로 구성된 저장전극을 형성한다.Then, after removing the second diffusion barrier film 18 and the first diffusion barrier film 16, a conductive layer 20 made of platinum (Pt) is formed on the entire surface of the contact plug 14 and the diffusion barrier film ( 16 and 18 to form a storage electrode consisting of a pattern and a conductive layer (20).
다음, 상기 구조의 전표면에 PbTiO3, PbZr1-XTiXO3, PbLa1-XZrXTiO3, SrBi2Ta2O9, Bi4Ti3O12, BaTiO3, Ba1-XSrXTiO3, SrTiO3막등의 재질로 이루어진 유전체막(22)을 형성한다.Next, PbTiO 3 , PbZr 1-X Ti X O 3 , PbLa 1-X Zr X TiO 3 , SrBi 2 Ta 2 O 9 , Bi 4 Ti 3 O 12 , BaTiO 3 , Ba 1-X on the entire surface of the structure A dielectric film 22 made of a material such as Sr X TiO 3 and SrTiO 3 is formed.
그 다음, 상기 유전체막(22) 상부에 플라티늄(Pt)으로 이루어진 플레이트 전극(28)을 형성하여 캐패시터를 형성함으로써 반도체 소자의 신뢰성을 향상시키는 본 발명에 따른 캐패시터 제조공정을 완료한다(도 1 참조).Next, a capacitor manufacturing process is performed on the dielectric film 22 to form a plate electrode 28 made of platinum (Pt), thereby completing a capacitor manufacturing process according to the present invention, which improves reliability of a semiconductor device (see FIG. 1). ).
상기한 바와 같이 본 발명에 따른 반도체 소자의 캐패시터 제조방법은 콘택플러그 상부에 확산방지막 MOCVD-TiN막을 형성하고, 상기 티타늄질화막(TiN)의 일부를 플라즈마처리하여 캐패시터를 형성함으로써 반응물 형성에 따른 소자의 오동작을 방지하여 반도체 소자의 신뢰성을 향상시키는 효과가 있다.As described above, in the method of manufacturing a capacitor of a semiconductor device according to the present invention, a diffusion barrier MOCVD-TiN film is formed on a contact plug, and a portion of the titanium nitride film (TiN) is plasma-treated to form a capacitor, thereby forming a capacitor. There is an effect of preventing malfunction to improve the reliability of the semiconductor device.
Claims (5)
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| KR1019960079974A KR19980060612A (en) | 1996-12-31 | 1996-12-31 | Capacitor Manufacturing Method of Semiconductor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020052474A (en) * | 2000-12-26 | 2002-07-04 | 박종섭 | A method for forming a capacitor of a semiconductor device |
| KR100691495B1 (en) * | 1999-07-24 | 2007-03-09 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
| US7374953B2 (en) | 2004-08-16 | 2008-05-20 | Samsung Electronics Co., Ltd. | Ferroelectric random access memories (FRAMS) having lower electrodes respectively self-aligned to node conductive layer patterns and methods of forming the same |
-
1996
- 1996-12-31 KR KR1019960079974A patent/KR19980060612A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100691495B1 (en) * | 1999-07-24 | 2007-03-09 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
| KR20020052474A (en) * | 2000-12-26 | 2002-07-04 | 박종섭 | A method for forming a capacitor of a semiconductor device |
| US7374953B2 (en) | 2004-08-16 | 2008-05-20 | Samsung Electronics Co., Ltd. | Ferroelectric random access memories (FRAMS) having lower electrodes respectively self-aligned to node conductive layer patterns and methods of forming the same |
| US7521746B2 (en) | 2004-08-16 | 2009-04-21 | Samsung Electronics Co., Ltd. | Ferroelectric random access memories (FRAMS) having lower electrodes respectively self-aligned to node conductive layer patterns and methods of forming the same |
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