KR100580747B1 - Method of manufacturing a high dielectric capacitor - Google Patents

Abstract

A method of manufacturing a high dielectric capacitor according to the present invention comprises the steps of: forming a contact hole to expose a junction by patterning an interlayer insulating film formed on a semiconductor substrate, and forming a plug in the contact hole, and forming a first insulating film on the entire upper surface And forming a plate electrode on the first insulating film, forming a second insulating film on the plate electrode, and then sequentially patterning the second insulating film and the plate electrode, and forming a dielectric film on the entire upper surface. And then heat treating, forming a metal layer on the dielectric layer, and then etching the metal layer and the dielectric layer by etching the entire surface of the metal layer and the dielectric layer until the second insulating layer is exposed. Allowing the spacer to remain and removing the exposed first insulating film of the exposed portion After exposing the made by forming a metal layer on the entire upper surface including the plug comprises such a storage electrode of a cylindrical shape connected to the plug is formed by removing a metal layer deposited on said second insulating layer.

Capacitors, high dielectric materials, metal electrodes, metallic oxide films

Description

Method of manufacturing a high dielectric capacitor

1A to 1D are cross-sectional views of a device for explaining a conventional high dielectric capacitor manufacturing method.

2A to 2E are cross-sectional views of devices for explaining a method of manufacturing a high dielectric capacitor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1 and 11: semiconductor substrates 2 and 12 junctions

3 and 13: interlayer insulating films 4 and 14: plug

4a and 14a: polysilicon 4b and 14b: diffusion barrier

5: oxide films 6 and 20: storage electrode

7 and 18: dielectric film 8: metallic oxide film

15 and 17: first and second insulating film 16: plate electrode

19: metal spacer

The present invention relates to a method of manufacturing a high dielectric capacitor of a semiconductor device, and more particularly, to a method of manufacturing a high dielectric capacitor consisting of a metal electrode, a high dielectric material and a metal electrode.

In general, as the degree of integration of semiconductor memory devices such as DRAM increases, the area occupied by memory cells in a chip is rapidly reduced. However, for the operation of the device, a certain amount of capacitance per unit memory cell must be secured. To this end, the development of a process technology that minimizes the area occupied by the capacitor while maintaining the capacitance required for the operation of the memory cell is required. Required.

In order to secure the capacitance necessary for the operation of the device within a limited area, it is necessary to increase the effective surface area of the storage electrode or to use a dielectric having improved dielectric properties. It should have a leakage current characteristic of fA / µm ² or less.

In accordance with these requirements, in the manufacturing process of a device having a memory capacity of 4 gigabytes (G) or more, a high dielectric constant having a higher dielectric constant than a conventional dielectric consisting of an oxide film, a nitride film, and an oxide film is used, and the structure of the capacitor is MIM That is, it is formed in the form of a metal electrode, a high dielectric material and a metal electrode, and also to ensure a sufficient capacitance by making the structure of the storage electrode in the form of a stack (Stack) or cylinder (Cylinder).

Then, the conventional capacitor manufacturing method having the MIM structure of the upper and lower electrodes made of metal will be described with reference to FIGS. 1A to 1D.

In FIG. 1A, after forming an interlayer insulating film 3 on a semiconductor substrate 1 on which a junction part 2 is formed, a contact hole is formed by patterning the interlayer insulating film 3 so that the junction part 2 is exposed. It is sectional drawing of the state which formed the plug 4 in the inside.

Here, the plug 4 has a structure in which a polysilicon 4a and a diffusion barrier 4b are stacked, and the diffusion barrier 4b reduces contact resistance with a metal electrode to be formed thereon. And to prevent the mutual diffusion of the polysilicon (4a) and the metal, for this purpose is formed of Ti / TiN or TiSiN.

FIG. 1B is a cross-sectional view of the oxide film 5 formed on the entire structure including the plug 4 and patterned on the oxide film 5 so that the plug 4 is exposed by using a storage electrode mask. .

FIG. 1C illustrates a cylindrical storage electrode 6 connected to the plug 4 to a patterned portion of the oxide film 5 by removing metal deposited on the oxide film 5 after depositing the metal on the entire upper surface. ) Is a cross-sectional view of a state in which the metal is formed, and as the metal, Ru, Ir, Pt, and the like are used.

FIG. 1D illustrates a dielectric film 7 formed by depositing a high dielectric material such as Ta ₂ O ₅ , (Ba, Sr) TiO ₃ (Barium Strontium Titanate; hereinafter referred to as BST) on the entire upper surface thereof, and then forming the dielectric film 7 7 is a cross-sectional view of the heat treatment state to improve the film quality, and after the heat treatment, a metallic material is formed at the interface between the storage electrode 6 and the dielectric film 7 and at the interface between the diffusion barrier film 4b and the storage electrode 6. An oxide film 8 is produced, where the cause of the metallic oxide film 8 is explained as follows.

High dielectric materials such as Ta ₂ O ₅ , BST and the like are deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Physical vapor deposition (PVD) is a method in which a thin film is deposited on a wafer by flux released by colliding an inert gas with a target having a constant composition ratio. For example, plasma sputtering Fair belongs here. Chemical Vapor Deposition (CVD) is a method in which a thin film is deposited on a wafer by vaporizing a source in a liquid or solid state.

Deposition of BST using physical vapor deposition (PVD) yields a thin film having a dense structure with excellent composition ratio, but the layer coverage is poor due to the straightness of the flux. In addition, when the chemical vapor deposition (CVD) method is used, for example, a good layer covering of about 80% can be obtained at a temperature of 400 ° C, but the layer covering is poor to less than 50% at a temperature of 500 ° C. Therefore, BST is deposited using chemical vapor deposition (CVD), which has better layer covering properties than physical vapor deposition (PVD), but Ta ₂ O _{5, which} has a lower dielectric constant than BST, has also been developed. Therefore, it is possible to deposit by chemical vapor deposition (CVD) method.

On the other hand, the metal organic source (Metal Ogarnic Source) contains a large amount of organic impurities (Organic Impurity) such as carbon (C), hydrogen (H). Therefore, the high dielectric film deposited at low temperature has good layer covering, but has poor crystallinity due to the inclusion of organic impurities. Therefore, after the high dielectric material is deposited, a low temperature heat treatment to remove organic impurities and a high temperature heat treatment to improve the crystallinity of the thin film should be performed. If the heat treatment temperature is too high, silicon (Si) diffuses into the high dielectric film or oxygen (Oxygen) deficiency occurs, and an oxide film 8 is formed at the interface between the metal and the dielectric film due to the characteristics of the metal electrode that easily reacts or diffuses with silicon and oxygen.

Therefore, the characteristics of the dielectric film and the metal electrode are deteriorated by the unnecessary compound (metal oxide film) generated as described above, and thus the electrical characteristics of the capacitor are deteriorated. The reliability is lowered.

Therefore, the present invention forms a plate electrode under the storage electrode and prevents contact between the plug and the electrode made of polysilicon and the diffusion barrier during high temperature heat treatment to improve the film quality of the dielectric film. It is an object to provide a method of manufacturing a capacitor.

The present invention for achieving the above object is to form a contact hole to expose the junction by patterning the interlayer insulating film formed on the semiconductor substrate and to form a plug in the contact hole, the first insulating film formed on the entire upper surface Forming a plate electrode on the first insulating film, forming a second insulating film on the plate electrode, and subsequently patterning the second insulating film and the plate electrode, and forming a dielectric film on the entire upper surface thereof. Post-heat treatment, and after forming the metal layer on the dielectric layer, the dielectric layer and the metal spacer only on the sidewalls of the second insulating layer and the plate electrode patterned by etching the metal layer and the dielectric layer over the entire surface until the second insulating layer is exposed. And the first insulating film of the exposed portion is removed to expose the plug. Forming a metal layer on the entire upper surface including the plug after Keane, and is characterized in that comprises the step of: so that the storage electrode of a cylindrical shape connected to the plug is formed by removing a metal layer deposited on said second insulating layer.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2E are cross-sectional views of devices for explaining a method of manufacturing a high dielectric capacitor according to the present invention.

FIG. 2A illustrates that after forming the interlayer insulating film 13 on the semiconductor substrate 11 on which the junction part 12 is formed, patterning the interlayer insulating film 13 to expose the junction part 12 to form a contact hole and forming the contact hole. It is a cross-sectional view of a state in which the plug 14 is formed, the plug 14 is formed through the following process.

After filling the polysilicon 14a in the contact hole, a part of the polysilicon 14a on the contact hole is removed and titanium (Ti) is deposited on the portion where the polysilicon 14a is removed. The heat treatment is performed such that the contact resistance between the polysilicon 14a and the metal electrode to be connected to the upper portion is reduced so that titanium silicide (TiSix) is formed at the interface between the polysilicon 14a and titanium (Ti), and then the polysilicon ( 14a) deposit TiN, TiAlN or TiSiN on the titanium (Ti) to prevent diffusion of silicon (Si) or oxygen and planarize by etching or chemical mechanical polishing (CMP), for example, Ti The diffusion barrier 14b made of / TiN is formed.

FIG. 2B shows a first insulating film 15 formed over the entire structure including the plug 14 and then physically assembles a metal such as Ru, Pt, RuO ₂ , Ir, IrO _2, etc. on the first insulating film 15. A cross-sectional view showing a plate electrode 16 formed by vapor deposition (PVD) and a second insulating film 17 formed on the plate electrode 16. The first and second insulating films 15 and 17) is formed by depositing a nitride film (SiN or SiON) to a thickness of 200 to 1000 GPa. In addition, the thickness of the plate electrode 16 is adjusted differently according to the type of the dielectric film, it is to be a thickness of 8000 to 12000Å when using Ta ₂ O ₅ , 4000 to 7000Å when using BST.

FIG. 2C illustrates that the second insulating film 17 and the plate electrode 16 are sequentially patterned using the first insulating film 15 as an etch barrier, and then the dielectric film 18 is formed on the entire upper surface. As a cross-sectional view of one state, the dielectric film 18 is formed by depositing a high-k dielectric such as Ta ₂ O ₅ or BST by chemical vapor deposition (CVD) with good layer covering properties, and using Ta ₂ O ₅ . If the thickness of 100 to 250 kPa, BST is to be 150 to 250 kPa.

In addition, after depositing the high dielectric constant by low-temperature heat treatment by an oxygen (O ₂ ) plasma (UV) or UV / O ₃ method at a temperature of 350 to 450 ℃ to remove impurities contained in the high dielectric constant and a temperature of 550 to 800 ℃ Crystallization by high temperature heat treatment in a reactor or rapid thermal treatment (RTP) equipment ensures a compact structure of the membrane.

FIG. 2D illustrates that the metal 19 and the dielectric film 18 are completely covered by the deposition of the metal 19 on the dielectric film 18 to a thickness of 100 to 500 Å until the second insulating film 17 is exposed. The dielectric layer 18 and the metal spacer 19 remain only on the sidewalls of the second and second insulating layers 17 and plate electrodes 16 that are etched and patterned, and then the exposed portions of the first insulating layer 15 are removed. To the plug 14 exposed.

FIG. 2E is a chemical vapor deposition (CVD) method having excellent layer covering properties. The metal 20 is deposited on the entire upper surface including the plug 14 to a thickness of 100 to 500 microseconds, and is then used for electrical separation between memory cells. A cylindrical shape connected to the plug 14 and formed of the metal spacer 19 and the metal 20 by removing the metal 20 deposited on the second insulating layer 17 by a tooth back or chemical mechanical polishing (CMP) process. Is a cross-sectional view of a storage electrode formed thereon.

As described above, in the present invention, the plate electrode 16 is surrounded by a thermally stable nitride film during high temperature heat treatment for improving the film quality of the dielectric film, and is spaced apart from the diffusion preventing film 14b so that unnecessary compounds are not produced and diffused in the electrode 16. The oxidation of the protective film 14b is prevented. In addition, the plate electrode is formed by using a physical vapor deposition (PVD) method with good electrical characteristics.

As described above, the present invention increases the heat treatment temperature and time by forming a plate electrode under the storage electrode and preventing contact between the plug and the electrode made of polysilicon and the diffusion barrier during high temperature heat treatment to improve the film quality of the dielectric film. Can be. Therefore, the film quality of the dielectric film is improved to increase the capacitance of the capacitor, thereby improving the electrical characteristics of the device. Therefore, by using the present invention, the cell size can be reduced according to the improvement of the dielectric constant, so that the integration of the device is easy, and the capacitance between the metal layers is reduced during the metallization process, thereby increasing the operation speed of the device.

Claims (9)

Patterning an interlayer insulating film formed on the semiconductor substrate to form a contact hole so that the junction is exposed and forming a plug in the contact hole; Forming a plate electrode on the first insulating film after forming the first insulating film on the entire upper surface; Forming a second insulating film on the plate electrode and subsequently patterning the second insulating film and the plate electrode; Forming a dielectric film on the entire upper surface and then performing heat treatment; Forming a metal layer on the dielectric film, and then etching the metal layer and the dielectric film over the entire surface until the second insulating film is exposed so that the dielectric film and the metal spacer remain only on sidewalls of the patterned second insulating film and the plate electrode; , After exposing the plug by removing the exposed first insulating film, the metal layer is formed on the entire upper surface including the plug, and the metal layer deposited on the second insulating film is removed to store the cylinder. A method of manufacturing a high dielectric capacitor, comprising the step of forming an electrode. The method of claim 1, The plug is a method of manufacturing a high-k dielectric capacitor, characterized in that the polysilicon and the diffusion barrier is laminated. The method of claim 2, The diffusion barrier is a method of manufacturing a high dielectric capacitor, characterized in that any one of TiN, TiAlN and TiSiN. The method of claim 1, The first and second insulating film is made of a nitride film, a method of manufacturing a high dielectric capacitor, characterized in that formed to a thickness of 200 to 1000Å. The method of claim 1, The plate electrode is made of any one metal of Ru, Pt, RuO ₂ , Ir, IrO ₂ , the metal is a method of manufacturing a high-k dielectric capacitor, characterized in that the deposition by physical vapor deposition method. The method of claim 1, The dielectric film is made of Ta ₂ O ₅ , a method of manufacturing a high dielectric capacitor, characterized in that formed in a thickness of 8000 to 12000Å. The method of claim 1, The dielectric film is made of BST, the method of manufacturing a high-k dielectric capacitor, characterized in that formed in a thickness of 4000 to 7000Å. The method of claim 1, The heat treatment is a low temperature heat treatment by any one of oxygen (O ₂ ) plasma (UV) and UV / O ₃ method; Method of manufacturing a high-k dielectric capacitor, characterized in that consisting of a high temperature heat treatment in any one of the reactor and rapid thermal treatment (RTP) equipment. The method of claim 1, The storage electrode is made of any one metal of Ru, Pt, RuO ₂ , Ir, IrO ₂ , the metal is a method of manufacturing a high-k dielectric capacitor, characterized in that the deposition by chemical vapor deposition.

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